As mentioned in Section 5.1, the VREFLO sampling method of mitigating memory cross-talk can be applied to multiple signals per-ADC (unlike the dedicated ADC method). There are some points to consider when setting up this sampling sequence. Figure 5-3 will be used as an example of a scheme where four signals spread across two ADCs all need to benefit from memory cross-talk mitigation using VREFLO sampling.

Consider first that even though the last SOC in each sequence (SCO3 = VREFLO) does not occur immediately before the first sample in the sequence (SOC0 = V1 or V3), for the sake of memory-cross talk it will be the sample influencing the first conversion in the sequence due to the periodic nature of the sampling. Because of this, appending VREFLO to the end of the sequence and making a channel affected by memory cross-talk the first sample in the sequence is an acceptable configuration.

Furthermore, consider where the trigger to the ISR should be placed in the sequence. Normally, the last SOC in the sequence would trigger the ISR to ensure that all ADC results are ready by the time the CPU enters the ISR. However, there is not need to read the VREFLO conversion results, so the ideal place to place the ISR trigger would be after SOC2, not after SOC3. Because of this, even through two signals are benefiting from VREFLO memory cross-talk mitigation in Figure 5-3, the latency only increases by the time needed to take one VREFLO sample, not two (the latency of the VREFLO conversion at the end of the sequence can be masked).