SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The PCIe PHY APLL_PCIE clock generator receive hardware non-retention reset, COREAON_PWRON_RST, which comes from the device power and reset manager. For more information on the hardware reset source, see Reset Domains in Power, Reset, and Clock Management.
The APLL_PCIE itself has no software reset capabilities.