SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Register Name | Type | Register Width (Bits) | Address Offset | CM_CORE_AON__RESTORE Physical Address L4_CFG Interconnect |
---|---|---|---|---|
CM_CLKSEL_CORE_RESTORE | RW | 32 | 0x0000 0000 | 0x4A00 5E00 |
CM_DIV_M2_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0004 | 0x4A00 5E04 |
CM_DIV_M3_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0008 | 0x4A00 5E08 |
CM_DIV_H11_DPLL_CORE_RESTORE | RW | 32 | 0x0000 000C | 0x4A00 5E0C |
CM_DIV_H12_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0010 | 0x4A00 5E10 |
CM_DIV_H13_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0014 | 0x4A00 5E14 |
CM_DIV_H14_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0018 | 0x4A00 5E18 |
CM_DIV_H21_DPLL_CORE_RESTORE | RW | 32 | 0x0000 001C | 0x4A00 5E1C |
CM_DIV_H22_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0020 | 0x4A00 5E20 |
CM_DIV_H23_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0024 | 0x4A00 5E24 |
CM_DIV_H24_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0028 | 0x4A00 5E28 |
CM_CLKSEL_DPLL_CORE_RESTORE | RW | 32 | 0x0000 002C | 0x4A00 5E2C |
CM_SSC_DELTAMSTEP_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0030 | 0x4A00 5E30 |
CM_SSC_MODFREQDIV_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0034 | 0x4A00 5E34 |
CM_CLKMODE_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0038 | 0x4A00 5E38 |
CM_SHADOW_FREQ_CONFIG2_RESTORE | RW | 32 | 0x0000 003C | 0x4A00 5E3C |
CM_SHADOW_FREQ_CONFIG1_RESTORE | RW | 32 | 0x0000 0040 | 0x4A00 5E40 |
CM_AUTOIDLE_DPLL_CORE_RESTORE | RW | 32 | 0x0000 0044 | 0x4A00 5E44 |
CM_MPU_CLKSTCTRL_RESTORE | RW | 32 | 0x0000 0048 | 0x4A00 5E48 |
CM_CM_CORE_AON_PROFILING_CLKCTRL_RESTORE | RW | 32 | 0x0000 004C | 0x4A00 5E4C |
CM_DYN_DEP_PRESCAL_RESTORE | RW | 32 | 0x0000 0050 | 0x4A00 5E50 |