SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The wake-up events can be asynchronous or synchronous. Synchronous wake-up events require the 32-kHz clock or the system clock to be active, while asynchronous wake-up events do not require an active clock.
The Modules Attributes subsection of each clock domain in Section 3.6, Clock Management Functional Description, describes the wake-up capability support for each module of the corresponding power domain.
While the device is in STANDBY mode, additional asynchronous wakeup events from other domains are able to wake up the device.
Table 3-364 identifies which modules in which power domains can be configured to generate a wake-up while the device is in a low-power mode.
These modules are not supported on this familyAM571x and AM570x families of devices:
MLB
These modules are not supported on the AM570x family of devices only:
Device Power Mode name | VD_RTC VOLTAGE STATE | VD_CORE VOLTAGE STATE | VD_MPU VOLTAGE (2)STATE | VD_GPU (2)VOLTAGE STATE | VD_IVAHD VOLTAGE STATE | VD_DSPEVE VOLTAGE STATE | Domain containing wake-up source | Wakeup sources |
---|---|---|---|---|---|---|---|---|
Really OFF | OFF | OFF | OFF | OFF | OFF | OFF | N/A | Application of Power Supply and Power on Reset Sequence |
RTC mode | ON | OFF | OFF | OFF | OFF | OFF | RTC SS sends signal to power supply to apply power voltage to all other voltage domains | RTC ("alarm" and "timer" slave wake-up capabilities), EXT_WKUP0, EXT_WKUP3 |
STANDBY | Active Voltage Level | PD_IPU (1) | I2C5, IPU1, MCASP1, TIMER5, TIMER6, TIMER7, TIMER8, UART6 | |||||
PD_CORE | DMA_SYSTEM, IPU2, OCMC_RAM1, EDMA_TPCC, EDMA_TPTC1, EDMA_TPTC2 | |||||||
PD_L3INIT (1) | IEEE1500_2_OCP, MLB_SS, MMC1, MMC2, PCIe_SS1, PCIe_SS2, SATA, USB1, USB2, USB3 | |||||||
PD_L4PER | DCAN2, GPIO2 - GPIO8, I2C1- I2C4, MCASP2 - MCASP8, MCSPI1 - MCSPI4, MMC3, MMC4, QSPI, TIMER2 - TIMER4, TIMER9 -TIMER11, TIMER13 - TIMER16, UART1 - UART9 | |||||||
PD_MPU | MPU | |||||||
PD_DSP1 | DSP1 | |||||||
PD_WKUPAON | DCAN1, GPIO1, KBD, TIMER1, TIMER12, UART10, WD_TIMER2 | |||||||
PD_EMU | (Debug_logic) Any ForceActive directive Dynanic depedency towards L3_MAIN |