SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Address Offset | 0x0000 000C | ||
Physical Address | 0x4A08 440C | Instance | USB3_PHY_RX |
Description | Some programmability for different analog circuits in the PHY. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_ANAMODE | MEM_EN_PLLBYP | MEM_PLLDIV | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:8 | MEM_ANAMODE | Programmability for Analog circuits in the IP. The top 5 bits - MEM_ANAMODE[31:27] indicate the serial Interface using this PHY module. To select USB Super-Speed interface mode, user must set bit MEM_ANAMODE [31] to '0b1', and the other bits must be written to '0b0', as follows: MEM_ANAMODE[31:27] = '0b10000' for the USB Super-Speed. Bits [17:14] of the MEM_ANAMODE bitfield are used to control loss-of-signal detection (LOSD) threshold. | RW | 0x00 0000 |
7 | MEM_EN_PLLBYP | 0: USB Mode (uses PLL_CLK input clock) 1: PCIe Mode (uses PLLBYPCLK input clock) | RW | 0 |
6:5 | MEM_PLLDIV | This is a test mode. SoC Users are requested to leave this at default value. The input PLL_CLK (after being muxed with PLLBYPCLK) is divided by the following factors indicated by this register. 00=1 01=2 10=4 11=RESERVED. All references to PLL_CLK in this register descriptions are AFTER considering this division. | RW | 0x0 |
4:0 | RESERVED | R | 0x00 |
Address Offset | 0x0000 001C | ||
Physical Address | 0x4A08 441C | Instance | USB3_PHY_RX |
Description | The IP requires some values to be remembered in EFUSE. This register provides an alternative to EFUSE. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_DLL_TRIM_SEL | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | MEM_DLL_TRIM_SEL | Determines which of the 4 EFUSE registers EFUSE_dll_rateN_coarsetrim should be used as the trim code by the DLL. This feature is so that the user may find and store the trim codes corresponding to different (at most 4) DLL frequencies (PLL_CLK (after the bypassing by MEM_EN_PLLBYP and the division by MEM_PLLDIV) frequencies) and at wake-up, instruct the IP to choose one of these available trim values depending on the Application's frequency requirement. 00 selects dll_rate0_coarsetrim 01 selects dll_rate1_coarsetrim 10 selects dll_rate2_coarsetrim 11 selects dll_rate3_coarsetrim. | RW | 0x0 |
29:0 | RESERVED | RW | 0x0000 0000 |
Address Offset | 0x0000 0024 | ||
Physical Address | 0x4A08 4424 | Instance | USB3_PHY_RX |
Description | This register is used to program DLL settings. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_DLL_PHINT_RATE | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:30 | MEM_DLL_PHINT_RATE | Programs the DLL and the Phase Interpolator analog circuits to work with different clock frequencies. The frequency of PLL_CLK (after the bypassing by MEM_EN_PLLBYP and the division by MEM_PLLDIV) should be indicated by this register. 00=0.625GHz to 0.75GHz 01=RESERVED 10=1.25GHz to 1.5GHz 11=2.5GHz to 2.9GHz. | RW | 0x3 |
29:0 | RESERVED | R | 0x00A4 1915 |
Address Offset | 0x0000 0028 | ||
Physical Address | 0x4A08 4428 | Instance | USB3_PHY_RX |
Description | This register contains control bits which affect different circuits in digital section of the PHY. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_INV_RXPN_PAIR | MEM_OVRD_INV_RXPN_PAIR | RESERVED | MEM_HS_RATE | MEM_OVRD_HS_RATE | RESERVED | MEM_CDR_FASTLOCK | MEM_CDR_LBW | MEM_CDR_STEPCNT | MEM_CDR_STL | MEM_CDR_THR | MEM_CDR_THR_MODE | MEM_CDR_2NDO_SDM_MODE | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31 | MEM_INV_RXPN_PAIR | If '1', interchanges RXP and RXN effectively by inverting the received data samples. | RW | 0 |
30 | MEM_OVRD_INV_RXPN_PAIR | Pin override control. See register bit MEM_INV_RXPN_PAIR. | RW | 0 |
29 | RESERVED | R | 0 | |
28:27 | MEM_HS_RATE | Determines the ratio of PLL_CLK (after the bypassing by MEM_EN_PLLBYP and the division by MEM_PLLDIV) frequency and the output data rate. Full Rate means PLL_CLK (after the bypassing by MEM_EN_PLLBYP and the division by MEM_PLLDIV) frequency = Data Rate/2 00=Full Rate 01=Half Rate 10=Quarter Rate 11=RESERVED. This takes effect only if register bit MEM_OVRD_HS_RATE is '1', else the same is controlled by input pins hs_rate. | RW | 0x0 |
26 | MEM_OVRD_HS_RATE | Pin override control. See register bit MEM_HS_RATE. | RW | 0 |
25:24 | RESERVED | R | 0x2 | |
23 | MEM_CDR_FASTLOCK | '1' to reduce lock time of CDR (clock-data-recovery circuit). | RW | 1 |
22:21 | MEM_CDR_LBW | CDR band-width control. | RW | 0x3 |
20:19 | MEM_CDR_STEPCNT | CDR 2nd order setting. | RW | 0x0 |
18:16 | MEM_CDR_STL | CDR settling time. Determines the number of vote clocks to blank ELV (Early-Late-Voter circuit) after update of phase. | RW | 0x3 |
15:13 | MEM_CDR_THR | CDR 1st order threshold. Determines how much early/late votes should differ by before a phase change in the receiver sampling clock is triggered. | RW | 0x1 |
12 | MEM_CDR_THR_MODE | CDR 1st order threshold. | RW | 1 |
11 | MEM_CDR_2NDO_SDM_MODE | If '1', the 2nd Order CDR block uses a 1st order Sigma Delta Modulator to accomplish frequency offset If '0', a simple rate transformer is used for the same purpose. | RW | 0 |
10:0 | RESERVED | R | 0x000 |
Address Offset | 0x0000 0038 | ||
Physical Address | 0x4A08 4438 | Instance | USB3_PHY_RX |
Description |
The IP has an Equalizer (with analog and digital parts) which addresses Inter Symbol Interference (ISI). This register is for its controllability. The equalizer can be configured via the EQCTL bits which are part of the SCP register. The options are: No adaptive equalisation. The equalizer provides a flat response at the maximum gain. This setting may be appropriate if jitter at the receiver occurs predominantly as a result of crosstalk rather than frequency dependent loss. Fully adaptive equalisation. Both the low frequency gain and zero position of the equalizer are determined algorithmically by analysing the data patterns and transition positions in the received data. This setting should be used for most applications. Partially adaptive equalisation. The low frequency gain of the equalizer is determined algorithmically by analysing the data patterns and transition positions in the received data. The zero position is fixed in one of eight zero positions. When enabled, the receiver equalization logic analyzes data patterns and transition times to determine whether the low frequency gain of the equalizer should be increased or decreased. For the fully adaptive setting (EQCTL = 0001), if the low frequency gain reaches the minimum value, the zero frequency is then reduced. Likewise, if it reaches the maximum value, the zero frequency is then increased. | ||
Type | RW |
31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
MEM_EQLEV | MEM_EQFTC | MEM_EQCTL | RESERVED | MEM_OVRD_EQLEV | MEM_OVRD_EQFTC | RESERVED |
Bits | Field Name | Description | Type | Reset |
---|---|---|---|---|
31:16 | MEM_EQLEV | Equalizer level control. | RW | 0x0000 |
15:11 | MEM_EQFTC | Equalizer zero freq control. | RW | 0x00 |
10:7 | MEM_EQCTL | 0000 - Equalizer disabled 0001 - Fully adaptive; FTC normal 0010 - Fully adaptive; FTC inverted 0011 - Hold eq state 01xx - Init eq to fully adaptive start/midpoint 1000 - Partially adaptive; zero=1084 MHz 1001 - Partially adaptive; zero= 805 MHz 1010 - Partially adaptive; zero= 573 MHz 1011 - Partially adaptive; zero= 402 MHZ 1100 - Partially adaptive; zero= 304 MHz 1101 - Partially adaptive; zero= 216 MHz 1110 - Partially adaptive; zero= 156 MHz 1111 - Partially adaptive; zero= 135 MHz | RW | 0x0 |
6:3 | RESERVED | R | 0 | |
2 | MEM_OVRD_EQLEV | Continuosly forces the Equalizer output with the eqlev[15:0]. | RW | 0 |
1 | MEM_OVRD_EQFTC | Continuosly forces the Equalizer output with the eqftc[4:0]. | RW | 0 |
0 | RESERVED | R | 0 |