SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The L3 interconnect is divided into two clock domains L3_CLK1 and L3_CLK2. CLK1 domain is further splitted into two sub groups:
The two clock elements (CLK1 and CLK2) are implemented in a different clock domain.