SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Each multimaster HS I2C controller can generate two DMA requests to the device DMA controllers through the DMA_CROSSBAR module. Table 24-11 lists the DMA requests. For information about DMA generation, see Section 24.1.4.8.3, HS I2C FIFO DMA Mode (I2C Mode Only).
Name | Source | Description |
---|---|---|
I2C1_DREQ_TX | I2C1 | I2C1 DMA write request to inform the DMAs to write new data in the I2C1.I2C_DATA[7:0] DATA bit field |
I2C1_DREQ_RX | I2C1 | I2C1 DMA read request to inform the DMAs to read the data in the I2C1.I2C_DATA[7:0] DATA bit field |
I2C2_DREQ_TX | I2C2 | I2C2 DMA write request to inform the DMAs to write new data in the I2C2.I2C_DATA[7:0] DATA bit field |
I2C2_DREQ_RX | I2C2 | I2C2 DMA read request to inform the DMAs to read the data in the I2C2.I2C_DATA[7:0] DATA bit field |
I2C3_DREQ_TX | I2C3 | I2C3 DMA write request to inform the DMAs to write new data in the I2C3.I2C_DATA[7:0] DATA bit field |
I2C3_DREQ_RX | I2C3 | I2C3 DMA read request to inform the DMAs to read the data in the I2C3.I2C_DATA[7:0] DATA bit field |
I2C4_DREQ_TX | I2C4 | I2C4 DMA write request to inform the DMAs to write new data in the I2C4.I2C_DATA[7:0] DATA bit field |
I2C4_DREQ_RX | I2C4 | I2C4 DMA read request to inform the DMAs to read the data in the I2C4.I2C_DATA[7:0] DATA bit field |
I2C6_DREQ_TX | I2C6 | I2C6 DMA write request to inform the DMAs to write new data in the I2C6.I2C_DATA[7:0] DATA bit field |
I2C6_DREQ_RX | I2C6 | I2C6 DMA read request to inform the DMAs to read the data in the I2C6.I2C_DATA[7:0] DATA bit field |
For more information about I2Ci_DREQ_TX and I2Ci_DREQ_RX (where i= 1 to 6)signals mapping to DMA_CROSSBAR, see Section 16.1.3.2Section 16.1.3.2, Mapping of DMA Requests to DMA_CROSSBAR Inputs, in Table 24-4, HS I2C Hardware Requests.