SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The PRU core is little endian. To support big endian, the MII_RT supports optional nibble swapping on both the RX and TX side.
On the receive side, the order of the two data bytes in RX R31 and the RX L2 buffer are configurable through the RX_BYTE_SWAP bit in the PRUSS_MII_RT_RXCFG0/1 registers, as shown in Table 30-280. Note the Nibble0 is the first nibble received.
Configuration | Order |
---|---|
PRUSS_MII_RT_RXCFG0/1 [RX_BYTE_SWAP] = 0 (default) | R31[15:8] / RXL2[15:8] = Byte1{Nibble3,Nibble2} R31[7:0] / RXL2[7:0] = Byte0{Nibble1,Nibble0} |
PRUSS_MII_RT_RXCFG0/1 [RX_BYTE_SWAP] = 1 | R31[15:8] / RXL2[15:8] = Byte0{Nibble1,Nibble0} R31[7:0] / RXL2[7:0] = Byte1{Nibble3,Nibble2} |
On the transmit side, the order of the two data bytes and mask bytes in TX R30 are configurable through the TX_BYTE_SWAP bit in the PRUSS_MII_RT_TXCFG0/1 registers, as shown in Table 30-281. Note the Nibble0 is the first nibble received.
Configuration | Order |
---|---|
PRUSS_MII_RT_TXCFG0/1 [TX_BYTE_SWAP] = 0 (default) | If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0, R30[15:8] = Byte1{Nibble3,Nibble2} R30[7:0] = Byte0{Nibble1,Nibble0} R30[31:24] = TX_MASK[15:8] R30[23:16] = TX_MASK[7:0] If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 1, R30[31:24] = Byte3{Nibble7,Nibble6} R30[23:16] = Byte2{Nibble5,Nibble4} R30[15:8] = Byte1{Nibble3,Nibble2} R30[ 7:0] = Byte0{Nibble1,Nibble0} |
PRUSS_MII_RT_TXCFG0/1 [TX_BYTE_SWAP] = 1 | If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0, R30[15:8] = Byte0{Nibble1,Nibble0} R30[7:0] = Byte1{Nibble3,Nibble2} R30[31:24] = TX_MASK[7:0] R30[23:16] = TX_MASK[15:8] If PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 1, Only 32bit push is supported. R30[31:24] = Byte0{Nibble1,Nibble0} R30[23:16] = Byte1{Nibble3,Nibble2} R30[15:8] = Byte2{Nibble5,Nibble4} R30[ 7:0] = Byte3{Nibble7,Nibble6} |