SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
Table 3-347 lists the power mode controls for the power domain.
Parameter Name | Memory Bank | Control Bit Field | Access Type |
---|---|---|---|
Memory Area – State Control (Logic in ON state) | IPU_UNICACHE | PM_CORE_PWRSTCTRL[23:22] IPU_UNICACHE_ONSTATE | Read only |
Memory Area – State Control (Logic in ON state) | IPU_L2RAM | PM_CORE_PWRSTCTRL[21:20] IPU_L2RAM_ONSTATE | Read only |
Memory Area – State Control (Logic in RETENTION state) | IPU_UNICACHE | PM_CORE_PWRSTCTRL[11] IPU_UNICACHE_RETSTATE | Read/write |
Memory Area – State Control (Logic in RETENTION state) | IPU_L2RAM | PM_CORE_PWRSTCTRL[10] IPU_L2RAM_RETSTATE | Read/write |
Logic Area – RETENTION State Control | N/A | PM_CORE_PWRSTCTRL[2] LOGICRETSTATE | Read/write |
Power Domain – Low-Power State Change Control | N/A | PM_CORE_PWRSTCTRL[4] LOWPOWERSTATECHANGE | Read/write |
Power Domain – State Transition Control | N/A | PM_CORE_PWRSTCTRL[1:0] POWERSTATE | Read/write |
Table 3-348 lists the status of the power modes for the power domain.
Parameter Name | Memory Bank | Status Bit Field |
---|---|---|
Power Domain – Last Power State Entered Status | PM_CORE_PWRSTST[25:24] LASTPOWERSTATEENTERED | |
Memory Area – State Status | IPU_L2RAM | PM_CORE_PWRSTST[9:8] IPU_L2RAM_STATEST |
Memory Area – State Status | IPU_UNICACHE | PM_CORE_PWRSTST[11:10] IPU_UNICACHE_STATEST |
Logic Area – State Status | PM_CORE_PWRSTST[2] LOGICSTATEST | |
Power Domain – State Transition Status | PM_CORE_PWRSTST[20] INTRANSITION | |
Power Domain – State Status | PM_CORE_PWRSTST[1:0] POWERSTATEST |