SPRUHZ7K August 2015 – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL
The PRU uses writes to R31[31:16] to control the reception and transmission of packets in register mode. Table 30-279 lists the available commands. Each bit in the table is a single clock pulse output from the PRU. When more than one action is to be performed in the same instant, the PRU firmware must set those command bits in one instruction.
Bit | Command | Description |
---|---|---|
31 | TX_CRC_ERR | TX_CRC_ERR command when set will add 0xa5 byte to the TX L1 FIFO if the current FCS is valid. This bit can only be set with the TX_EOF command and optionally with the TX_ERROR_NIBBLE command. It cannot get set with any other commands, and the PRU firmware must wait > 2 clocks from the last command. Note for proper operations auto-forward preamble must be enabled. |
30 | TX_RESET | TX_RESET command is used to reset the transmit FIFO and clear all its contents. This is required to recover from a TX FIFO overrun. |
29 | TX_EOF | TX_EOF command is used to indicate that the data loaded is considered last for the current frame |
28 | TX_ERROR_NIBBLE | TX_ERROR_NIBBLE command is used to insert an error nibble. This makes the frame invalid. Also, it will add 0x0 after the 32-bit CRC. |
27 | TX_CRC_HIGH | TX_CRC_HIGH command ends the CRC calculations and pushes CRC[31:16] to append to the outgoing frame in the TX L1 FIFO. Note PRUSS_MII_RT_TX_CRC0/1 will become valid after 6 clock cycles. |
26 | TX_CRC_LOW | TX_CRC_LOW command pushes CRC[15:0] to append to the outgoing frame in the TX L1 FIFO. |
25 | TX_PUSH16 | TX_PUSH16 command pushes R30[15:0] when PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0. See Table x, TX Push for more details. Note there are no restrictions on concurrent PUSH/POP nor R30 requirements to maintain data. Back to back PUSH is supported. |
24 | TX_PUSH8 | TX_PUSH8 command pushes R30[7:0] when PRUSS_MII_RT_TXCFG0/1 [TX_32_MODE_EN] = 0. See Table x, TX Push for more details. Note there are no restrictions on concurrent PUSH/POP nor R30 requirements to maintain data. Back to back PUSH is supported. |
23 | RX_ ERROR_CLR | RX_ERROR_CLR command is used to clear RX_ ERROR indicator bit by writing 1. |
22 | RX_EOF_CLR | RX_EOF_CLR command is used to clear RX_EOF status indicator bit by writing 1. |
21 | RX_SFD_CLR | RX_SFD_CLR command is used to clear RX_SFD indicator bit by writing 1. |
20 | RX_SOF_CLR | RX_SOF_CLR command is used to clear RX_SOF indicator bit by writing 1. |
19 | Reserved | Reserved |
18 | RX_RESET | RX_RESET is used to reset the receive FIFO and clear all contents. This is required to recover from a RX FIFO overrun, if software does not want to undrain. The typical use case is assertion after RX_EOF. If asserted during an active frame, the following actions will occur:
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17 | RX_POP16 | RX_POP16 command advances the receive traffic by two bytes. This is only required when R31 is used to read the data. After R31[15:0] is ready to read by PRU, it will set 1 to WORD_RDY, and the next new data will be allowed to advance. RX_POP16 to WORD_RDY update has 2 clock cycles latency. Firmware needs to insure it does not read WORD_RDY/BYTE_RDY until 2 clock cycles after RX_POP16. |
16 | RX_POP8 | RX_POP8 command advances the receive traffic by one bytes. This is only required when R31 is used to read the data. After R31[7:0] is ready to read by PRU, it will set 1 to BYTE_RDY, and the next new data will be allowed to advance. RX_POP8 to BYTE_RDY update has 2 clock cycles latency. Firmware needs to insure it does not read WORD_RDY/BYTE_RDY until 2 clock cycles after RX_POP8. |