SPRUHZ7K August   2015  – April 2024 AM5706 , AM5708 , AM5716 , AM5718 , AM5718-HIREL

 

  1.   1
  2.   Preface
    1.     Support Resources
    2.     About This Manual
    3.     Information About Cautions and Warnings
    4.     Register, Field, and Bit Calls
    5.     Coding Rules
    6.     Flow Chart Rules
    7.     Export Control Notice
    8.     AM571x, AM570x MIPI® Disclaimer
    9.     Trademarks
  3. 1 Introduction
    1. 1.1 AM571x, AM570x Overview
    2. 1.2 AM571x, AM570x Environment
    3. 1.3 AM571x, AM570x Description
      1. 1.3.1  MPU Subsystem
      2. 1.3.2  DSP Subsystem
      3. 1.3.3  PRU-ICSS
      4. 1.3.4  IPU Subsystems
      5. 1.3.5  IVA-HD Subsystem
      6. 1.3.6  Display Subsystem
      7. 1.3.7  Video Processing Subsystem
      8. 1.3.8  Video Capture
      9. 1.3.9  3D GPU Subsystem
      10. 1.3.10 BB2D Subsystem
      11. 1.3.11 Camera Interface Subsystem
      12. 1.3.12 On-Chip Debug Support
      13. 1.3.13 Power, Reset, and Clock Management
      14. 1.3.14 On-Chip Memory
      15. 1.3.15 Memory Management
      16. 1.3.16 External Memory Interfaces
      17. 1.3.17 System and Connectivity Peripherals
        1. 1.3.17.1 System Peripherals
        2. 1.3.17.2 Media Connectivity Peripherals
        3. 1.3.17.3 Connectivity Peripherals
        4. 1.3.17.4 Audio Connectivity Peripherals
        5. 1.3.17.5 Serial Control Peripherals
    4. 1.4 AM571x, AM570x Family
    5. 1.5 AM571x, AM570x Device Identification
    6. 1.6 AM571x, AM570x Package Characteristics Overview
  4. 2 Memory Mapping
    1. 2.1 Introduction
    2. 2.2 L3_MAIN Memory Map
      1. 2.2.1 L3_INSTR Memory Map
    3. 2.3 L4 Memory Map
      1. 2.3.1 L4_CFG Memory Map
      2. 2.3.2 L4_WKUP Memory Map
      3. 2.3.3 L4_PER Memory Map
        1. 2.3.3.1 L4_PER1 Memory Map
        2. 2.3.3.2 L4_PER2 Memory Map
        3. 2.3.3.3 L4_PER3 Memory Map
    4. 2.4 MPU Memory Map
    5. 2.5 IPU Memory Map
    6. 2.6 DSP Memory Map
    7. 2.7 PRU-ICSS Memory Map
    8. 2.8 TILER View Memory Map
  5. 3 Power, Reset, and Clock Management
    1. 3.1  Device Power Management Introduction
      1. 3.1.1 Device Power-Management Architecture Building Blocks
        1. 3.1.1.1 Clock Management
          1. 3.1.1.1.1 Module Interface and Functional Clocks
          2. 3.1.1.1.2 62
          3. 3.1.1.1.3 Module-Level Clock Management
          4. 3.1.1.1.4 Clock Domain
          5. 3.1.1.1.5 Clock Domain-Level Clock Management
          6. 3.1.1.1.6 Clock Domain HW_AUTO Mode Sequences
          7. 3.1.1.1.7 Clock Domain Sleep/Wake-up
          8. 3.1.1.1.8 Clock Domain Dependency
            1. 3.1.1.1.8.1 Static Dependency
            2. 3.1.1.1.8.2 Dynamic Dependency
            3. 3.1.1.1.8.3 Wake-Up Dependency
        2. 3.1.1.2 Power Management
          1. 3.1.1.2.1 Power Domain
          2. 3.1.1.2.2 Module Logic and Memory Context
          3. 3.1.1.2.3 Power Domain Management
        3. 3.1.1.3 Voltage Management
          1. 3.1.1.3.1 Voltage Domain
          2. 3.1.1.3.2 Voltage Domain Management
          3. 3.1.1.3.3 AVS Overview
            1. 3.1.1.3.3.1 AVS Class 0 (SmartReflex™) Voltage Control
      2. 3.1.2 Power-Management Techniques
        1. 3.1.2.1 Standby Leakage Management
        2. 3.1.2.2 Dynamic Voltage and Frequency Scaling
        3. 3.1.2.3 Dynamic Power Switching
        4. 3.1.2.4 Adaptive Voltage Scaling
        5. 3.1.2.5 Adaptive Body Bias
        6. 3.1.2.6 87
        7. 3.1.2.7 SR3-APG (Automatic Power Gating)
        8. 3.1.2.8 Combining Power-Management Techniques
          1. 3.1.2.8.1 DPS Versus SLM
    2. 3.2  PRCM Subsystem Overview
      1. 3.2.1 Introduction
      2. 3.2.2 Power-Management Framework Features
    3. 3.3  PRCM Subsystem Environment
      1. 3.3.1 External Clock Signals
      2. 3.3.2 External Boot Signals
      3. 3.3.3 External Reset Signals
      4. 3.3.4 External Voltage Inputs
    4. 3.4  PRCM Subsystem Integration
      1. 3.4.1 Device Power-Management Layout
      2. 3.4.2 Power-Management Scheme, Reset, and Interrupt Requests
        1. 3.4.2.1 Power Domain
        2. 3.4.2.2 Resets
        3. 3.4.2.3 PRCM Interrupt Requests
        4. 3.4.2.4 105
    5. 3.5  Reset Management Functional Description
      1. 3.5.1 Overview
        1. 3.5.1.1 PRCM Reset Management Functional Description
          1. 3.5.1.1.1 Power-On Reset
          2. 3.5.1.1.2 Warm Reset
        2. 3.5.1.2 PRM Reset Management Functional Description
      2. 3.5.2 General Characteristics of Reset Signals
        1. 3.5.2.1 Scope
        2. 3.5.2.2 Occurrence
        3. 3.5.2.3 Source Type
        4. 3.5.2.4 Retention Type
      3. 3.5.3 Reset Sources
        1. 3.5.3.1 Global Reset Sources
        2. 3.5.3.2 Local Reset Sources
      4. 3.5.4 Reset Logging
      5. 3.5.5 Reset Domains
      6. 3.5.6 Reset Sequences
        1. 3.5.6.1  MPU Subsystem Power-On Reset Sequence
        2. 3.5.6.2  MPU Subsystem Warm Reset Sequence
        3. 3.5.6.3  MPU Subsystem Reset Sequence on Sleep and Wake-Up Transitions From RETENTION State
        4. 3.5.6.4  IVA Subsystem Power-On Reset Sequence
        5. 3.5.6.5  IVA Subsystem Software Warm Reset Sequence
        6. 3.5.6.6  DSP1 Subsystem Power-On Reset Sequence
        7. 3.5.6.7  DSP1 Subsystem Software Warm Reset Sequence
        8. 3.5.6.8  IPU1 Subsystem Power-On Reset Sequence
        9. 3.5.6.9  IPU1 Subsystem Software Warm Reset Sequence
        10. 3.5.6.10 IPU2 Subsystem Power-On Reset Sequence
        11. 3.5.6.11 IPU2 Subsystem Software Warm Reset Sequence
        12. 3.5.6.12 Global Warm Reset Sequence
    6. 3.6  Clock Management Functional Description
      1. 3.6.1 Overview
      2. 3.6.2 External Clock Inputs
        1. 3.6.2.1 FUNC_32K_CLK Clock
        2. 3.6.2.2 High-Frequency System Clock Input
        3. 3.6.2.3 External Reference Clock Input
      3. 3.6.3 Internal Clock Sources and Generators
        1. 3.6.3.1  PRM Clock Source
        2. 3.6.3.2  CM Clock Source
          1. 3.6.3.2.1 CM_CORE_AON Clock Generator
          2. 3.6.3.2.2 CM_CORE_AON_CLKOUTMUX Overview
          3. 3.6.3.2.3 CM_CORE_AON_TIMER Overview
          4. 3.6.3.2.4 CM_CORE_AON_MCASP Overview
        3. 3.6.3.3  Generic DPLL Overview
          1. 3.6.3.3.1 Generic APLL Overview
          2. 3.6.3.3.2 DPLLs Output Clocks Parameters
          3. 3.6.3.3.3 Enable Control, Status, and Low-Power Operation Mode
          4. 3.6.3.3.4 DPLL Power Modes
          5. 3.6.3.3.5 DPLL Recalibration
          6. 3.6.3.3.6 DPLL Output Power Down
        4. 3.6.3.4  DPLL_PER Description
          1. 3.6.3.4.1 DPLL_PER Overview
          2. 3.6.3.4.2 DPLL_PER Synthesized Clock Parameters
          3. 3.6.3.4.3 DPLL_PER Power Modes
          4. 3.6.3.4.4 DPLL_PER Recalibration
        5. 3.6.3.5  DPLL_CORE Description
          1. 3.6.3.5.1 DPLL_CORE Overview
          2. 3.6.3.5.2 DPLL_CORE Synthesized Clock Parameters
          3. 3.6.3.5.3 DPLL_CORE Power Modes
          4. 3.6.3.5.4 DPLL_CORE Recalibration
        6. 3.6.3.6  DPLL_ABE Description
          1. 3.6.3.6.1 DPLL_ABE Overview
          2. 3.6.3.6.2 DPLL_ABE Synthesized Clock Parameters
          3. 3.6.3.6.3 DPLL_ABE Power Modes
          4. 3.6.3.6.4 DPLL_ABE Recalibration
        7. 3.6.3.7  DPLL_MPU Description
          1. 3.6.3.7.1 DPLL_MPU Overview
          2. 3.6.3.7.2 DPLL_MPU Tactical Clocking Adjustment
          3. 3.6.3.7.3 DPLL_MPU Synthesized Clock Parameters
          4. 3.6.3.7.4 DPLL_MPU Power Modes
          5. 3.6.3.7.5 DPLL_MPU Recalibration
        8. 3.6.3.8  DPLL_IVA Description
          1. 3.6.3.8.1 DPLL_IVA Overview
          2. 3.6.3.8.2 DPLL_IVA Synthesized Clock Parameters
          3. 3.6.3.8.3 DPLL_IVA Power Modes
          4. 3.6.3.8.4 DPLL_IVA Recalibration
        9. 3.6.3.9  DPLL_USB Description
          1. 3.6.3.9.1 DPLL_USB Overview
          2. 3.6.3.9.2 DPLL_USB Synthesized Clock Parameters
          3. 3.6.3.9.3 DPLL_USB Power Modes
          4. 3.6.3.9.4 DPLL_USB Recalibration
        10. 3.6.3.10 DPLL_DSP Description
          1. 3.6.3.10.1 DPLL_DSP Overview
          2. 3.6.3.10.2 DPLL_DSP Synthesized Clock Parameters
          3. 3.6.3.10.3 DPLL_DSP Power Modes
          4. 3.6.3.10.4 DPLL_DSP Recalibration
        11. 3.6.3.11 DPLL_GMAC Description
          1. 3.6.3.11.1 DPLL_GMAC Overview
          2. 3.6.3.11.2 DPLL_GMAC Synthesized Clock Parameters
          3. 3.6.3.11.3 DPLL_GMAC Power Modes
          4. 3.6.3.11.4 DPLL_GMAC Recalibration
        12. 3.6.3.12 DPLL_GPU Description
          1. 3.6.3.12.1 DPLL_GPU Overview
          2. 3.6.3.12.2 DPLL_GPU Synthesized Clock Parameters
          3. 3.6.3.12.3 DPLL_GPU Power Modes
          4. 3.6.3.12.4 DPLL_GPU Recalibration
        13. 3.6.3.13 DPLL_DDR Description
          1. 3.6.3.13.1 DPLL_DDR Overview
          2. 3.6.3.13.2 DPLL_DDR Synthesized Clock Parameters
          3. 3.6.3.13.3 DPLL_DDR Power Modes
          4. 3.6.3.13.4 DPLL_DDR Recalibration
        14. 3.6.3.14 DPLL_PCIE_REF Description
          1. 3.6.3.14.1 DPLL_PCIE_REF Overview
          2. 3.6.3.14.2 DPLL_PCIE_REF Synthesized Clock Parameters
          3. 3.6.3.14.3 DPLL_PCIE_REF Power Modes
        15. 3.6.3.15 APLL_PCIE Description
          1. 3.6.3.15.1 APLL_PCIE Overview
          2. 3.6.3.15.2 APLL_PCIE Synthesized Clock Parameters
          3. 3.6.3.15.3 APLL_PCIE Power Modes
      4. 3.6.4 Clock Domains
        1. 3.6.4.1  CD_WKUPAON Clock Domain
          1. 3.6.4.1.1 CD_WKUPAON Overview
          2. 3.6.4.1.2 CD_WKUPAON Clock Domain Modes
          3. 3.6.4.1.3 CD_WKUPAON Clock Domain Dependency
            1. 3.6.4.1.3.1 CD_WKUPAON Wake-Up Dependency
          4. 3.6.4.1.4 CD_WKUPAON Clock Domain Module Attributes
        2. 3.6.4.2  CD_DSP1 Clock Domain
          1. 3.6.4.2.1 CD_DSP1 Overview
          2. 3.6.4.2.2 CD_DSP1 Clock Domain Modes
          3. 3.6.4.2.3 CD_DSP1 Clock Domain Dependency
            1. 3.6.4.2.3.1 CD_DSP1 Static Dependency
            2. 3.6.4.2.3.2 CD_DSP1 Dynamic Dependency
          4. 3.6.4.2.4 CD_DSP1 Clock Domain Module Attributes
        3. 3.6.4.3  CD_CUSTEFUSE Clock Domain
          1. 3.6.4.3.1 CD_CUSTEFUSE Overview
          2. 3.6.4.3.2 CD_CUSTEFUSE Clock Domain Modes
          3. 3.6.4.3.3 CD_CUSTEFUSE Clock Domain Dependency
          4. 3.6.4.3.4 CD_CUSTEFUSE Clock Domain Module Attributes
        4. 3.6.4.4  CD_MPU Clock Domain
          1. 3.6.4.4.1 CD_MPU Overview
          2. 3.6.4.4.2 CD_MPU Clock Domain Modes
          3. 3.6.4.4.3 CD_MPU Clock Domain Dependency
            1. 3.6.4.4.3.1 CD_MPU Static Dependency
            2. 3.6.4.4.3.2 CD_MPU Dynamic Dependency
          4. 3.6.4.4.4 CD_MPU Clock Domain Module Attributes
        5. 3.6.4.5  CD_L4PER1 Clock Domain
          1. 3.6.4.5.1 CD_L4PER1 Overview
          2. 3.6.4.5.2 CD_L4PER1 Clock Domain Modes
          3. 3.6.4.5.3 CD_L4PER1 Clock Domain Dependency
            1. 3.6.4.5.3.1 CD_L4PER1 Dynamic Dependency
            2. 3.6.4.5.3.2 CD_L4PER1 Wake-Up Dependency
          4. 3.6.4.5.4 CD_L4PER1 Clock Domain Module Attributes
        6. 3.6.4.6  CD_L4PER2 Clock Domain
          1. 3.6.4.6.1 CD_L4PER2 Overview
          2. 3.6.4.6.2 CD_L4PER2 Clock Domain Modes
          3. 3.6.4.6.3 CD_L4PER2 Clock Domain Dependency
            1. 3.6.4.6.3.1 CD_L4PER2 Dynamic Dependency
            2. 3.6.4.6.3.2 CD_L4PER2 Wake-Up Dependency
          4. 3.6.4.6.4 CD_L4PER2 Clock Domain Module Attributes
        7. 3.6.4.7  CD_L4PER3 Clock Domain
          1. 3.6.4.7.1 CD_L4PER3 Overview
          2. 3.6.4.7.2 CD_L4PER3 Clock Domain Modes
          3. 3.6.4.7.3 CD_L4PER3 Clock Domain Dependency
            1. 3.6.4.7.3.1 CD_L4PER3 Dynamic Dependency
            2. 3.6.4.7.3.2 CD_L4PER3 Wake-Up Dependency
          4. 3.6.4.7.4 CD_L4PER3 Clock Domain Module Attributes
        8. 3.6.4.8  CD_L4SEC Clock Domain
          1. 3.6.4.8.1 CD_L4SEC Overview
          2. 3.6.4.8.2 CD_L4SEC Clock Domain Modes
          3. 3.6.4.8.3 CD_L4SEC Clock Domain Dependency
            1. 3.6.4.8.3.1 CD_L4SEC Static Dependency
            2. 3.6.4.8.3.2 CD_L4SEC Dynamic Dependency
          4. 3.6.4.8.4 CD_L4SEC Clock Domain Module Attributes
          5. 3.6.4.8.5 268
        9. 3.6.4.9  CD_L3INIT Clock Domain
          1. 3.6.4.9.1 CD_L3INIT Overview
          2. 3.6.4.9.2 CD_L3INIT Clock Domain Modes
          3. 3.6.4.9.3 CD_L3INIT Clock Domain Dependency
            1. 3.6.4.9.3.1 CD_L3INIT Static Dependency
            2. 3.6.4.9.3.2 CD_L3INIT Dynamic Dependency
            3. 3.6.4.9.3.3 CD_L3INIT Wake-Up Dependency
          4. 3.6.4.9.4 CD_L3INIT Clock Domain Module Attributes
        10. 3.6.4.10 CD_IVA Clock Domain
          1. 3.6.4.10.1 CD_IVA Overview
          2. 3.6.4.10.2 CD_IVA Clock Domain Modes
          3. 3.6.4.10.3 CD_IVA Clock Domain Dependency
            1. 3.6.4.10.3.1 CD_IVA Static Dependency
            2. 3.6.4.10.3.2 CD_IVA Dynamic Dependency
          4. 3.6.4.10.4 CD_IVA Clock Domain Module Attributes
        11. 3.6.4.11 CD_GPU Description
          1. 3.6.4.11.1 CD_GPU Overview
          2. 3.6.4.11.2 CD_GPU Clock Domain Modes
          3. 3.6.4.11.3 CD_GPU Clock Domain Dependency
            1. 3.6.4.11.3.1 CD_GPU Static Dependency
            2. 3.6.4.11.3.2 CD_GPU Dynamic Dependency
          4. 3.6.4.11.4 CD_GPU Clock Domain Module Attributes
        12. 3.6.4.12 CD_EMU Clock Domain
          1. 3.6.4.12.1 CD_EMU Overview
          2. 3.6.4.12.2 CD_EMU Clock Domain Modes
          3. 3.6.4.12.3 CD_EMU Clock Domain Dependency
            1. 3.6.4.12.3.1 CD_EMU Dynamic Dependency
          4. 3.6.4.12.4 CD_EMU Clock Domain Module Attributes
        13. 3.6.4.13 CD_DSS Clock Domain
          1. 3.6.4.13.1 CD_DSS Overview
          2. 3.6.4.13.2 CD_DSS Clock Domain Modes
          3. 3.6.4.13.3 CD_DSS Clock Domain Dependency
            1. 3.6.4.13.3.1 CD_DSS Static Dependency
            2. 3.6.4.13.3.2 CD_DSS Dynamic Dependency
            3. 3.6.4.13.3.3 CD_DSS Wake-Up Dependency
          4. 3.6.4.13.4 CD_DSS Clock Domain Module Attributes
        14. 3.6.4.14 CD_L4_CFG Clock Domain
          1. 3.6.4.14.1 CD_L4_CFG Overview
          2. 3.6.4.14.2 CD_L4_CFG Clock Domain Modes
          3. 3.6.4.14.3 CD_L4_CFG Clock Domain Dependency
            1. 3.6.4.14.3.1 CD_L4_CFG Dynamic Dependency
          4. 3.6.4.14.4 CD_L4_CFG Clock Domain Module Attributes
        15. 3.6.4.15 CD_L3_INSTR Clock Domain
          1. 3.6.4.15.1 CD_L3_INSTR Overview
          2. 3.6.4.15.2 CD_L3_INSTR Clock Domain Modes
          3. 3.6.4.15.3 CD_L3_INSTR Clock Domain Dependency
          4. 3.6.4.15.4 CD_L3_INSTR Clock Domain Module Attributes
        16. 3.6.4.16 CD_L3_MAIN1 Clock Domain
          1. 3.6.4.16.1 CD_L3_MAIN1 Overview
          2. 3.6.4.16.2 CD_L3_MAIN1 Clock Domain Modes
          3. 3.6.4.16.3 CD_L3_MAIN1 Clock Domain Dependency
            1. 3.6.4.16.3.1 CD_L3_MAIN1 Dynamic Dependency
          4. 3.6.4.16.4 CD_L3_MAIN1 Clock Domain Module Attributes
        17. 3.6.4.17 CD_EMIF Clock Domain
          1. 3.6.4.17.1 CD_EMIF Overview
          2. 3.6.4.17.2 CD_EMIF Clock Domain Modes
          3. 3.6.4.17.3 CD_EMIF Clock Domain Dependency
          4. 3.6.4.17.4 CD_EMIF Clock Domain Module Attributes
        18. 3.6.4.18 CD_IPU Clock Domain
          1. 3.6.4.18.1 CD_IPU Overview
          2. 3.6.4.18.2 CD_IPU Clock Domain Modes
          3. 3.6.4.18.3 CD_IPU Clock Domain Dependency
            1. 3.6.4.18.3.1 CD_IPU Static Dependency
            2. 3.6.4.18.3.2 CD_IPU Dynamic Dependency
          4. 3.6.4.18.4 CD_IPU Clock Domain Module Attributes
        19. 3.6.4.19 CD_IPU1 Clock Domain
          1. 3.6.4.19.1 CD_IPU1 Overview
          2. 3.6.4.19.2 CD_IPU1 Clock Domain Modes
          3. 3.6.4.19.3 CD_IPU1 Clock Domain Dependency
            1. 3.6.4.19.3.1 CD_IPU1 Static Dependency
            2. 3.6.4.19.3.2 CD_IPU1 Dynamic Dependency
          4. 3.6.4.19.4 CD_IPU1 Clock Domain Module Attributes
        20. 3.6.4.20 CD_IPU2 Clock Domain
          1. 3.6.4.20.1 CD_IPU2 Overview
          2. 3.6.4.20.2 CD_IPU2 Clock Domain Modes
          3. 3.6.4.20.3 CD_IPU2 Clock Domain Dependency
            1. 3.6.4.20.3.1 CD_IPU2 Static Dependency
            2. 3.6.4.20.3.2 CD_IPU2 Dynamic Dependency
          4. 3.6.4.20.4 CD_IPU2 Clock Domain Module Attributes
        21. 3.6.4.21 CD_DMA Clock Domain
          1. 3.6.4.21.1 CD_DMA Overview
          2. 3.6.4.21.2 CD_DMA Clock Domain Modes
          3. 3.6.4.21.3 CD_DMA Clock Domain Dependency
            1. 3.6.4.21.3.1 CD_DMA Static Dependency
            2. 3.6.4.21.3.2 CD_DMA Dynamic Dependency
          4. 3.6.4.21.4 CD_DMA Clock Domain Module Attributes
        22. 3.6.4.22 CD_ATL Clock Domain
          1. 3.6.4.22.1 CD_ATL Overview
          2. 3.6.4.22.2 CD_ATL Clock Domain Modes
          3. 3.6.4.22.3 CD_ATL Clock Domain Module Attributes
        23. 3.6.4.23 CD_CAM Clock Domain
          1. 3.6.4.23.1 CD_CAM Overview
          2. 3.6.4.23.2 CD_CAM Clock Domain Modes
          3. 3.6.4.23.3 CD_CAM Clock Domain Dependency
            1. 3.6.4.23.3.1 CD_CAM Static Dependency
            2. 3.6.4.23.3.2 CD_CAM Dynamic Dependency
          4. 3.6.4.23.4 CD_CAM Clock Domain Module Attributes
          5. 3.6.4.23.5 366
        24. 3.6.4.24 CD_GMAC Clock Domain
          1. 3.6.4.24.1 CD_GMAC Overview
          2. 3.6.4.24.2 CD_GMAC Clock Domain Modes
          3. 3.6.4.24.3 CD_GMAC Clock Domain Dependency
            1. 3.6.4.24.3.1 CD_GMAC Static Dependency
            2. 3.6.4.24.3.2 CD_GMAC Dynamic Dependency
          4. 3.6.4.24.4 CD_GMAC Clock Domain Module Attributes
        25. 3.6.4.25 CD_VPE Clock Domain
          1. 3.6.4.25.1 CD_VPE Overview
          2. 3.6.4.25.2 CD_VPE Clock Domain Modes
          3. 3.6.4.25.3 CD_VPE Clock Domain Dependency
            1. 3.6.4.25.3.1 CD_VPE Wake-Up Dependency
          4. 3.6.4.25.4 CD_VPE Clock Domain Module Attributes
        26. 3.6.4.26 CD_RTC Clock Domain
          1. 3.6.4.26.1 CD_RTC Overview
          2. 3.6.4.26.2 CD_RTC Clock Domain Modes
          3. 3.6.4.26.3 CD_RTC Clock Domain Dependency
            1. 3.6.4.26.3.1 CD_RTC Wake-Up Dependency
          4. 3.6.4.26.4 CD_RTC Clock Domain Module Attributes
        27. 3.6.4.27 CD_PCIE Clock Domain
          1. 3.6.4.27.1 CD_PCIE Overview
          2. 3.6.4.27.2 CD_PCIE Clock Domain Modes
          3. 3.6.4.27.3 CD_PCIE Clock Domain Dependency
            1. 3.6.4.27.3.1 CD_PCIE Wake-Up Dependency
          4. 3.6.4.27.4 CD_PCIE Clock Domain Module Attributes
    7. 3.7  Power Management Functional Description
      1. 3.7.1  PD_WKUPAON Description
        1. 3.7.1.1 PD_WKUPAON Power Domain Modes
          1. 3.7.1.1.1 PD_WKUPAON Logic and Memory Area Power Modes
      2. 3.7.2  PD_DSP1 Description
        1. 3.7.2.1 PD_DSP1 Power Domain Modes
          1. 3.7.2.1.1 PD_DSP1 Logic and Memory Area Power Modes
          2. 3.7.2.1.2 PD_DSP1 Logic and Memory Area Power Modes Control and Status
      3. 3.7.3  PD_CUSTEFUSE Description
        1. 3.7.3.1 PD_CUSTEFUSE Power Domain Modes
          1. 3.7.3.1.1 PD_CUSTEFUSE Logic and Memory Area Power Modes
          2. 3.7.3.1.2 PD_CUSTEFUSE Logic and Memory Area Power Modes Control and Status
      4. 3.7.4  PD_MPU Description
        1. 3.7.4.1 PD_MPU Power Domain Modes
          1. 3.7.4.1.1 PD_MPU Logic and Memory Area Power Modes
          2. 3.7.4.1.2 PD_MPU Logic and Memory Area Power Modes Control and Status
          3. 3.7.4.1.3 PD_MPU Power State Override
      5. 3.7.5  PD_IPU Description
        1. 3.7.5.1 PD_IPU Power Domain Modes
          1. 3.7.5.1.1 PD_IPU Logic and Memory Area Power Modes
          2. 3.7.5.1.2 PD_IPU Logic and Memory Area Power Modes Control and Status
      6. 3.7.6  PD_L3INIT Description
        1. 3.7.6.1 PD_L3INIT Power Domain Modes
          1. 3.7.6.1.1 PD_L3INIT Logic and Memory Area Power Modes
          2. 3.7.6.1.2 PD_L3INIT Logic and Memory Area Power Modes Control and Status
      7. 3.7.7  PD_L4PER Description
      8. 3.7.8  PD_IVA Description
        1. 3.7.8.1 PD_IVA Power Domain Modes
          1. 3.7.8.1.1 PD_IVA Logic and Memory Area Power Modes
          2. 3.7.8.1.2 PD_IVA Logic and Memory Area Power Modes Control and Status
      9. 3.7.9  PD_GPU Description
        1. 3.7.9.1 PD_GPU Power Domain Modes
          1. 3.7.9.1.1 PD_GPU Logic and Memory Area Power Modes
          2. 3.7.9.1.2 PD_GPU Logic and Memory Area Power Modes Control and Status
      10. 3.7.10 PD_EMU Description
      11. 3.7.11 PD_DSS Description
        1. 3.7.11.1 PD_DSS Power Domain Modes
          1. 3.7.11.1.1 PD_DSS Logic and Memory Area Power Modes
          2. 3.7.11.1.2 PD_DSS Logic and Memory Area Power Mode Control and Status
      12. 3.7.12 PD_CORE Description
        1. 3.7.12.1 PD_CORE Power Domain Modes
          1. 3.7.12.1.1 PD_CORE Logic and Memory Area Power Modes
          2. 3.7.12.1.2 PD_CORE Logic and Memory Area Power Mode Control and Status
      13. 3.7.13 PD_CAM Description
        1. 3.7.13.1 PD_CAM Power Domain Modes
          1. 3.7.13.1.1 PD_CAM Logic and Memory Area Power Modes
          2. 3.7.13.1.2 PD_CAM Logic and Memory Area Power Mode Control and Status
      14. 3.7.14 PD_MPUAON Description
        1. 3.7.14.1 PD_MPUAON Power Domain Modes
      15. 3.7.15 PD_MMAON Description
        1. 3.7.15.1 PD_MMAON Power Domain Modes
      16. 3.7.16 PD_COREAON Description
        1. 3.7.16.1 PD_COREAON Power Domain Modes
      17. 3.7.17 PD_VPE Description
        1. 3.7.17.1 PD_VPE Power Domain Modes
          1. 3.7.17.1.1 PD_VPE Logic and Memory Area Power Modes
          2. 3.7.17.1.2 PD_VPE Logic and Memory Area Power Modes Control and Status
      18. 3.7.18 PD_RTC Description
        1. 3.7.18.1 PD_RTC Power Domain Modes
          1. 3.7.18.1.1 PD_RTC Logic and Memory Area Power Modes
    8. 3.8  Voltage-Management Functional Description
      1. 3.8.1 Overview
      2. 3.8.2 Voltage-Control Architecture
      3. 3.8.3 Internal LDOs Control
        1. 3.8.3.1 VDD_MPU_L, VDD_CORE_L, and VDD_IVAHD_L, VDD_GPU_L, VDD_DSPEVE_L Control
          1. 3.8.3.1.1 Adaptive Voltage Scaling
            1. 3.8.3.1.1.1 SmartReflex in the Device
        2. 3.8.3.2 Memory LDOs
        3. 3.8.3.3 ABB LDOs Control
        4. 3.8.3.4 ABB LDO Programming Sequence
          1. 3.8.3.4.1 ABB LDO Enable Sequence
          2. 3.8.3.4.2 ABB LDO Disable Sequence (Entering in Bypass Mode)
        5. 3.8.3.5 BANDGAPs Control
      4. 3.8.4 DVFS
    9. 3.9  Device Low-Power States
      1. 3.9.1 Device Wake-Up Source Summary
      2. 3.9.2 Wakeup Upon Global Warm Reset
      3. 3.9.3 Global Warm Reset During a Device Wake-Up Sequence
      4. 3.9.4 I/O Management
        1. 3.9.4.1 Isolation / Wakeup Sequence
          1. 3.9.4.1.1 Software-Controlled I/O Isolation
    10. 3.10 PRCM Module Programming Guide
      1. 3.10.1 DPLLs Low-Level Programming Models
        1. 3.10.1.1 Global Initialization
          1. 3.10.1.1.1 Surrounding Module Global Initialization
          2. 3.10.1.1.2 DPLL Global Initialization
            1. 3.10.1.1.2.1 Main Sequence – DPLL Global Initialization
            2. 3.10.1.1.2.2 Subsequence – Recalibration Parameter Configuration
            3. 3.10.1.1.2.3 Subsequence – Synthesized Clock Parameter Configuration
            4. 3.10.1.1.2.4 Subsequence – Output Clock Parameter Configuration
        2. 3.10.1.2 DPLL Output Frequency Change
      2. 3.10.2 Clock Management Low-Level Programming Models
        1. 3.10.2.1 Global Initialization
          1. 3.10.2.1.1 Surrounding Module Global Initialization
          2. 3.10.2.1.2 Clock Management Global Initialization
            1. 3.10.2.1.2.1 Main Sequence – Clock Domain Global Initialization
        2. 3.10.2.2 Clock Domain Sleep Transition and Troubleshooting
        3. 3.10.2.3 Enable/Disable Software-Programmable Static Dependency
      3. 3.10.3 Power Management Low-Level Programming Models
        1. 3.10.3.1 Global Initialization
          1. 3.10.3.1.1 Surrounding Module Global Initialization
          2. 3.10.3.1.2 Power Management Global Initialization
            1. 3.10.3.1.2.1 Main Sequence – Power Domain Global Initialization and Setting
        2. 3.10.3.2 Forced Memory Area State Change With Power Domain ON
        3. 3.10.3.3 Forced Power Domain Low-Power State Transition
    11. 3.11 497
    12. 3.12 PRCM Software Configuration for OPP_PLUS
    13. 3.13 PRCM Register Manual
      1. 3.13.1  Not Supported Functionality (Registers and Bits)
      2. 3.13.2  PRCM Instance Summary
      3. 3.13.3  CM_CORE_AON__CKGEN Registers
        1. 3.13.3.1 CM_CORE_AON__CKGEN Register Summary
        2. 3.13.3.2 CM_CORE_AON__CKGEN Register Description
      4. 3.13.4  CM_CORE_AON__DSP1 Registers
        1. 3.13.4.1 CM_CORE_AON__DSP1 Register Summary
        2. 3.13.4.2 CM_CORE_AON__DSP1 Register Description
      5. 3.13.5  CM_CORE_AON__DSP2 Registers
        1. 3.13.5.1 CM_CORE_AON__DSP2 Register Summary
        2. 3.13.5.2 CM_CORE_AON__DSP2 Register Description
      6. 3.13.6  CM_CORE_AON__EVE1 Registers
        1. 3.13.6.1 CM_CORE_AON__EVE1 Register Summary
        2. 3.13.6.2 CM_CORE_AON__EVE1 Register Description
      7. 3.13.7  CM_CORE_AON__EVE2 Registers
        1. 3.13.7.1 CM_CORE_AON__EVE2 Register Summary
        2. 3.13.7.2 CM_CORE_AON__EVE2 Register Description
      8. 3.13.8  CM_CORE_AON__EVE3 Registers
        1. 3.13.8.1 CM_CORE_AON__EVE3 Register Summary
        2. 3.13.8.2 CM_CORE_AON__EVE3 Register Description
      9. 3.13.9  CM_CORE_AON__EVE4 Registers
        1. 3.13.9.1 CM_CORE_AON__EVE4 Register Summary
        2. 3.13.9.2 CM_CORE_AON__EVE4 Register Description
      10. 3.13.10 CM_CORE_AON__INSTR Registers
        1. 3.13.10.1 CM_CORE_AON__INSTR Register Summary
        2. 3.13.10.2 CM_CORE_AON__INSTR Register Description
      11. 3.13.11 CM_CORE_AON__IPU Registers
        1. 3.13.11.1 CM_CORE_AON__IPU Register Summary
        2. 3.13.11.2 CM_CORE_AON__IPU Register Description
      12. 3.13.12 CM_CORE_AON__MPU Registers
        1. 3.13.12.1 CM_CORE_AON__MPU Register Summary
        2. 3.13.12.2 CM_CORE_AON__MPU Register Description
      13. 3.13.13 CM_CORE_AON__OCP_SOCKET Registers
        1. 3.13.13.1 CM_CORE_AON__OCP_SOCKET Register Summary
        2. 3.13.13.2 CM_CORE_AON__OCP_SOCKET Register Description
      14. 3.13.14 CM_CORE_AON__RESTORE Registers
        1. 3.13.14.1 CM_CORE_AON__RESTORE Register Summary
        2. 3.13.14.2 CM_CORE_AON__RESTORE Register Description
      15. 3.13.15 CM_CORE_AON__RTC Registers
        1. 3.13.15.1 CM_CORE_AON__RTC Register Summary
        2. 3.13.15.2 CM_CORE_AON__RTC Register Description
      16. 3.13.16 CM_CORE_AON__VPE Registers
        1. 3.13.16.1 CM_CORE_AON__VPE Register Summary
        2. 3.13.16.2 CM_CORE_AON__VPE Register Description
      17. 3.13.17 CM_CORE__CAM Registers
        1. 3.13.17.1 CM_CORE__CAM Register Summary
        2. 3.13.17.2 CM_CORE__CAM Register Description
      18. 3.13.18 CM_CORE__CKGEN Registers
        1. 3.13.18.1 CM_CORE__CKGEN Register Summary
        2. 3.13.18.2 CM_CORE__CKGEN Register Description
      19. 3.13.19 CM_CORE__COREAON Registers
        1. 3.13.19.1 CM_CORE__COREAON Register Summary
        2. 3.13.19.2 CM_CORE__COREAON Register Description
      20. 3.13.20 CM_CORE__CORE Registers
        1. 3.13.20.1 CM_CORE__CORE Register Summary
        2. 3.13.20.2 CM_CORE__CORE Register Description
      21. 3.13.21 CM_CORE__CUSTEFUSE Registers
        1. 3.13.21.1 CM_CORE__CUSTEFUSE Register Summary
        2. 3.13.21.2 CM_CORE__CUSTEFUSE Register Description
      22. 3.13.22 CM_CORE__DSS Registers
        1. 3.13.22.1 CM_CORE__DSS Register Summary
        2. 3.13.22.2 CM_CORE__DSS Register Description
      23. 3.13.23 CM_CORE__GPU Registers
        1. 3.13.23.1 CM_CORE__GPU Register Summary
        2. 3.13.23.2 CM_CORE__GPU Register Description
      24. 3.13.24 CM_CORE__IVA Registers
        1. 3.13.24.1 CM_CORE__IVA Register Summary
        2. 3.13.24.2 CM_CORE__IVA Register Description
      25. 3.13.25 CM_CORE__L3INIT Registers
        1. 3.13.25.1 CM_CORE__L3INIT Register Summary
        2. 3.13.25.2 CM_CORE__L3INIT Register Description
      26. 3.13.26 CM_CORE__L4PER Registers
        1. 3.13.26.1 CM_CORE__L4PER Register Summary
        2. 3.13.26.2 CM_CORE__L4PER Register Description
      27. 3.13.27 CM_CORE__OCP_SOCKET Registers
        1. 3.13.27.1 CM_CORE__OCP_SOCKET Register Summary
        2. 3.13.27.2 CM_CORE__OCP_SOCKET Register Description
      28. 3.13.28 CM_CORE__RESTORE Registers
        1. 3.13.28.1 CM_CORE__RESTORE Register Summary
        2. 3.13.28.2 CM_CORE__RESTORE Register Description
      29. 3.13.29 SMARTREFLEX Registers
        1. 3.13.29.1 SMARTREFLEX Register Summary
        2. 3.13.29.2 SMARTREFLEX Register Description
      30. 3.13.30 CAM_PRM Registers
        1. 3.13.30.1 CAM_PRM Register Summary
        2. 3.13.30.2 CAM_PRM Register Description
      31. 3.13.31 CKGEN_PRM Registers
        1. 3.13.31.1 CKGEN_PRM Register Summary
        2. 3.13.31.2 CKGEN_PRM Register Description
      32. 3.13.32 COREAON_PRM Registers
        1. 3.13.32.1 COREAON_PRM Register Summary
        2. 3.13.32.2 COREAON_PRM Register Description
      33. 3.13.33 CORE_PRM Registers
        1. 3.13.33.1 CORE_PRM Register Summary
        2. 3.13.33.2 CORE_PRM Register Description
      34. 3.13.34 CUSTEFUSE_PRM Registers
        1. 3.13.34.1 CUSTEFUSE_PRM Register Summary
        2. 3.13.34.2 CUSTEFUSE_PRM Register Description
      35. 3.13.35 DEVICE_PRM Registers
        1. 3.13.35.1 DEVICE_PRM Register Summary
        2. 3.13.35.2 DEVICE_PRM Register Description
      36. 3.13.36 DSP1_PRM registers
        1. 3.13.36.1 DSP1_PRM Register Summary
        2. 3.13.36.2 DSP1_PRM Register Description
      37. 3.13.37 DSP2_PRM Registers
        1. 3.13.37.1 DSP2_PRM Register Summary
        2. 3.13.37.2 DSP2_PRM Register Description
      38. 3.13.38 DSS_PRM Registers
        1. 3.13.38.1 DSS_PRM Register Summary
        2. 3.13.38.2 DSS_PRM Register Description
      39. 3.13.39 EMU_CM Registers
        1. 3.13.39.1 EMU_CM Register Summary
        2. 3.13.39.2 EMU_CM Register Description
      40. 3.13.40 EMU_PRM Registers
        1. 3.13.40.1 EMU_PRM Register Summary
        2. 3.13.40.2 EMU_PRM Register Description
      41. 3.13.41 EVE1_PRM Registers
        1. 3.13.41.1 EVE1_PRM Register Summary
        2. 3.13.41.2 EVE1_PRM Register Description
      42. 3.13.42 EVE2_PRM Registers
        1. 3.13.42.1 EVE2_PRM Register Summary
        2. 3.13.42.2 EVE2_PRM Register Description
      43. 3.13.43 EVE3_PRM Registers
        1. 3.13.43.1 EVE3_PRM Register Summary
        2. 3.13.43.2 EVE3_PRM Register Description
      44. 3.13.44 EVE4_PRM Registers
        1. 3.13.44.1 EVE4_PRM Register Summary
        2. 3.13.44.2 EVE4_PRM Register Description
      45. 3.13.45 GPU_PRM Registers
        1. 3.13.45.1 GPU_PRM Register Summary
        2. 3.13.45.2 GPU_PRM Register Description
      46. 3.13.46 INSTR_PRM Registers
        1. 3.13.46.1 INSTR_PRM Register Summary
        2. 3.13.46.2 INSTR_PRM Register Description
      47. 3.13.47 IPU_PRM registers
        1. 3.13.47.1 IPU_PRM Register Summary
        2. 3.13.47.2 IPU_PRM Register Description
      48. 3.13.48 IVA_PRM Registers
        1. 3.13.48.1 IVA_PRM Register Summary
        2. 3.13.48.2 IVA_PRM Register Description
      49. 3.13.49 L3INIT_PRM Registers
        1. 3.13.49.1 L3INIT_PRM Register Summary
        2. 3.13.49.2 L3INIT_PRM Register Description
      50. 3.13.50 L4PER_PRM Registers
        1. 3.13.50.1 L4PER_PRM Register Summary
        2. 3.13.50.2 L4PER_PRM Register Description
      51. 3.13.51 MPU_PRM Registers
        1. 3.13.51.1 MPU_PRM Register Summary
        2. 3.13.51.2 MPU_PRM Register Description
      52. 3.13.52 OCP_SOCKET_PRM Registers
        1. 3.13.52.1 OCP_SOCKET_PRM Register Summary
        2. 3.13.52.2 OCP_SOCKET_PRM Register Description
      53. 3.13.53 RTC_PRM Registers
        1. 3.13.53.1 RTC_PRM Register Summary
        2. 3.13.53.2 RTC_PRM Register Description
      54. 3.13.54 VPE_PRM Registers
        1. 3.13.54.1 VPE_PRM Register Summary
        2. 3.13.54.2 VPE_PRM Register Description
      55. 3.13.55 WKUPAON_CM Registers
        1. 3.13.55.1 WKUPAON_CM Register Summary
        2. 3.13.55.2 WKUPAON_CM Register Description
      56. 3.13.56 WKUPAON_PRM registers
        1. 3.13.56.1 WKUPAON_PRM Register Summary
        2. 3.13.56.2 WKUPAON_PRM Register Description
  6. 4 Cortex-A15 MPU Subsystem
    1. 4.1 Cortex-A15 MPU Subsystem Overview
      1. 4.1.1 Introduction
      2. 4.1.2 Features
    2. 4.2 Cortex-A15 MPU Subsystem Integration
      1. 4.2.1 Clock Distribution
      2. 4.2.2 Reset Distribution
    3. 4.3 Cortex-A15 MPU Subsystem Functional Description
      1. 4.3.1 MPU Subsystem Block Diagram
      2. 4.3.2 Cortex-A15 MPCore (MPU_CLUSTER)
        1. 4.3.2.1 MPU L2 Cache Memory System
          1. 4.3.2.1.1 MPU L2 Cache Architecture
          2. 4.3.2.1.2 MPU L2 Cache Controller
          3. 4.3.2.1.3 677
      3. 4.3.3 MPU_AXI2OCP
      4. 4.3.4 Memory Adapter
        1. 4.3.4.1 MPU_MA Overview
        2. 4.3.4.2 AXI Input Interface
        3. 4.3.4.3 Interleaving
          1. 4.3.4.3.1 High-Order Fixed Interleaving Model
          2. 4.3.4.3.2 Lower 2-GiB Programmable Interleaving Model
          3. 4.3.4.3.3 Local Interconnect and Synchronization Agent (LISA) Section Manager
          4. 4.3.4.3.4 MA_LSM Registers
          5. 4.3.4.3.5 Posted and Nonposted Writes
          6. 4.3.4.3.6 Errors
        4. 4.3.4.4 Statistics Collector Probe Ports
        5. 4.3.4.5 MPU_MA Firewall
        6. 4.3.4.6 MPU_MA Power and Reset Management
        7. 4.3.4.7 MPU_MA Watchpoint
          1. 4.3.4.7.1 Watchpoint Types
          2. 4.3.4.7.2 Transaction Filtering Options
          3. 4.3.4.7.3 Transaction Match Effects
          4. 4.3.4.7.4 Trigger Generation
          5. 4.3.4.7.5 Programming Options Summary
      5. 4.3.5 Realtime Counter (Master Counter)
        1. 4.3.5.1 Counter Operation
        2. 4.3.5.2 Frequency Change Procedure
      6. 4.3.6 MPU Watchdog Timer
      7. 4.3.7 MPU Subsystem Power Management
        1. 4.3.7.1 Power Domains
        2. 4.3.7.2 Power States of MPU_C0
        3. 4.3.7.3 Power States of MPU Subsystem
        4. 4.3.7.4 MPU_WUGEN
        5. 4.3.7.5 Power Transition Sequence
        6. 4.3.7.6 SR3-APG Technology Fail-Safe Mode
      8. 4.3.8 MPU Subsystem AMBA Interface Configuration
    4. 4.4 Cortex-A15 MPU Subsystem Register Manual
      1. 4.4.1  Cortex-A15 MPU Subsystem Instance Summary
      2. 4.4.2  MPU_CS_STM Registers
      3. 4.4.3  MPU_INTC Registers
      4. 4.4.4  MPU_PRCM_OCP_SOCKET Registers
        1. 4.4.4.1 MPU_PRCM_OCP_SOCKET Register Summary
        2. 4.4.4.2 MPU_PRCM_OCP_SOCKET Register Description
      5. 4.4.5  MPU_PRCM_DEVICE Registers
        1. 4.4.5.1 MPU_PRCM_DEVICE Register Summary
        2. 4.4.5.2 MPU_PRCM_DEVICE Register Description
      6. 4.4.6  MPU_PRCM_PRM_C0 Registers
        1. 4.4.6.1 MPU_PRCM_PRM_C0 Register Summary
        2. 4.4.6.2 MPU_PRCM_PRM_C0 Register Description
      7. 4.4.7  MPU_PRCM_CM_C0 Registers
        1. 4.4.7.1 MPU_PRCM_CM_C0 Register Summary
        2. 4.4.7.2 MPU_PRCM_CM_C0 Register Description
      8. 4.4.8  MPU_WUGEN Registers
        1. 4.4.8.1 MPU_WUGEN Register Summary
        2. 4.4.8.2 MPU_WUGEN Register Description
      9. 4.4.9  MPU_WD_TIMER Registers
        1. 4.4.9.1 MPU_WD_TIMER Register Summary
        2. 4.4.9.2 MPU_WD_TIMER Register Description
      10. 4.4.10 MPU_AXI2OCP_MISC Registers
        1. 4.4.10.1 MPU_AXI2OCP_MISC Register Summary
        2. 4.4.10.2 MPU_AXI2OCP_MISC Register Description
      11. 4.4.11 MPU_MA_LSM Registers
        1. 4.4.11.1 MPU_MA_LSM Register Summary
        2. 4.4.11.2 MPU_MA_LSM Register Description
      12. 4.4.12 MPU_MA_WP Registers
        1. 4.4.12.1 MPU_MA_WP Register Summary
        2. 4.4.12.2 MPU_MA_WP Register Description
  7. 5 DSP Subsystem
    1. 5.1 DSP Subsystem Overview
      1. 5.1.1 DSP Subsystem Key Features
    2. 5.2 DSP Subsystem Integration
    3. 5.3 DSP Subsystem Functional Description
      1. 5.3.1  DSP Subsystem Block Diagram
      2. 5.3.2  DSP Subsystem Components
        1. 5.3.2.1 C66x DSP Subsystem Introduction
        2. 5.3.2.2 DSP TMS320C66x CorePac
          1. 5.3.2.2.1 DSP TMS320C66x CorePac CPU
          2. 5.3.2.2.2 DSP TMS320C66x CorePac Internal Memory Controllers and Memories
            1. 5.3.2.2.2.1 Level 1 Memories
            2. 5.3.2.2.2.2 Level 2 Memory
          3. 5.3.2.2.3 DSP C66x CorePac Internal Peripherals
            1. 5.3.2.2.3.1 DSP C66x CorePac Interrupt Controller (DSP INTC)
            2. 5.3.2.2.3.2 DSP C66x CorePac Power-Down Controller (DSP PDC)
            3. 5.3.2.2.3.3 DSP C66x CorePac Bandwidth Manager (BWM)
            4. 5.3.2.2.3.4 DSP C66x CorePac Memory Protection Hardware
            5. 5.3.2.2.3.5 DSP C66x CorePac Internal DMA (IDMA) Controller
            6. 5.3.2.2.3.6 DSP C66x CorePac External Memory Controller
            7. 5.3.2.2.3.7 DSP C66x CorePac Extended Memory Controller
              1. 5.3.2.2.3.7.1 XMC MDMA Accesses at DSP System Level
                1. 5.3.2.2.3.7.1.1 DSP System MPAX Logic
                2. 5.3.2.2.3.7.1.2 MDMA Non-Post Override Control
            8. 5.3.2.2.3.8 L1P Memory Error Detection Logic
            9. 5.3.2.2.3.9 L2 Memory Error Detection and Correction Logic
        3. 5.3.2.3 DSP Debug and Trace Support
          1. 5.3.2.3.1 DSP Advanced Event Triggering (AET)
          2. 5.3.2.3.2 DSP Trace Support
          3. 5.3.2.3.3 770
      3. 5.3.3  DSP System Control Logic
        1. 5.3.3.1 DSP System Clocks
        2. 5.3.3.2 DSP Hardware Resets
        3. 5.3.3.3 DSP Software Resets
        4. 5.3.3.4 DSP Power Management
          1. 5.3.3.4.1 DSP System Powerdown Protocols
          2. 5.3.3.4.2 DSP Software and Hardware Power Down Sequence Overview
          3. 5.3.3.4.3 DSP IDLE Wakeup
          4. 5.3.3.4.4 DSP SYSTEM IRQWAKEEN registers
          5. 5.3.3.4.5 DSP Automatic Power Transition
      4. 5.3.4  DSP Interrupt Requests
        1. 5.3.4.1 DSP Input Interrupts
          1. 5.3.4.1.1 DSP Non-maskable Interrupt Input
        2. 5.3.4.2 DSP Event and Interrupt Generation Outputs
          1. 5.3.4.2.1 DSP MDMA and DSP EDMA Mflag Event Outputs
          2. 5.3.4.2.2 DSP Aggregated Error Interrupt Output
          3. 5.3.4.2.3 Non-DSP C66x CorePac Generated Peripheral Interrupt Outputs
      5. 5.3.5  DSP DMA Requests
        1. 5.3.5.1 DSP EDMA Wakeup Interrupt
      6. 5.3.6  DSP Intergated Memory Management Units
        1. 5.3.6.1 DSP MMUs Overview
        2. 5.3.6.2 Routing MDMA Traffic through DSP MMU0
        3. 5.3.6.3 Routing EDMA Traffic thorugh DSP MMU1
      7. 5.3.7  DSP Integrated EDMA Subsystem
        1. 5.3.7.1 DSP EDMA Overview
        2. 5.3.7.2 DSP System and Device Level Settings of DSP EDMA
      8. 5.3.8  DSP L2 interconnect Network
        1. 5.3.8.1 DSP Public Firewall Settings
        2. 5.3.8.2 DSP NoC Flag Mux and Error Log Registers
        3. 5.3.8.3 DSP NoC Arbitration
      9. 5.3.9  DSP Boot Configuration
      10. 5.3.10 DSP Internal and External Memory Views
        1. 5.3.10.1 C66x CPU View of the Address Space
        2. 5.3.10.2 DSP_EDMA View of the Address Space
        3. 5.3.10.3 L3_MAIN View of the DSP Address Space
    4. 5.4 DSP Subsystem Register Manual
      1. 5.4.1 DSP Subsystem Instance Summary
      2. 5.4.2 DSP_ICFG Registers
        1. 5.4.2.1 DSP_ICFG Register Summary
        2. 5.4.2.2 DSP_ICFG Register Description
      3. 5.4.3 DSP_SYSTEM Registers
        1. 5.4.3.1 DSP_SYSTEM Register Summary
        2. 5.4.3.2 DSP_SYSTEM Register Description
      4. 5.4.4 DSP_FW_L2_NOC_CFG Registers
        1. 5.4.4.1 DSP_FW_L2_NOC_CFG Register Summary
        2. 5.4.4.2 DSP_FW_L2_NOC_CFG Register Description
  8. 6 IVA Subsystem
  9. 7 Dual Cortex-M4 IPU Subsystem
    1. 7.1 Dual Cortex-M4 IPU Subsystem Overview
      1. 7.1.1 Introduction
      2. 7.1.2 Features
    2. 7.2 Dual Cortex-M4 IPU Subsystem Integration
      1. 7.2.1 Dual Cortex-M4 IPU Subsystem Clock and Reset Distribution
        1. 7.2.1.1 Clock Distribution
        2. 7.2.1.2 Reset Distribution
    3. 7.3 Dual Cortex-M4 IPU Subsystem Functional Description
      1. 7.3.1 IPUx Subsystem Block Diagram
      2. 7.3.2 Power Management
        1. 7.3.2.1 Local Power Management
        2. 7.3.2.2 Power Domains
        3. 7.3.2.3 831
        4. 7.3.2.4 Voltage Domain
        5. 7.3.2.5 Power States and Modes
        6. 7.3.2.6 Wake-Up Generator (IPUx_WUGEN)
          1. 7.3.2.6.1 IPUx_WUGEN Main Features
      3. 7.3.3 IPUx_UNICACHE
      4. 7.3.4 IPUx_UNICACHE_MMU
      5. 7.3.5 IPUx_UNICACHE_SCTM
        1. 7.3.5.1 Counter Functions
          1. 7.3.5.1.1 Input Events
          2. 7.3.5.1.2 Counters
            1. 7.3.5.1.2.1 Counting Modes
            2. 7.3.5.1.2.2 Counter Overflow
            3. 7.3.5.1.2.3 Counters and Processor State
            4. 7.3.5.1.2.4 Chaining Counters
            5. 7.3.5.1.2.5 Enabling and Disabling Counters
            6. 7.3.5.1.2.6 Resetting Counters
        2. 7.3.5.2 Timer Functions
          1. 7.3.5.2.1 Periodic Intervals
          2. 7.3.5.2.2 Event Generation
      6. 7.3.6 IPUx_MMU
        1. 7.3.6.1 IPUx_MMU Behavior on Page-Fault in IPUx Subsystem
      7. 7.3.7 Interprocessor Communication (IPC)
        1. 7.3.7.1 Use of WFE and SEV
        2. 7.3.7.2 Use of Interrupt for IPC
        3. 7.3.7.3 Use of the Bit-Band Feature for Semaphore Operations
        4. 7.3.7.4 Private Memory Space
      8. 7.3.8 IPU Boot Options
    4. 7.4 Dual Cortex-M4 IPU Subsystem Register Manual
      1. 7.4.1 IPUx Subsystem Instance Summary
      2. 7.4.2 IPUx_UNICACHE_CFG Registers
        1. 7.4.2.1 IPUx_UNICACHE_CFG Register Summary
        2. 7.4.2.2 IPUx_UNICACHE_CFG Register Description
      3. 7.4.3 IPUx_UNICACHE_SCTM Registers
        1. 7.4.3.1 IPUx_UNICACHE_SCTM Register Summary
        2. 7.4.3.2 IPUx_UNICACHE_SCTM Register Description
      4. 7.4.4 IPUx_UNICACHE_MMU (AMMU) Registers
        1. 7.4.4.1 IPUx_UNICACHE_MMU (AMMU) Register Summary
        2. 7.4.4.2 IPUx_UNICACHE_MMU (AMMU) Register Description
      5. 7.4.5 IPUx_MMU Registers
      6. 7.4.6 IPUx_Cx_INTC Registers
      7. 7.4.7 IPUx_WUGEN Registers
        1. 7.4.7.1 IPUx_WUGEN Register Summary
        2. 7.4.7.2 IPUx_WUGEN Register Description
      8. 7.4.8 IPUx_Cx_RW_TABLE Registers
        1. 7.4.8.1 IPUx_Cx_RW_TABLE Register Summary
        2. 7.4.8.2 IPUx_Cx_RW_TABLE Register Description
  10. 8 Camera Interface Subsystem
    1. 8.1 CAMSS Overview
      1. 8.1.1 CAMSS Block Diagram
      2. 8.1.2 881
      3. 8.1.3 CAMSS Features
    2. 8.2 CAMSS Environment
      1. 8.2.1 CAMSS Interfaces Signal Descriptions
    3. 8.3 CAMSS Integration
      1. 8.3.1 CAMSS Main Integration Attributes
      2. 8.3.2 CAL Integration - Video Port
      3. 8.3.3 CAL Integration - PPI Interface
    4. 8.4 CAMSS Functional Description
      1. 8.4.1 CAMSS Hardware and Software Reset
      2. 8.4.2 CAMSS Clock Configuration
      3. 8.4.3 CAMSS Power Management
      4. 8.4.4 CAMSS Interrupt Events
      5. 8.4.5 CSI2 PHY Functional Description
        1. 8.4.5.1 CSI2 PHY Overview
        2. 8.4.5.2 CSI2 PHY Configuration
        3. 8.4.5.3 CSI2 PHY Link Initialization Sequence
        4. 8.4.5.4 CSI2 PHY Error Signals
      6. 8.4.6 CAL Functional Description
        1. 8.4.6.1  CAL Block Diagram
        2. 8.4.6.2  CSI2 Low Level Protocol
          1. 8.4.6.2.1 CSI2 Physical Layer
          2. 8.4.6.2.2 CSI2 Multi-lane Layer and Lane Merger
          3. 8.4.6.2.3 CSI2 Protocol Layer
            1. 8.4.6.2.3.1  CSI2 Short Packet
            2. 8.4.6.2.3.2  CSI2 Long Packet
            3. 8.4.6.2.3.3  CSI2 ECC and Checksum Generation
              1. 8.4.6.2.3.3.1 CSI2 ECC
              2. 8.4.6.2.3.3.2 CSI2 Checksum
            4. 8.4.6.2.3.4  CSI2 Alignment Constraints
            5. 8.4.6.2.3.5  CSI2 Data Identifier
            6. 8.4.6.2.3.6  CSI2 Virtual Channel ID
            7. 8.4.6.2.3.7  CSI2 Synchronization Codes
            8. 8.4.6.2.3.8  CSI2 Generic Short Packet Codes
            9. 8.4.6.2.3.9  CSI2 Frame Structure and Data
            10. 8.4.6.2.3.10 CSI2 Virtual Channel and Context
          4. 8.4.6.2.4 CSI2 TAG Generation FSM
        3. 8.4.6.3  CAL Data Stream Merger
        4. 8.4.6.4  CAL Pixel Extraction
        5. 8.4.6.5  CAL DPCM Decoding and Encoding
        6. 8.4.6.6  CAL Stream Interleaving
        7. 8.4.6.7  CAL Pixel Packing
        8. 8.4.6.8  CAL Write DMA
          1. 8.4.6.8.1 CAL Write DMA Overview
          2. 8.4.6.8.2 CAL Write DMA Data Cropping
          3. 8.4.6.8.3 CAL Write DMA Buffer Management
          4. 8.4.6.8.4 CAL Write DMA OCP Address Generation
            1. 8.4.6.8.4.1 Write DMA Buffer Base Address
            2. 8.4.6.8.4.2 Write DMA Line Start Address
            3. 8.4.6.8.4.3 Write DMA Data Address
          5. 8.4.6.8.5 CAL Write DMA OCP Transaction Generation
          6. 8.4.6.8.6 CAL Write DMA Real Time Traffic
        9. 8.4.6.9  CAL Video Port
          1. 8.4.6.9.1 CAL Video Port Overview
          2. 8.4.6.9.2 CAL Video Port Pixel Clock Generation
          3. 8.4.6.9.3 CAL Video Port Video Timing Generator
        10. 8.4.6.10 CAL Registers Shadowing
    5. 8.5 CAMSS Register Manual
      1. 8.5.1 CAMSS Instance Summary
      2. 8.5.2 CAL Registers
        1. 8.5.2.1 CAL Register Summary
        2. 8.5.2.2 CAL Register Description
      3. 8.5.3 CSI2 PHY Registers
        1. 8.5.3.1 CSI2 PHY Register Summary
        2. 8.5.3.2 CSI2 PHY Register Description
  11. 9 Video Input Port
    1. 9.1 VIP Overview
    2. 9.2 VIP Environment
    3. 9.3 VIP Integration
    4. 9.4 VIP Functional Description
      1. 9.4.1 VIP Block Diagram
      2. 9.4.2 VIP Software Reset
      3. 9.4.3 VIP Power and Clocks Management
        1. 9.4.3.1 VIP Clocks
        2. 9.4.3.2 VIP Idle Mode
        3. 9.4.3.3 VIP StandBy Mode
      4. 9.4.4 VIP Slice
        1. 9.4.4.1 VIP Slice Processing Path Overview
        2. 9.4.4.2 VIP Slice Processing Path Multiplexers
          1. 9.4.4.2.1 VIP_CSC Multiplexers
          2. 9.4.4.2.2 VIP_SC Multiplexer
          3. 9.4.4.2.3 Output to VPDMA Multiplexers
        3. 9.4.4.3 VIP Slice Processing Path Examples
          1. 9.4.4.3.1 Input: A=RGB, B=YUV422; Output: A=RGB, B=RGB
          2. 9.4.4.3.2 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=RGB
          3. 9.4.4.3.3 Input: A=RGB, B=YUV422; Output: A=RGB, B=Scaled YUV420
          4. 9.4.4.3.4 Input: A=YUV444, B=YUV422; Output: A=YUV422, A=Scaled YUV422, B=YUV422
          5. 9.4.4.3.5 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV420
          6. 9.4.4.3.6 Input: A=YUV444; Output: A=Scaled YUV420, A=YUV444
          7. 9.4.4.3.7 Input: A=YUV422 8/16; Output: A=Scaled YUV420, A=YUV444
          8. 9.4.4.3.8 Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=YUV420
          9. 9.4.4.3.9 Input: A=YUV422 8/16, B=YUV422; Output: A=YUV420, B=YUV420
      5. 9.4.5 VIP Parser
        1. 9.4.5.1  Features
        2. 9.4.5.2  Repacker
        3. 9.4.5.3  Analog Video
        4. 9.4.5.4  Digitized Video
        5. 9.4.5.5  Frame Buffers
        6. 9.4.5.6  Input Data Interface
          1. 9.4.5.6.1  8b Interface Mode
          2. 9.4.5.6.2  16b Interface Mode
          3. 9.4.5.6.3  24b Interface Mode
          4. 9.4.5.6.4  Signal Relationships
          5. 9.4.5.6.5  General 5 Pin Interfaces
          6. 9.4.5.6.6  Signal Subsets—4 Pin VSYNC, ACTVID, and FID
          7. 9.4.5.6.7  Signal Subsets—4 Pin VSYNC, HSYNC, and FID
          8. 9.4.5.6.8  Vertical Sync
          9. 9.4.5.6.9  Field ID Determination Using Dedicated Signal
          10. 9.4.5.6.10 Field ID Determination Using VSYNC Skew
          11. 9.4.5.6.11 Rationale for FID Determination By VSYNC Skew
          12. 9.4.5.6.12 ACTVID Framing
          13. 9.4.5.6.13 Ancillary Data Storage in Descrete Sync Mode
        7. 9.4.5.7  BT.656 Style Embedded Sync
          1. 9.4.5.7.1 Data Input
          2. 9.4.5.7.2 Sync Words
          3. 9.4.5.7.3 Error Correction
          4. 9.4.5.7.4 Embedded Sync Ancillary Data
          5. 9.4.5.7.5 Embedded Sync RGB 24-bit Data
        8. 9.4.5.8  Source Multiplexing
          1. 9.4.5.8.1  Multiplexing Scenarios
          2. 9.4.5.8.2  2-Way Multiplexing
          3. 9.4.5.8.3  4-Way Multiplexing
          4. 9.4.5.8.4  Line Multiplexing
          5. 9.4.5.8.5  Super Frame Concept in Line Multiplexing
          6. 9.4.5.8.6  8-bit Data Interface in Line Multiplexing
          7. 9.4.5.8.7  16-bit Data Interface in Line Multiplexing
          8. 9.4.5.8.8  Split Lines in Line Multiplex Mode
          9. 9.4.5.8.9  Meta Data
          10. 9.4.5.8.10 TI Line Mux Mode, Split Lines, and Channel ID Remapping
        9. 9.4.5.9  Channel ID Extraction for 2x/4x Multiplexed Source
          1. 9.4.5.9.1 Channel ID Extraction Overview
          2. 9.4.5.9.2 Channel ID Embedded in Protection Bits for 2- and 4-Way Multiplexing
          3. 9.4.5.9.3 Channel ID Embedded in Horizontal Blanking Pixel Data for 2- and 4-Way Multiplexing
        10. 9.4.5.10 Embedded Sync Mux Modes and Data Bus Widths
        11. 9.4.5.11 Ancillary and Active Video Cropping
        12. 9.4.5.12 Interrupts
        13. 9.4.5.13 VDET Interrupt
        14. 9.4.5.14 Source Video Size
        15. 9.4.5.15 Clipping
        16. 9.4.5.16 Current and Last FID Value
        17. 9.4.5.17 Disable Handling
        18. 9.4.5.18 Picture Size Interrupt
        19. 9.4.5.19 Discrete Sync Signals
          1. 9.4.5.19.1 VBLNK and HBLNK
          2. 9.4.5.19.2 BLNK and ACTVID (1)
          3. 9.4.5.19.3 VBLNK and ACTVID(2)
          4. 9.4.5.19.4 VBLNK and HSYNC
          5. 9.4.5.19.5 VSYNC and HBLNK
          6. 9.4.5.19.6 VSYNC and ACTIVID(1)
          7. 9.4.5.19.7 VSYNC and ACTIVID(2)
          8. 9.4.5.19.8 VSYNC and HSYNC
          9. 9.4.5.19.9 Line and Pixel Capture Examples
        20. 9.4.5.20 VIP Overflow Detection and Recovery
      6. 9.4.6 VIP Color Space Converter (CSC)
        1. 9.4.6.1 CSC Features
        2. 9.4.6.2 CSC Functional Description
          1. 9.4.6.2.1 HDTV Application
            1. 9.4.6.2.1.1 HDTV Application with Video Data Range
            2. 9.4.6.2.1.2 HDTV Application with Graphics Data Range
            3. 9.4.6.2.1.3 Quantized Coefficients for Color Space Converter in HDTV
          2. 9.4.6.2.2 SDTV Application
            1. 9.4.6.2.2.1 SDTV Application with Video Data Range
            2. 9.4.6.2.2.2 SDTV Application with Graphics Data Range
            3. 9.4.6.2.2.3 Quantized Coefficients for Color Space Converter in SDTV
        3. 9.4.6.3 CSC Bypass Mode
      7. 9.4.7 VIP Scaler (SC)
        1. 9.4.7.1 SC Features
        2. 9.4.7.2 SC Functional Description
          1. 9.4.7.2.1 Trimmer
          2. 9.4.7.2.2 1050
          3. 9.4.7.2.3 Peaking
          4. 9.4.7.2.4 Vertical Scaler
            1. 9.4.7.2.4.1 Running Average Filter
            2. 9.4.7.2.4.2 Vertical Scaler Configuration Parameters
          5. 9.4.7.2.5 Horizontal Scaler
            1. 9.4.7.2.5.1 Half Decimation Filter
            2. 9.4.7.2.5.2 Polyphase Filter
            3. 9.4.7.2.5.3 Nonlinear Horizontal Scaling
            4. 9.4.7.2.5.4 Horizontal Scaler Configuration Registers
          6. 9.4.7.2.6 Basic Configurations
          7. 9.4.7.2.7 Coefficient Memory
            1. 9.4.7.2.7.1 Overview
            2. 9.4.7.2.7.2 Physical Coefficient SRAM Layout
            3. 9.4.7.2.7.3 Scaler Coefficients Packing on 128-bit VPI Control I/F
            4. 9.4.7.2.7.4 VPI Control I/F Memory Map for Scaler Coefficients
            5. 9.4.7.2.7.5 VPI Control Interface
            6. 9.4.7.2.7.6 Coefficient Table Selection Guide
        3. 9.4.7.3 SC Code
          1. 9.4.7.3.1 Generate Coefficient Memory Image
          2. 9.4.7.3.2 Scaler Configuration Calculation
          3. 9.4.7.3.3 Typical Configuration Values
        4. 9.4.7.4 SC Coefficient Data Files
          1. 9.4.7.4.1 HS Polyphase Filter Coefficients
            1. 9.4.7.4.1.1 ppfcoef_scale_eq_1_32_phases_flip.dat
            2. 9.4.7.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat
            3. 9.4.7.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat
            4. 9.4.7.4.1.4 ppfcoef_scale_eq_10div16_32_phases_flip.dat
            5. 9.4.7.4.1.5 ppfcoef_scale_eq_11div16_32_phases_flip.dat
            6. 9.4.7.4.1.6 ppfcoef_scale_eq_12div16_32_phases_flip.dat
            7. 9.4.7.4.1.7 ppfcoef_scale_eq_13div16_32_phases_flip.dat
            8. 9.4.7.4.1.8 ppfcoef_scale_eq_14div16_32_phases_flip.dat
            9. 9.4.7.4.1.9 ppfcoef_scale_eq_15div16_32_phases_flip.dat
          2. 9.4.7.4.2 VS Polyphase Filter Coefficients
            1. 9.4.7.4.2.1 ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
            2. 9.4.7.4.2.2 ppfcoef_scale_eq_3_32_phases_flip.dat
            3. 9.4.7.4.2.3 ppfcoef_scale_eq_4_32_phases_flip.dat
            4. 9.4.7.4.2.4 ppfcoef_scale_eq_5_32_phases_flip.dat
            5. 9.4.7.4.2.5 ppfcoef_scale_eq_6_32_phases_flip.dat
            6. 9.4.7.4.2.6 ppfcoef_scale_eq_7_32_phases_flip.dat
              1. 9.4.7.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
              2. 9.4.7.4.2.6.2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
              3. 9.4.7.4.2.6.3 ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
              4. 9.4.7.4.2.6.4 ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
              5. 9.4.7.4.2.6.5 ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
              6. 9.4.7.4.2.6.6 ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
              7. 9.4.7.4.2.6.7 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
              8. 9.4.7.4.2.6.8 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
          3. 9.4.7.4.3 VS (Bilinear Filter Coefficients)
            1. 9.4.7.4.3.1 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
      8. 9.4.8 VIP Video Port Direct Memory Access (VPDMA)
        1. 9.4.8.1  VPDMA Introduction
        2. 9.4.8.2  VPDMA Basic Definitions
          1. 9.4.8.2.1 Client
          2. 9.4.8.2.2 Channel
          3. 9.4.8.2.3 List
          4. 9.4.8.2.4 Data Formats Supported
        3. 9.4.8.3  1107
        4. 9.4.8.4  VPDMA Client Buffering and Functionality
        5. 9.4.8.5  VPDMA Channels Assignment
        6. 9.4.8.6  VPDMA MFLAG Mechanism
        7. 9.4.8.7  VPDMA Interrupts
        8. 9.4.8.8  VPDMA Descriptors
          1. 9.4.8.8.1 Data Transfer Descriptors
            1. 9.4.8.8.1.1 Data Packet Descriptor Word 0 (Data)
              1. 9.4.8.8.1.1.1 Data Type
              2. 9.4.8.8.1.1.2 Notify
              3. 9.4.8.8.1.1.3 Field
              4. 9.4.8.8.1.1.4 Even Line Skip
              5. 9.4.8.8.1.1.5 Odd Line Skip
              6. 9.4.8.8.1.1.6 Line Stride
            2. 9.4.8.8.1.2 Data Packet Descriptor Word 1
              1. 9.4.8.8.1.2.1 Line Length
              2. 9.4.8.8.1.2.2 Transfer Height
            3. 9.4.8.8.1.3 Data Packet Descriptor Word 2
              1. 9.4.8.8.1.3.1 Start Address
            4. 9.4.8.8.1.4 Data Packet Descriptor Word 3
              1. 9.4.8.8.1.4.1 Packet Type
              2. 9.4.8.8.1.4.2 Mode
              3. 9.4.8.8.1.4.3 Direction
              4. 9.4.8.8.1.4.4 Channel
              5. 9.4.8.8.1.4.5 Priority
              6. 9.4.8.8.1.4.6 Next Channel
            5. 9.4.8.8.1.5 Data Packet Descriptor Word 4
              1. 9.4.8.8.1.5.1 Inbound data
                1. 9.4.8.8.1.5.1.1 Frame Width
                2. 9.4.8.8.1.5.1.2 Frame Height
              2. 9.4.8.8.1.5.2 Outbound data
                1. 9.4.8.8.1.5.2.1 Descriptor Write Address
                2. 9.4.8.8.1.5.2.2 Write Descriptor
                3. 9.4.8.8.1.5.2.3 Drop Data
            6. 9.4.8.8.1.6 Data Packet Descriptor Word 5
              1. 9.4.8.8.1.6.1 Outbound data
                1. 9.4.8.8.1.6.1.1 Max Width
                2. 9.4.8.8.1.6.1.2 Max Height
          2. 9.4.8.8.2 Configuration Descriptor
            1. 9.4.8.8.2.1 Configuration Descriptor Header Word0
            2. 9.4.8.8.2.2 Configuration Descriptor Header Word1
              1. 9.4.8.8.2.2.1 Number of Data Words
            3. 9.4.8.8.2.3 Configuration Descriptor Header Word2
              1. 9.4.8.8.2.3.1 Payload Location
            4. 9.4.8.8.2.4 Configuration Descriptor Header Word3
              1. 9.4.8.8.2.4.1 Packet Type
              2. 9.4.8.8.2.4.2 Direct
              3. 9.4.8.8.2.4.3 Class
                1. 9.4.8.8.2.4.3.1 Address Data Block Format
              4. 9.4.8.8.2.4.4 Destination
              5. 9.4.8.8.2.4.5 Descriptor Length
          3. 9.4.8.8.3 Control Descriptor
            1. 9.4.8.8.3.1 Generic Control Descriptor Format
            2. 9.4.8.8.3.2 Control Descriptor Header Description
              1. 9.4.8.8.3.2.1 Packet Type
              2. 9.4.8.8.3.2.2 Source
              3. 9.4.8.8.3.2.3 Control
            3. 9.4.8.8.3.3 Control Descriptor Types
              1. 9.4.8.8.3.3.1 Sync on Client
              2. 9.4.8.8.3.3.2 Sync on List
              3. 9.4.8.8.3.3.3 Sync on External Event
              4. 9.4.8.8.3.3.4 Sync on Channel
              5. 9.4.8.8.3.3.5 Sync on LM Timer
              6. 9.4.8.8.3.3.6 Change Client Interrupt
              7. 9.4.8.8.3.3.7 Send Interrupt
              8. 9.4.8.8.3.3.8 Reload List
              9. 9.4.8.8.3.3.9 Abort Channel
        9. 9.4.8.9  VPDMA Configuration
          1. 9.4.8.9.1 Regular List
          2. 9.4.8.9.2 Video Input Ports
            1. 9.4.8.9.2.1 Multiplexed Data Streams
            2. 9.4.8.9.2.2 Single YUV Color Separate
            3. 9.4.8.9.2.3 Dual YUV Interleaved
        10. 9.4.8.10 VPDMA Data Formats
          1. 9.4.8.10.1 YUV Data Formats
            1. 9.4.8.10.1.1 Y 4:4:4 (Data Type 0)
            2. 9.4.8.10.1.2 Y 4:2:2 (Data Type 1)
            3. 9.4.8.10.1.3 Y 4:2:0 (Data Type 2)
            4. 9.4.8.10.1.4 C 4:4:4 (Data Type 4)
            5. 9.4.8.10.1.5 C 4:2:2 (Data Type 5)
            6. 9.4.8.10.1.6 C 4:2:0 (Data Type 6)
            7. 9.4.8.10.1.7 YC 4:2:2 (Data Type 7)
            8. 9.4.8.10.1.8 YC 4:4:4 (Data Type 8)
            9. 9.4.8.10.1.9 CY 4:2:2 (Data Type 23)
          2. 9.4.8.10.2 RGB Data Formats
            1. 9.4.8.10.2.1  RGB16-565 (Data Type 0)
            2. 9.4.8.10.2.2  ARGB-1555 (Data Type 1)
            3. 9.4.8.10.2.3  ARGB-4444 (Data Type 2)
            4. 9.4.8.10.2.4  RGBA-5551 (Data Type 3)
            5. 9.4.8.10.2.5  RGBA-4444 (Data Type 4)
            6. 9.4.8.10.2.6  ARGB24-6666 (Data Type 5)
            7. 9.4.8.10.2.7  RGB24-888 (Data Type 6)
            8. 9.4.8.10.2.8  ARGB32-8888 (Data Type 7)
            9. 9.4.8.10.2.9  RGBA24-6666 (Data Type 8)
            10. 9.4.8.10.2.10 RGBA32-8888 (Data Type 9)
          3. 9.4.8.10.3 Miscellaneous Data Type
    5. 9.5 VIP Register Manual
      1. 9.5.1 VIP Instance Summary
      2. 9.5.2 VIP Top Level Registers
        1. 9.5.2.1 VIP Top Level Register Summary
        2. 9.5.2.2 VIP Top Level Register Description
      3. 9.5.3 VIP Parser Registers
        1. 9.5.3.1 VIP Parser Register Summary
        2. 9.5.3.2 VIP Parser Register Description
      4. 9.5.4 VIP CSC Registers
        1. 9.5.4.1 VIP CSC Register Summary
        2. 9.5.4.2 VIP CSC Register Description
      5. 9.5.5 VIP SC registers
        1. 9.5.5.1 VIP SC Register Summary
        2. 9.5.5.2 VIP SC Register Description
      6. 9.5.6 VIP VPDMA Registers
        1. 9.5.6.1 VIP VPDMA Register Summary
        2. 9.5.6.2 VIP VPDMA Register Description
  12. 10Video Processing Engine
    1. 10.1 VPE Overview
    2. 10.2 VPE Integration
    3. 10.3 VPE Functional Description
      1. 10.3.1  VPE Block Diagram
      2. 10.3.2  VPE VC1 Range Mapping/Range Reduction
      3. 10.3.3  VPE Deinterlacer (DEI)
        1. 10.3.3.1 Functional Description
        2. 10.3.3.2 Bypass Mode
        3. 10.3.3.3 1229
          1. 10.3.3.3.1 VPDMA Interface
          2. 10.3.3.3.2 MDT
          3. 10.3.3.3.3 EDI
          4. 10.3.3.3.4 FMD
          5. 10.3.3.3.5 MUX
          6. 10.3.3.3.6 LINE BUFFER
      4. 10.3.4  VPE Scaler (SC)
        1. 10.3.4.1 SC Features
        2. 10.3.4.2 SC Functional Description
          1. 10.3.4.2.1 Trimmer
          2. 10.3.4.2.2 1240
          3. 10.3.4.2.3 Peaking
          4. 10.3.4.2.4 Vertical Scaler
            1. 10.3.4.2.4.1 Running Average Filter
            2. 10.3.4.2.4.2 Vertical Scaler Configuration Parameters
          5. 10.3.4.2.5 Horizontal Scaler
            1. 10.3.4.2.5.1 Half Decimation Filter
            2. 10.3.4.2.5.2 Polyphase Filter
            3. 10.3.4.2.5.3 Nonlinear Horizontal Scaling
            4. 10.3.4.2.5.4 Horizontal Scaler Configuration Registers
          6. 10.3.4.2.6 Basic Configurations
          7. 10.3.4.2.7 Coefficient Memory
            1. 10.3.4.2.7.1 Overview
            2. 10.3.4.2.7.2 Physical Coefficient SRAM Layout
            3. 10.3.4.2.7.3 Scaler Coefficients Packing on 128-bit VPI Control I/F
            4. 10.3.4.2.7.4 VPI Control I/F Memory Map for Scaler Coefficients
            5. 10.3.4.2.7.5 VPI Control Interface
            6. 10.3.4.2.7.6 Coefficient Table Selection Guide
        3. 10.3.4.3 SC Code
          1. 10.3.4.3.1 Generate Coefficient Memory Image
          2. 10.3.4.3.2 Scaler Configuration Calculation
          3. 10.3.4.3.3 Typical Configuration Values
        4. 10.3.4.4 SC Coefficient Data Files
          1. 10.3.4.4.1 HS Polyphase Filter Coefficients
            1. 10.3.4.4.1.1 ppfcoef_scale_eq_1_32_phases_flip.dat
            2. 10.3.4.4.1.2 ppfcoef_scale_eq_8div16_32_phases_flip.dat
            3. 10.3.4.4.1.3 ppfcoef_scale_eq_9div16_32_phases_flip.dat
            4. 10.3.4.4.1.4 ppfcoef_scale_eq_10div16_32_phases_flip.dat
            5. 10.3.4.4.1.5 ppfcoef_scale_eq_11div16_32_phases_flip.dat
            6. 10.3.4.4.1.6 ppfcoef_scale_eq_12div16_32_phases_flip.dat
            7. 10.3.4.4.1.7 ppfcoef_scale_eq_13div16_32_phases_flip.dat
            8. 10.3.4.4.1.8 ppfcoef_scale_eq_14div16_32_phases_flip.dat
            9. 10.3.4.4.1.9 ppfcoef_scale_eq_15div16_32_phases_flip.dat
          2. 10.3.4.4.2 VS Polyphase Filter Coefficients
            1. 10.3.4.4.2.1 ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
            2. 10.3.4.4.2.2 ppfcoef_scale_eq_3_32_phases_flip.dat
            3. 10.3.4.4.2.3 ppfcoef_scale_eq_4_32_phases_flip.dat
            4. 10.3.4.4.2.4 ppfcoef_scale_eq_5_32_phases_flip.dat
            5. 10.3.4.4.2.5 ppfcoef_scale_eq_6_32_phases_flip.dat
            6. 10.3.4.4.2.6 ppfcoef_scale_eq_7_32_phases_flip.dat
              1. 10.3.4.4.2.6.1 ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
              2. 10.3.4.4.2.6.2 ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
              3. 10.3.4.4.2.6.3 ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
              4. 10.3.4.4.2.6.4 ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
              5. 10.3.4.4.2.6.5 ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
              6. 10.3.4.4.2.6.6 ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
              7. 10.3.4.4.2.6.7 ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
              8. 10.3.4.4.2.6.8 ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
              9. 10.3.4.4.2.6.9 ppcoef_scale_1x_ver_5tap.dat
          3. 10.3.4.4.3 VS (Bilinear Filter Coefficients)
            1. 10.3.4.4.3.1 ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
      5. 10.3.5  VPE Color Space Converter (CSC)
        1. 10.3.5.1 CSC Features
        2. 10.3.5.2 CSC Functional Description
        3. 10.3.5.3 1294
          1. 10.3.5.3.1 HDTV Application
            1. 10.3.5.3.1.1 HDTV Application with Video Data Range
            2. 10.3.5.3.1.2 HDTV Application with Graphics Data Range
            3. 10.3.5.3.1.3 Quantized Coefficients for Color Space Converter in HDTV
          2. 10.3.5.3.2 SDTV Application
            1. 10.3.5.3.2.1 SDTV Application with Video Data Range
            2. 10.3.5.3.2.2 SDTV Application with Graphics Data Range
            3. 10.3.5.3.2.3 Quantized Coefficients for Color Space Converter in SDTV
        4. 10.3.5.4 CSC Bypass Mode
      6. 10.3.6  VPE Chroma Up-Sampler (CHR_US)
        1. 10.3.6.1 Features
        2. 10.3.6.2 Functional Description
        3. 10.3.6.3 For Interlaced YUV420 Input Data
        4. 10.3.6.4 Edge Effects
        5. 10.3.6.5 Modes of Operation (VPDMA)
        6. 10.3.6.6 Coefficient Configuration
      7. 10.3.7  VPE Chroma Down-Sampler (CHR_DS)
      8. 10.3.8  VPE YUV422 to YUV444 Conversion
      9. 10.3.9  VPE Video Port Direct Memory Access (VPDMA)
        1. 10.3.9.1 VPDMA Introduction
        2. 10.3.9.2 VPDMA Basic Definitions
          1. 10.3.9.2.1 Client
          2. 10.3.9.2.2 Channel
          3. 10.3.9.2.3 List
          4. 10.3.9.2.4 Data Formats Supported
        3. 10.3.9.3 VPDMA Client Buffering and Functionality
        4. 10.3.9.4 VPDMA Channels Assignment
        5. 10.3.9.5 VPDMA Interrupts
        6. 10.3.9.6 VPDMA Descriptors
          1. 10.3.9.6.1 Data Transfer Descriptors
            1. 10.3.9.6.1.1 Data Packet Descriptor Word 0 (Data)
              1. 10.3.9.6.1.1.1 Data Type
              2. 10.3.9.6.1.1.2 Notify
              3. 10.3.9.6.1.1.3 Field
              4. 10.3.9.6.1.1.4 1D
              5. 10.3.9.6.1.1.5 Even Line Skip
              6. 10.3.9.6.1.1.6 Odd Line Skip
              7. 10.3.9.6.1.1.7 Line Stride
            2. 10.3.9.6.1.2 Data Packet Descriptor Word 1
              1. 10.3.9.6.1.2.1 Line Length
              2. 10.3.9.6.1.2.2 Transfer Height
            3. 10.3.9.6.1.3 Data Packet Descriptor Word 2
              1. 10.3.9.6.1.3.1 Start Address
            4. 10.3.9.6.1.4 Data Packet Descriptor Word 3
              1. 10.3.9.6.1.4.1 Packet Type
              2. 10.3.9.6.1.4.2 Mode
              3. 10.3.9.6.1.4.3 Direction
              4. 10.3.9.6.1.4.4 Channel
              5. 10.3.9.6.1.4.5 Priority
              6. 10.3.9.6.1.4.6 Next Channel
            5. 10.3.9.6.1.5 Data Packet Descriptor Word 4
              1. 10.3.9.6.1.5.1 Inbound data
                1. 10.3.9.6.1.5.1.1 Frame Width
                2. 10.3.9.6.1.5.1.2 Frame Height
              2. 10.3.9.6.1.5.2 Outbound data
                1. 10.3.9.6.1.5.2.1 Descriptor Write Address
                2. 10.3.9.6.1.5.2.2 Write Descriptor
                3. 10.3.9.6.1.5.2.3 Drop Data
                4. 10.3.9.6.1.5.2.4 Use Descriptor Register
            6. 10.3.9.6.1.6 Data Packet Descriptor Word 5
              1. 10.3.9.6.1.6.1 Outbound data
                1. 10.3.9.6.1.6.1.1 Max Width
                2. 10.3.9.6.1.6.1.2 Max Height
            7. 10.3.9.6.1.7 Data Packet Descriptor Word 6/7 (Data)
          2. 10.3.9.6.2 Configuration Descriptor
            1. 10.3.9.6.2.1 Configuration Descriptor Header Word0
            2. 10.3.9.6.2.2 Configuration Descriptor Header Word1
              1. 10.3.9.6.2.2.1 Number of Data Words
            3. 10.3.9.6.2.3 Configuration Descriptor Header Word2
              1. 10.3.9.6.2.3.1 Payload Location
            4. 10.3.9.6.2.4 Configuration Descriptor Header Word3
              1. 10.3.9.6.2.4.1 Packet Type
              2. 10.3.9.6.2.4.2 Direct
              3. 10.3.9.6.2.4.3 Class
                1. 10.3.9.6.2.4.3.1 Address Data Block Format
              4. 10.3.9.6.2.4.4 Destination
              5. 10.3.9.6.2.4.5 Descriptor Length
          3. 10.3.9.6.3 Control Descriptor
            1. 10.3.9.6.3.1 Generic Control Descriptor Format
            2. 10.3.9.6.3.2 Control Descriptor Header Description
              1. 10.3.9.6.3.2.1 Packet Type
              2. 10.3.9.6.3.2.2 Source
              3. 10.3.9.6.3.2.3 Control
            3. 10.3.9.6.3.3 Control Descriptor Types
              1. 10.3.9.6.3.3.1 Sync on Client
              2. 10.3.9.6.3.3.2 Sync on List
              3. 10.3.9.6.3.3.3 Sync on External Event
              4. 10.3.9.6.3.3.4 Sync on Channel
              5. 10.3.9.6.3.3.5 Sync on LM Timer
              6. 10.3.9.6.3.3.6 Change Client Interrupt
              7. 10.3.9.6.3.3.7 Send Interrupt
              8. 10.3.9.6.3.3.8 Reload List
              9. 10.3.9.6.3.3.9 Abort Channel
        7. 10.3.9.7 VPDMA Configuration
          1. 10.3.9.7.1 Regular List
          2. 10.3.9.7.2 Video Input Ports
            1. 10.3.9.7.2.1 Single YUV Color Separate
            2. 10.3.9.7.2.2 Dual YUV Interleaved
            3. 10.3.9.7.2.3 Single RGB Stream
        8. 10.3.9.8 VPDMA Data Formats
          1. 10.3.9.8.1 YUV Data Formats
            1. 10.3.9.8.1.1 Y 4:4:4 (Data Type 0)
            2. 10.3.9.8.1.2 Y 4:2:2 (Data Type 1)
            3. 10.3.9.8.1.3 Y 4:2:0 (Data Type 2)
            4. 10.3.9.8.1.4 C 4:4:4 (Data Type 4)
            5. 10.3.9.8.1.5 C 4:2:2 (Data Type 5)
            6. 10.3.9.8.1.6 C 4:2:0 (Data Type 6)
            7. 10.3.9.8.1.7 YC 4:2:2 (Data Type 7)
            8. 10.3.9.8.1.8 YC 4:4:4 (Data Type 8)
            9. 10.3.9.8.1.9 CY 4:2:2 (Data Type 23)
          2. 10.3.9.8.2 RGB Data Formats
            1. 10.3.9.8.2.1 Input Data Formats
              1. 10.3.9.8.2.1.1  RGB16-565 (Data Type 0)
              2. 10.3.9.8.2.1.2  ARGB-1555 (Data Type 1)
              3. 10.3.9.8.2.1.3  ARGB-4444 (Data Type 2)
              4. 10.3.9.8.2.1.4  RGBA-5551 (Data Type 3)
              5. 10.3.9.8.2.1.5  RGBA-4444 (Data Type 4)
              6. 10.3.9.8.2.1.6  ARGB24-6666 (Data Type 5)
              7. 10.3.9.8.2.1.7  RGB24-888 (Data Type 6)
              8. 10.3.9.8.2.1.8  ARGB32-8888 (Data Type 7)
              9. 10.3.9.8.2.1.9  RGBA24-6666 (Data Type 8)
              10. 10.3.9.8.2.1.10 RGBA32-8888 (Data Type 9)
            2. 10.3.9.8.2.2 Output Data Formats
              1. 10.3.9.8.2.2.1  RGB16-565 (Data Type 0)
              2. 10.3.9.8.2.2.2  ARGB-1555 (Data Type 1)
              3. 10.3.9.8.2.2.3  ARGB-4444 (Data Type 2)
              4. 10.3.9.8.2.2.4  RGBA-5551 (Data Type 3)
              5. 10.3.9.8.2.2.5  RGBA-4444 (Data Type 4)
              6. 10.3.9.8.2.2.6  ARGB24-6666 (Data Type 5)
              7. 10.3.9.8.2.2.7  RGB24-888 (Data Type 6)
              8. 10.3.9.8.2.2.8  ARGB32-8888 (Data Type 7)
              9. 10.3.9.8.2.2.9  RGBA24-6666 (Data Type 8)
              10. 10.3.9.8.2.2.10 RGBA32-8888 (Data Type 9)
          3. 10.3.9.8.3 Miscellaneous Data Type
      10. 10.3.10 VPE Software Reset
      11. 10.3.11 VPE Power and Clocks Management
        1. 10.3.11.1 VPE Clocks
        2. 10.3.11.2 VPE Idle Mode
        3. 10.3.11.3 VPE StandBy Mode
    4. 10.4 VPE Register Manual
      1. 10.4.1 VPE Instance Summary
      2. 10.4.2 VPE_CSC Registers
        1. 10.4.2.1 VPE_CSC Register Summary
        2. 10.4.2.2 VPE_CSC Register Description
      3. 10.4.3 VPE_SC Registers
        1. 10.4.3.1 VPE_SC Register Summary
        2. 10.4.3.2 VPE_SC Register Description
      4. 10.4.4 VPE_CHR_US Registers
        1. 10.4.4.1 VPE_CHR_US Register Summary
        2. 10.4.4.2 VPE_CHR_US Register Description
      5. 10.4.5 VPE_DEI Registers
        1. 10.4.5.1 VPE_DEI Register Summary
        2. 10.4.5.2 VPE_DEI Register Description
      6. 10.4.6 VPE_VPDMA Registers
        1. 10.4.6.1 VPE_VPDMA Register Summary
        2. 10.4.6.2 VPE_VPDMA Register Description
      7. 10.4.7 VPE_TOP_LEVEL Registers
        1. 10.4.7.1 VPE_TOP_LEVEL Register Summary
        2. 10.4.7.2 VPE_TOP_LEVEL Register Description
  13. 11Display Subsystem
    1. 11.1 Display Subsystem Overview
      1. 11.1.1 Display Subsystem Environment
        1. 11.1.1.1 Display Subsystem LCD Support
          1. 11.1.1.1.1 Display Subsystem LCD with Parallel Interfaces
        2. 11.1.1.2 Display Subsystem TV Display Support
          1. 11.1.1.2.1 Display Subsystem TV With Parallel Interfaces
          2. 11.1.1.2.2 Display Subsystem TV With Serial Interfaces
      2. 11.1.2 Display Subsystem Integration
        1. 11.1.2.1 Display Subsystem Clocks
        2. 11.1.2.2 Display Subsystem Resets
        3. 11.1.2.3 Display Subsystem Power Management
          1. 11.1.2.3.1 Display Subsystem Standby Mode
          2. 11.1.2.3.2 1467
          3. 11.1.2.3.3 Display Subsystem Wake-Up Mode
      3. 11.1.3 Display Subsystem DPLL Controllers Functional Description
        1. 11.1.3.1 DPLL Controllers Overview
        2. 11.1.3.2 OCP2SCP2 Functional Description
          1. 11.1.3.2.1 OCP2SCP2 Reset
            1. 11.1.3.2.1.1 Hardware Reset
            2. 11.1.3.2.1.2 Software Reset
          2. 11.1.3.2.2 OCP2SCP2 Power Management
            1. 11.1.3.2.2.1 Idle Mode
            2. 11.1.3.2.2.2 Clock Gating
          3. 11.1.3.2.3 OCP2SCP2 Timing Registers
        3. 11.1.3.3 DPLL_VIDEO Functional Description
          1. 11.1.3.3.1 DPLL_VIDEO Controller Architecture
          2. 11.1.3.3.2 DPLL_VIDEO Operations
          3. 11.1.3.3.3 DPLL_VIDEO Error Handling
          4. 11.1.3.3.4 DPLL_VIDEO Software Reset
          5. 11.1.3.3.5 DPLL_VIDEO Power Management
          6. 11.1.3.3.6 DPLL_VIDEO HSDIVIDER Loading Operation
          7. 11.1.3.3.7 DPLL_VIDEO Clock Sequence
          8. 11.1.3.3.8 DPLL_VIDEO Go Sequence
          9. 11.1.3.3.9 DPLL_VIDEO Recommended Values
        4. 11.1.3.4 DPLL_HDMI Functional Description
          1. 11.1.3.4.1  DPLL_HDMI and PLLCTRL_HDMI Overview
          2. 11.1.3.4.2  DPLL_HDMI and PLLCTRL_HDMI Architecture
          3. 11.1.3.4.3  DPLL_HDMI Operations
          4. 11.1.3.4.4  DPLL_HDMI Register Access
          5. 11.1.3.4.5  DPLL_HDMI Error Handling
          6. 11.1.3.4.6  DPLL_HDMI Software Reset
          7. 11.1.3.4.7  DPLL_HDMI Power Management
          8. 11.1.3.4.8  DPLL_HDMI Lock Sequence
          9. 11.1.3.4.9  DPLL_HDMI Go Sequence
          10. 11.1.3.4.10 DPLL_HDMI Recommended Values
      4. 11.1.4 Display Subsystem Programming Guide
      5. 11.1.5 Display Subsystem Register Manual
        1. 11.1.5.1 Display Subsystem Instance Summary
        2. 11.1.5.2 Display Subsystem Registers
          1. 11.1.5.2.1 Display Subsystem Registers Mapping Summary
          2. 11.1.5.2.2 Display Subsystem Register Description
        3. 11.1.5.3 OCP2SCP2 registers
          1. 11.1.5.3.1 OCP2SCP2 Register Summary
          2. 11.1.5.3.2 OCP2SCP Register Description
        4. 11.1.5.4 DPLL_VIDEO Registers
          1. 11.1.5.4.1 DPLL_VIDEO Register Summary
          2. 11.1.5.4.2 DPLL_VIDEO Register Description
        5. 11.1.5.5 DPLL_HDMI Registers
          1. 11.1.5.5.1 DPLL_HDMI Registers Mapping Summary
          2. 11.1.5.5.2 DPLL_HDMI Register Description
        6. 11.1.5.6 HDMI_WP Registers
          1. 11.1.5.6.1 HDMI_WP Registers Mapping Summary
          2. 11.1.5.6.2 HDMI_WP Register Description
        7. 11.1.5.7 DSI Registers
          1. 11.1.5.7.1 DSI Register Summary
          2. 11.1.5.7.2 DSI Register Description
    2. 11.2 Display Controller
      1. 11.2.1 DISPC Overview
      2. 11.2.2 DISPC Environment
        1. 11.2.2.1 DISPC LCD Output and Data Format for the Parallel Interface
        2. 11.2.2.2 DISPC Transaction Timing Diagrams
        3. 11.2.2.3 DISPC TV Output and Data Format for the Parallel Interface
      3. 11.2.3 DISPC Integration
      4. 11.2.4 DISPC Functional Description
        1. 11.2.4.1  DISPC Clock Configuration
        2. 11.2.4.2  DISPC Software Reset
        3. 11.2.4.3  DISPC Power Management
          1. 11.2.4.3.1 DISPC Idle Mode
          2. 11.2.4.3.2 DISPC StandBy Mode
          3. 11.2.4.3.3 DISPC Wakeup
        4. 11.2.4.4  DISPC Interrupt Requests
        5. 11.2.4.5  DISPC DMA Requests
        6. 11.2.4.6  DISPC DMA Engine
          1. 11.2.4.6.1 DISPC Addressing and Bursts
          2. 11.2.4.6.2 DISPC Immediate Base Address Flip Mechanism
          3. 11.2.4.6.3 DISPC DMA Buffers
            1. 11.2.4.6.3.1 DISPC READ DMA Buffers (GFX and VID Pipelines)
            2. 11.2.4.6.3.2 DISPC WRITE DMA Buffer (WB Pipeline)
          4. 11.2.4.6.4 DISPC MFLAG Mechanism and Arbitration
          5. 11.2.4.6.5 DISPC Predecimation
          6. 11.2.4.6.6 DISPC Progressive-to-Interlaced Format Conversion
          7. 11.2.4.6.7 DISPC Arbitration
          8. 11.2.4.6.8 DISPC DMA Power Modes
            1. 11.2.4.6.8.1 DISPC DMA Low-Power Mode
            2. 11.2.4.6.8.2 DISPC DMA Ultralow-Power Mode
        7. 11.2.4.7  DISPC Rotation and Mirroring
        8. 11.2.4.8  DISPC Memory Format
        9. 11.2.4.9  DISPC Graphics Pipeline
          1. 11.2.4.9.1 DISPC Replication Logic
          2. 11.2.4.9.2 DISPC Antiflicker Filter
        10. 11.2.4.10 DISPC Video Pipelines
          1. 11.2.4.10.1 DISPC Replication Logic
          2. 11.2.4.10.2 DISPC VC-1 Range Mapping Unit
          3. 11.2.4.10.3 DISPC CSC Unit YUV to RGB
            1. 11.2.4.10.3.1 DISPC Chrominance Resampling
          4. 11.2.4.10.4 DISPC Scaler Unit
            1. 11.2.4.10.4.1 DISPC Scaling Algorithms
            2. 11.2.4.10.4.2 DISPC Scaling limitations
        11. 11.2.4.11 DISPC Write-Back Pipeline
          1. 11.2.4.11.1 DISPC Write-Back CSC Unit RGB to YUV
          2. 11.2.4.11.2 DISPC Write-Back Scaler Unit
          3. 11.2.4.11.3 DISPC Write-Back RGB Truncation Logic
        12. 11.2.4.12 DISPC Hardware Cursor
        13. 11.2.4.13 DISPC LCD Outputs
          1. 11.2.4.13.1 DISPC Overlay Manager
            1. 11.2.4.13.1.1 DISPC Priority Rule
            2. 11.2.4.13.1.2 DISPC Alpha Blender
            3. 11.2.4.13.1.3 DISPC Transparency Color Keys
            4. 11.2.4.13.1.4 DISPC Overlay Optimization
          2. 11.2.4.13.2 DISPC Gamma Correction Unit
          3. 11.2.4.13.3 DISPC Color Phase Rotation Unit
          4. 11.2.4.13.4 DISPC Color Space Conversion
          5. 11.2.4.13.5 DISPC BT.656 and BT.1120 Modes
            1. 11.2.4.13.5.1 Blanking
            2. 11.2.4.13.5.2 EAV and SAV
          6. 11.2.4.13.6 DISPC Active Matrix
            1. 11.2.4.13.6.1 DISPC Spatial/Temporal Dithering
            2. 11.2.4.13.6.2 DISPC Multiple Cycle Output Format (TDM)
          7. 11.2.4.13.7 DISPC Synchronized Buffer Update
          8. 11.2.4.13.8 DISPC Timing Generator and Panel Settings
        14. 11.2.4.14 DISPC TV Output
          1. 11.2.4.14.1 DISPC Overlay Manager
          2. 11.2.4.14.2 DISPC Gamma Correction Unit
          3. 11.2.4.14.3 DISPC Synchronized Buffer Update
          4. 11.2.4.14.4 DISPC Timing and TV Format Settings
        15. 11.2.4.15 DISPC Frame Width Considerations
        16. 11.2.4.16 DISPC Extended 3D Support
          1. 11.2.4.16.1 DISPC Extended 3D Support - Line Alternative Format
          2. 11.2.4.16.2 1593
          3. 11.2.4.16.3 DISPC Extended 3D Support - Frame Packing Format Format
          4. 11.2.4.16.4 DISPC Extended 3D Support - DLP 3D Format
        17. 11.2.4.17 DISPC Shadow Registers
      5. 11.2.5 DISPC Programming Guide
        1. 11.2.5.1 DISPC Low-Level Programming Models
          1. 11.2.5.1.1 DISPC Global Initialization
            1. 11.2.5.1.1.1 DISPC Surrounding Modules Global Initialization
          2. 11.2.5.1.2 DISPC Operational Modes Configuration
            1. 11.2.5.1.2.1 DISPC DMA Configuration
              1. 11.2.5.1.2.1.1 DISPC Main Sequence – DISPC DMA Channel Configuration
            2. 11.2.5.1.2.2 DISPC GFX Pipeline Configuration
              1. 11.2.5.1.2.2.1 DISPC Main Sequence – Configure the GFX Pipeline
              2. 11.2.5.1.2.2.2 DISPC Subsequence – Configure the GFX Window
              3. 11.2.5.1.2.2.3 DISPC Subsequence – Configure the GFX Pipeline Processing
              4. 11.2.5.1.2.2.4 DISPC Subsequence – Configure the GFX Pipeline Layer Output
            3. 11.2.5.1.2.3 DISPC Video Pipeline Configuration
              1. 11.2.5.1.2.3.1 DISPC Main Sequence – Configure the Video Pipeline
              2. 11.2.5.1.2.3.2 DISPC Subsequence – Configure the Video Window
              3. 11.2.5.1.2.3.3 DISPC Subsequence – Configure the Video Pipeline Processing
              4. 11.2.5.1.2.3.4 DISPC Subsequence – Configure the VC-1 Range Mapping
              5. 11.2.5.1.2.3.5 DISPC Subsequence – Configure the Video Color Space Conversion
              6. 11.2.5.1.2.3.6 DISPC Subsequence – Configure the Video Scaler Unit
              7. 11.2.5.1.2.3.7 DISPC Subsequence – Configure the Video Pipeline Layer Output
            4. 11.2.5.1.2.4 DISPC WB Pipeline Configuration
              1. 11.2.5.1.2.4.1 DISPC Main Sequence – Configure the WB Pipeline
              2. 11.2.5.1.2.4.2 DISPC Subsequence – Configure the Capture Window
              3. 11.2.5.1.2.4.3 DISPC Subsequence – Configure the WB Scaler Unit
              4. 11.2.5.1.2.4.4 DISPC Subsequence – Configure the WB Color Space Conversion Unit
            5. 11.2.5.1.2.5 DISPC LCD Output Configuration
              1. 11.2.5.1.2.5.1 DISPC Main Sequence – Configure the LCD Output
              2. 11.2.5.1.2.5.2 DISPC Subsequence – Configure the Overlay Manager
              3. 11.2.5.1.2.5.3 DISPC Subsequence – Configure the Gamma Table for Gamma Correction
              4. 11.2.5.1.2.5.4 DISPC Subsequence – Configure the Color Phase Rotation
              5. 11.2.5.1.2.5.5 DISPC Subsequence – Configure the LCD Panel Timings and Parameters
              6. 11.2.5.1.2.5.6 DISPC Subsequence – Configure BT.656 or BT.1120 Mode
            6. 11.2.5.1.2.6 DISPC TV Output Configuration
              1. 11.2.5.1.2.6.1 DISPC Main Sequence – Configure the TV Output
                1. 11.2.5.1.2.6.1.1 DISPC Subsequence – Configure the TV Overlay Manager
                2. 11.2.5.1.2.6.1.2 DISPC Subsequence – Configure the Gamma Table for Gamma Correction
                3. 11.2.5.1.2.6.1.3 DISPC Subsequence – Configure the TV Panel Timings and Parameters
      6. 11.2.6 DISPC Register Manual
        1. 11.2.6.1 DISPC Instance Summary
        2. 11.2.6.2 DISPC Logical Register Mapping
        3. 11.2.6.3 DISPC Registers
          1. 11.2.6.3.1 DISPC Register Summary
          2. 11.2.6.3.2 DISPC Register Description
    3. 11.3 High-Definition Multimedia Interface
      1. 11.3.1 HDMI Overview
        1. 11.3.1.1 HDMI Main Features
        2. 11.3.1.2 HDMI Video Formats and Timings
          1. 11.3.1.2.1 HDMI CEA-861-D Video Formats and Timings
          2. 11.3.1.2.2 VESA DMT Video Formats and Timings
  14. 123D Graphics Accelerator
    1. 12.1 GPU Overview
      1. 12.1.1 GPU Features Overview
      2. 12.1.2 Graphics Feature Overview
    2. 12.2 GPU Integration
    3. 12.3 GPU Functional Description
      1. 12.3.1 GPU Block Diagram
      2. 12.3.2 GPU Clock Configuration
      3. 12.3.3 GPU Software Reset
      4. 12.3.4 GPU Power Management
      5. 12.3.5 GPU Thermal Management
      6. 12.3.6 GPU Interrupt Requests
    4. 12.4 GPU Register Manual
      1. 12.4.1 GPU Instance Summary
      2. 12.4.2 GPU Registers
        1. 12.4.2.1 GPU_WRAPPER Register Summary
        2. 12.4.2.2 GPU_WRAPPER Register Description
  15. 132D Graphics Accelerator
    1. 13.1 BB2D Overview
      1. 13.1.1 BB2D Key Features Overview
    2. 13.2 BB2D Integration
    3. 13.3 BB2D Functional Description
      1. 13.3.1 BB2D Block Diagram
      2. 13.3.2 BB2D Clock Configuration
      3. 13.3.3 BB2D Software Reset
      4. 13.3.4 BB2D Power Management
    4. 13.4 BB2D Register Manual
      1. 13.4.1 BB2D Instance Summary
      2. 13.4.2 BB2D Registers
        1. 13.4.2.1 BB2D Register Summary
        2. 13.4.2.2 BB2D Register Description
  16. 14Interconnect
    1. 14.1 Interconnect Overview
      1. 14.1.1 Terminology
      2. 14.1.2 Architecture Overview
    2. 14.2 L3_MAIN Interconnect
      1. 14.2.1 L3_MAIN Interconnect Overview
      2. 14.2.2 L3_MAIN Interconnect Integration
      3. 14.2.3 L3_MAIN Interconnect Functional Description
        1. 14.2.3.1 Module Use in L3_MAIN Interconnect
        2. 14.2.3.2 Module Distribution
          1. 14.2.3.2.1 L3_MAIN Interconnect Agents
          2. 14.2.3.2.2 L3_MAIN Connectivity Matrix
            1. 14.2.3.2.2.1 Clock Domain Mapping of the L3_MAIN Interconnect Modules
            2. 14.2.3.2.2.2 1690
          3. 14.2.3.2.3 Master NIU Identification
        3. 14.2.3.3 Bandwidth Regulators
        4. 14.2.3.4 Bandwidth Limiters
        5. 14.2.3.5 Flag Muxing
          1. 14.2.3.5.1 Flag Mux Time-out
        6. 14.2.3.6 Statistic Collectors Group
        7. 14.2.3.7 L3_MAIN Protection and Firewalls
          1. 14.2.3.7.1 L3_MAIN Firewall Reset
            1. 14.2.3.7.1.1 L3_MAIN Firewall – Exported Reset Values
          2. 14.2.3.7.2 Power Management
          3. 14.2.3.7.3 L3_MAIN Firewall Functionality
            1. 14.2.3.7.3.1 Protection Regions
            2. 14.2.3.7.3.2 L3_MAIN Firewall Registers Overview
            3. 14.2.3.7.3.3 Protection Mechanism per Region Examples
            4. 14.2.3.7.3.4 L3_MAIN Firewall Error Logging
            5. 14.2.3.7.3.5 L3_MAIN Firewall Default Configuration
        8. 14.2.3.8 L3_MAIN Interconnect Error Handling
          1. 14.2.3.8.1 Global Error-Routing Scheme
          2. 14.2.3.8.2 Slave NIU Error Logging
          3. 14.2.3.8.3 Flag Mux Error Logging
          4. 14.2.3.8.4 Severity Level of Standard and Custom Errors
          5. 14.2.3.8.5 Example for Decoding Standard/Custom Errors Logged in L3_MAIN
      4. 14.2.4 L3_MAIN Interconnect Programming Guide
        1. 14.2.4.1 L3 _MAIN Interconnect Low-Level Programming Models
          1. 14.2.4.1.1 Global Initialization
            1. 14.2.4.1.1.1 Global Initialization of Surrounding Modules
        2. 14.2.4.2 Operational Modes Configuration
          1. 14.2.4.2.1 L3_MAIN Interconnect Error Analysis Mode
            1. 14.2.4.2.1.1 Main Sequence: L3_MAIN Interconnect Error Analysis Mode
              1. 14.2.4.2.1.1.1 Subsequence: L3_MAIN Custom Error Identification
              2. 14.2.4.2.1.1.2 Subsequence: L3_MAIN Interconnect Protection Violation Error Identification
              3. 14.2.4.2.1.1.3 Subsequence: L3_MAIN Interconnect Standard Error Identification
              4. 14.2.4.2.1.1.4 Subsequence: L3_MAIN Interconnect FLAGMUX Configuration
      5. 14.2.5 L3_MAIN Interconnect Register Manual
        1. 14.2.5.1 L3_MAIN Register Group Summary
          1. 14.2.5.1.1 L3_MAIN Firewall Registers Summary and Description
            1. 14.2.5.1.1.1 L3_MAIN Firewall Registers Summary
            2. 14.2.5.1.1.2 L3_MAIN Firewall Registers Description
          2. 14.2.5.1.2 L3_MAIN Host Register Summary and Description
            1. 14.2.5.1.2.1 L3_MAIN HOST Register Summary
            2. 14.2.5.1.2.2 L3_MAIN HOST Register Description
          3. 14.2.5.1.3 L3_MAIN TARG Register Summary and Description
            1. 14.2.5.1.3.1 L3_MAIN TARG Register Summary
            2. 14.2.5.1.3.2 L3_MAIN TARG Register Description
          4. 14.2.5.1.4 L3_MAIN FLAGMUX Registers Summary and Description
            1. 14.2.5.1.4.1 L3_MAIN FLAGMUX Registers Summary
            2. 14.2.5.1.4.2 L3_MAIN FLAGMUX Rebisters Description
          5. 14.2.5.1.5 L3_MAIN FLAGMUX CLK1MERGE Registers Summary and Description
            1. 14.2.5.1.5.1 L3_MAIN FLAGMUX CLK1MERGE Registers Summary
            2. 14.2.5.1.5.2 L3_MAIN FLAGMUX CLK1MERGE Registers Description
          6. 14.2.5.1.6 L3_MAIN FLAGMUX TIMEOUT Registers Summary and Description
            1. 14.2.5.1.6.1 L3_MAIN FLAGMUX TIMEOUT Registers Summary
            2. 14.2.5.1.6.2 L3_MAIN FLAGMUX TIMEOUT Registers Description
          7. 14.2.5.1.7 L3_MAIN BW Regulator Register Summary and Description
            1. 14.2.5.1.7.1 L3_MAIN BW_REGULATOR Register Summary
            2. 14.2.5.1.7.2 L3_MAIN BW_REGULATOR Register Description
          8. 14.2.5.1.8 L3_MAIN Bandwidth Limiter Register Summary and Description
            1. 14.2.5.1.8.1 L3_MAIN BW Limiter Register Summary
            2. 14.2.5.1.8.2 L3_MAIN BW Limiter Register Description
          9. 14.2.5.1.9 L3_MAIN STATCOLL Register Summary and Description
            1. 14.2.5.1.9.1 L3_MAIN STATCOLL Register Summary
            2. 14.2.5.1.9.2 L3_MAIN STATCOLL Register Description
    3. 14.3 L4 Interconnects
      1. 14.3.1 L4 Interconnect Overview
      2. 14.3.2 L4 Interconnect Integration
      3. 14.3.3 L4 Interconnect Functional Description
        1. 14.3.3.1 Module Distribution
          1. 14.3.3.1.1 L4_PER1 Interconnect Agents
          2. 14.3.3.1.2 L4_PER2 Interconnect Agents
          3. 14.3.3.1.3 L4_PER3 Interconnect Agents
          4. 14.3.3.1.4 L4_CFG Interconnect Agents
          5. 14.3.3.1.5 L4_WKUP Interconnect Agents
        2. 14.3.3.2 Power Management
        3. 14.3.3.3 L4 Firewalls
          1. 14.3.3.3.1 Protection Group
          2. 14.3.3.3.2 Segments and Regions
          3. 14.3.3.3.3 L4 Firewall Address and Protection Register Settings
        4. 14.3.3.4 L4 Error Detection and Reporting
          1. 14.3.3.4.1 IA and TA Error Detection and Logging
          2. 14.3.3.4.2 Time-Out
          3. 14.3.3.4.3 Error Reporting
          4. 14.3.3.4.4 Error Recovery
          5. 14.3.3.4.5 Firewall Error Logging in the Control Module
      4. 14.3.4 L4 Interconnect Programming Guide
        1. 14.3.4.1 L4 Interconnect Low-level Programming Models
          1. 14.3.4.1.1 Global Initialization
            1. 14.3.4.1.1.1 Surrounding Modules Global Initialization
          2. 14.3.4.1.2 Operational Modes Configuration
            1. 14.3.4.1.2.1 L4 Interconnect Error Analysis Mode
              1. 14.3.4.1.2.1.1 Main Sequence: L4 Interconnect Error Analysis Mode
              2. 14.3.4.1.2.1.2 Subsequence: L4 Interconnect Protection Violation Error Identification
              3. 14.3.4.1.2.1.3 Subsequence: L4 Interconnect Unsupported Command/Address Hole Error Identification
              4. 14.3.4.1.2.1.4 Subsequence: L4 Interconnect Reset TA and Module
            2. 14.3.4.1.2.2 L4 Interconnect Time-Out Configuration Mode
              1. 14.3.4.1.2.2.1 Main Sequence: L4 Interconnect Time-Out Configuration Mode
            3. 14.3.4.1.2.3 L4 Interconnect Firewall Configuration Mode
              1. 14.3.4.1.2.3.1 Main Sequence: L4 Interconnect Firewall Configuration Mode
      5. 14.3.5 L4 Interconnects Register Manual
        1. 14.3.5.1 L4 Interconnects Instance Summary
        2. 14.3.5.2 L4 Initiator Agent (L4 IA)
          1. 14.3.5.2.1 L4 Initiator Agent (L4 IA) Register Summary
          2. 14.3.5.2.2 L4 Initiator Agent (L4 IA) Register Description
        3. 14.3.5.3 L4 Target Agent (L4 TA)
          1. 14.3.5.3.1 L4 Target Agent (L4 TA) Register Summary
          2. 14.3.5.3.2 L4 Target Agent (L4 TA) Register Description
        4. 14.3.5.4 L4 Link Agent (L4 LA)
          1. 14.3.5.4.1 L4 Link Agent (L4 LA) Register Summary
          2. 14.3.5.4.2 L4 Link Agent (L4 LA) Register Description
        5. 14.3.5.5 L4 Address Protection (L4 AP)
          1. 14.3.5.5.1 L4 Address Protection (L4 AP) Register Summary
          2. 14.3.5.5.2 L4 Address Protection (L4 AP) Register Description
  17. 15Memory Subsystem
    1. 15.1 Memory Subsystem Overview
      1. 15.1.1 DMM Overview
      2. 15.1.2 TILER Overview
      3. 15.1.3 EMIF Overview
      4. 15.1.4 GPMC Overview
      5. 15.1.5 ELM Overview
      6. 15.1.6 OCM Overview
    2. 15.2 Dynamic Memory Manager
      1. 15.2.1 DMM Overview
      2. 15.2.2 DMM Integration
        1. 15.2.2.1 DMM Configuration
      3. 15.2.3 DMM Functional Description
        1. 15.2.3.1 DMM Block Diagram
        2. 15.2.3.2 DMM Clock Configuration
        3. 15.2.3.3 DMM Power Management
        4. 15.2.3.4 DMM Interrupt Requests
        5. 15.2.3.5 DMM
          1. 15.2.3.5.1 DMM Concepts
            1. 15.2.3.5.1.1 Dynamic Mapping
            2. 15.2.3.5.1.2 Address Mapping
            3. 15.2.3.5.1.3 Address Translation
              1. 15.2.3.5.1.3.1 PAT View Mappings
              2. 15.2.3.5.1.3.2 PAT View Map Base Address
              3. 15.2.3.5.1.3.3 PAT Views
                1. 15.2.3.5.1.3.3.1 PAT Direct Access Translation
                2. 15.2.3.5.1.3.3.2 PAT Indirect Access Translation
                3. 15.2.3.5.1.3.3.3 PAT View Configuration
                4. 15.2.3.5.1.3.3.4 PAT Address Translation LUT
                5. 15.2.3.5.1.3.3.5 Direct Access to the PAT Table Vectors
                6. 15.2.3.5.1.3.3.6 Automatic Refill Through the Refill Engines
          2. 15.2.3.5.2 DMM Transaction Flows
            1. 15.2.3.5.2.1 Nontiled Transaction Flow
            2. 15.2.3.5.2.2 Tiled Transaction Flow
          3. 15.2.3.5.3 DMM Internal Macro-Architecture
            1. 15.2.3.5.3.1 LISA Description
            2. 15.2.3.5.3.2 PAT Description
            3. 15.2.3.5.3.3 PEG Description
            4. 15.2.3.5.3.4 LISA Interconnect Arbitration
            5. 15.2.3.5.3.5 ROBIN Description
            6. 15.2.3.5.3.6 TILER Description
        6. 15.2.3.6 TILER
          1. 15.2.3.6.1 TILER Concepts
            1. 15.2.3.6.1.1 TILER Rationale
              1. 15.2.3.6.1.1.1 The TILER is a 4-GiB Virtual Address Space Composed of Eight Views
              2. 15.2.3.6.1.1.2 A View is a 512-MiB Virtual Address Space Composed of Four Containers
              3. 15.2.3.6.1.1.3 A Container is a 128-MiB Virtual Address Space
              4. 15.2.3.6.1.1.4 A Page is a 4-kiB Virtual Address Space
              5. 15.2.3.6.1.1.5 A Tile is a 1-kiB Address Space
              6. 15.2.3.6.1.1.6 1851
              7. 15.2.3.6.1.1.7 A Subtile is a 128-Bit Address Space
            2. 15.2.3.6.1.2 TILER Modes
              1. 15.2.3.6.1.2.1 Bypass Mode
              2. 15.2.3.6.1.2.2 Page Mode
              3. 15.2.3.6.1.2.3 Tiled Mode
            3. 15.2.3.6.1.3 Object Container Definition
            4. 15.2.3.6.1.4 Page Definition
              1. 15.2.3.6.1.4.1 Container Geometry With 4-kiB Pages
              2. 15.2.3.6.1.4.2 Container Geometry and Page Mapping Summary
            5. 15.2.3.6.1.5 Orientation
            6. 15.2.3.6.1.6 Tile Definition
            7. 15.2.3.6.1.7 Subtiles
              1. 15.2.3.6.1.7.1 Subtiling Definition
            8. 15.2.3.6.1.8 TILER Virtual Addressing
              1. 15.2.3.6.1.8.1 Page Mode Virtual Addressing and Characteristics
              2. 15.2.3.6.1.8.2 Tiled Mode Virtual Addressing and Characteristics
              3. 15.2.3.6.1.8.3 Element Ordering in the TILER Container
                1. 15.2.3.6.1.8.3.1 Natural View or 0-Degree View (Orientation 0)
                2. 15.2.3.6.1.8.3.2 0-Degree View With Vertical Mirror or 180-Degree View With Horizontal Mirror (Orientation 1)
                3. 15.2.3.6.1.8.3.3 0-Degree View With Horizontal Mirror or 180-Degree View With Vertical Mirror (Orientation 2)
                4. 15.2.3.6.1.8.3.4 180-Degree View (Orientation 3)
                5. 15.2.3.6.1.8.3.5 90-Degree View With Vertical Mirror or 270-Degree View With Horizontal Mirror (Orientation 4)
                6. 15.2.3.6.1.8.3.6 270-Degree View (Orientation 5)
                7. 15.2.3.6.1.8.3.7 90-Degree View (Orientation 6)
                8. 15.2.3.6.1.8.3.8 90-Degree View With Horizontal Mirror or 270-Degree View With Vertical Mirror (Orientation 7)
          2. 15.2.3.6.2 TILER Macro-Architecture
          3. 15.2.3.6.3 TILER Guidelines for Initiators
            1. 15.2.3.6.3.1 Buffered Raster-Based Initiators
              1. 15.2.3.6.3.1.1 Buffer Size
              2. 15.2.3.6.3.1.2 Performance
      4. 15.2.4 DMM Use Cases and Tips
        1. 15.2.4.1 PAT Use Cases
          1. 15.2.4.1.1 Simple Manual Area Refill
          2. 15.2.4.1.2 Single Auto-Configured Area Refill
          3. 15.2.4.1.3 Chained Auto-Configured Area Refill
          4. 15.2.4.1.4 Synchronized Auto-Configured Area Refill
          5. 15.2.4.1.5 Cyclic Synchronized Auto-Configured Area Refill
        2. 15.2.4.2 Addressing Management with LISA
          1. 15.2.4.2.1 Case 1: Use of One Memory Controller
      5. 15.2.5 DMM Basic Programming Model
        1. 15.2.5.1 Global Initialization
        2. 15.2.5.2 DMM Module Global Initialization
        3. 15.2.5.3 DMM Operational Modes Configuration
          1. 15.2.5.3.1 Different Operational Modes
          2. 15.2.5.3.2 Configuration Settings and LUT Refill
          3. 15.2.5.3.3 LISA Settings
          4. 15.2.5.3.4 Aliased Tiled View Orientation Settings and LUT Refill
          5. 15.2.5.3.5 Priority Settings
          6. 15.2.5.3.6 Error Handling
          7. 15.2.5.3.7 PAT Programming Model
            1. 15.2.5.3.7.1 PAT in Direct Translation Mode
            2. 15.2.5.3.7.2 PAT in Indirect Translation Mode
        4. 15.2.5.4 Addressing an Object in Tiled Mode
          1. 15.2.5.4.1 Frame-Buffer Addressing
          2. 15.2.5.4.2 TILER Page Mapping
        5. 15.2.5.5 Addressing an Object in Page Mode
        6. 15.2.5.6 Sharing Containers Between Different Modes
      6. 15.2.6 DMM Register Manual
        1. 15.2.6.1 DMM Instance Summary
        2. 15.2.6.2 DMM Registers
          1. 15.2.6.2.1 DMM Register Summary
          2. 15.2.6.2.2 DMM Register Description
    3. 15.3 EMIF Controller
      1. 15.3.1 EMIF Controller Overview
      2. 15.3.2 EMIF Module Environment
      3. 15.3.3 EMIF Module Integration
      4. 15.3.4 EMIF Functional Description
        1. 15.3.4.1  Block Diagram
          1. 15.3.4.1.1 Local Interface
          2. 15.3.4.1.2 FIFO Description
          3. 15.3.4.1.3 MPU Port Restrictions
          4. 15.3.4.1.4 Arbitration of Commands in the Command FIFO
        2. 15.3.4.2  Clock Management
          1. 15.3.4.2.1 EMIF_FICLK Overview
          2. 15.3.4.2.2 EMIF Dependency on MPU Clock Rate
        3. 15.3.4.3  Reset
        4. 15.3.4.4  System Power Management
          1. 15.3.4.4.1 Power-Down Mode
          2. 15.3.4.4.2 Self-Refresh Mode
        5. 15.3.4.5  Interrupt Requests
        6. 15.3.4.6  SDRAM Refresh Scheduling
        7. 15.3.4.7  SDRAM Initialization
          1. 15.3.4.7.1 DDR3/DDR3L SDRAM Initialization
        8. 15.3.4.8  DDR3/DDR3L Read-Write Leveling
          1. 15.3.4.8.1 Full Leveling
          2. 15.3.4.8.2 Software Leveling
        9. 15.3.4.9  EMIF Access Cycles
        10. 15.3.4.10 Turnaround Time
        11. 15.3.4.11 PHY DLL Calibration
        12. 15.3.4.12 SDRAM Address Mapping
          1. 15.3.4.12.1  Address Mapping for IBANK_POS = 0 and EBANK_POS = 0
          2. 15.3.4.12.2  Address Mapping for IBANK_POS = 1 and EBANK_POS = 0
          3. 15.3.4.12.3  Address Mapping for IBANK_POS = 2 and EBANK_POS = 0
          4. 15.3.4.12.4  Address Mapping for IBANK_POS = 3 and EBANK_POS = 0
          5. 15.3.4.12.5  Address Mapping for IBANK_POS = 0 and EBANK_POS = 1
          6. 15.3.4.12.6  Address Mapping for IBANK_POS = 1 and EBANK_POS = 1
          7. 15.3.4.12.7  Address Mapping for IBANK_POS = 2 and EBANK_POS = 1
          8. 15.3.4.12.8  1949
          9. 15.3.4.12.9  Address Mapping for IBANK_POS = 3 and EBANK_POS = 1
          10. 15.3.4.12.10 1951
        13. 15.3.4.13 DDR3/DDR3L Output Impedance Calibration
        14. 15.3.4.14 Error Correction And Detection Feature
        15. 15.3.4.15 Class of Service
        16. 15.3.4.16 Performance Counters
          1. 15.3.4.16.1 Performance Counters General Examples
        17. 15.3.4.17 Forcing CKE to tri-state
      5. 15.3.5 EMIF Programming Guide
        1. 15.3.5.1 EMIF Low-Level Programming Models
          1. 15.3.5.1.1 Global Initialization
            1. 15.3.5.1.1.1 EMIF Configuration Sequence
          2. 15.3.5.1.2 Operational Modes Configuration
            1. 15.3.5.1.2.1 EMIF Output Impedance Calibration Mode
            2. 15.3.5.1.2.2 EMIF SDRAM Self-Refresh
            3. 15.3.5.1.2.3 EMIF SDRAM Power-Down Mode
            4. 15.3.5.1.2.4 EMIF ECC Configuration
      6. 15.3.6 EMIF Register Manual
        1. 15.3.6.1 EMIF Instance Summary
        2. 15.3.6.2 EMIF Registers
          1. 15.3.6.2.1 EMIF Register Summary
          2. 15.3.6.2.2 EMIF Register Description
    4. 15.4 General-Purpose Memory Controller
      1. 15.4.1 GPMC Overview
      2. 15.4.2 GPMC Environment
        1. 15.4.2.1 GPMC Modes
        2. 15.4.2.2 GPMC Signals
      3. 15.4.3 GPMC Integration
      4. 15.4.4 GPMC Functional Description
        1. 15.4.4.1  GPMC Block Diagram
        2. 15.4.4.2  GPMC Clock Configuration
        3. 15.4.4.3  GPMC Software Reset
        4. 15.4.4.4  GPMC Power Management
        5. 15.4.4.5  GPMC Interrupt Requests
        6. 15.4.4.6  L3 Interconnect Interface
        7. 15.4.4.7  GPMC Address and Data Bus
          1. 15.4.4.7.1 GPMC I/O Configuration Setting
          2. 15.4.4.7.2 GPMC CS0 Default Configuration at Device Reset
        8. 15.4.4.8  Address Decoder and Chip-Select Configuration
          1. 15.4.4.8.1 Chip-Select Base Address and Region Size
          2. 15.4.4.8.2 Access Protocol
            1. 15.4.4.8.2.1 Supported Devices
            2. 15.4.4.8.2.2 Access Size Adaptation and Device Width
            3. 15.4.4.8.2.3 Address/Data-Multiplexing Interface
          3. 15.4.4.8.3 External Signals
            1. 15.4.4.8.3.1 Wait Pin Monitoring Control
              1. 15.4.4.8.3.1.1 Wait Monitoring During Asynchronous Read Access
              2. 15.4.4.8.3.1.2 Wait Monitoring During Asynchronous Write Access
              3. 15.4.4.8.3.1.3 Wait Monitoring During Synchronous Read Access
              4. 15.4.4.8.3.1.4 Wait Monitoring During Synchronous Write Access
              5. 15.4.4.8.3.1.5 Wait With NAND Device
              6. 15.4.4.8.3.1.6 Idle Cycle Control Between Successive Accesses
                1. 15.4.4.8.3.1.6.1 Bus Turnaround (BUSTURNAROUND)
                2. 15.4.4.8.3.1.6.2 Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
                3. 15.4.4.8.3.1.6.3 Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
              7. 15.4.4.8.3.1.7 Slow Device Support (TIMEPARAGRANULARITY Parameter)
            2. 15.4.4.8.3.2 Reset
            3. 15.4.4.8.3.3 Byte Enable (nBE1/nBE0)
          4. 15.4.4.8.4 Error Handling
        9. 15.4.4.9  Timing Setting
          1. 15.4.4.9.1  Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
          2. 15.4.4.9.2  nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
          3. 15.4.4.9.3  nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
          4. 15.4.4.9.4  nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
          5. 15.4.4.9.5  nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
          6. 15.4.4.9.6  GPMC_CLK
          7. 15.4.4.9.7  GPMC_CLK and Control Signals Setup and Hold
          8. 15.4.4.9.8  Access Time (RDACCESSTIME / WRACCESSTIME)
            1. 15.4.4.9.8.1 Access Time on Read Access
            2. 15.4.4.9.8.2 Access Time on Write Access
          9. 15.4.4.9.9  Page Burst Access Time (PAGEBURSTACCESSTIME)
            1. 15.4.4.9.9.1 Page Burst Access Time on Read Access
            2. 15.4.4.9.9.2 Page Burst Access Time on Write Access
          10. 15.4.4.9.10 Bus Keeping Support
        10. 15.4.4.10 NOR Access Description
          1. 15.4.4.10.1 Asynchronous Access Description
            1. 15.4.4.10.1.1 Access on Address/Data Multiplexed Devices
              1. 15.4.4.10.1.1.1 Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
              2. 15.4.4.10.1.1.2 Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
              3. 15.4.4.10.1.1.3 Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
            2. 15.4.4.10.1.2 Access on Address/Address/Data-Multiplexed Devices
              1. 15.4.4.10.1.2.1 Asynchronous Single Read Operation on an AAD-Multiplexed Device
              2. 15.4.4.10.1.2.2 Asynchronous Single-Write Operation on an AAD-Multiplexed Device
              3. 15.4.4.10.1.2.3 Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
          2. 15.4.4.10.2 Synchronous Access Description
            1. 15.4.4.10.2.1 Synchronous Single Read
            2. 15.4.4.10.2.2 Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
            3. 15.4.4.10.2.3 Synchronous Single Write
            4. 15.4.4.10.2.4 Synchronous Multiple (Burst) Write
          3. 15.4.4.10.3 Asynchronous and Synchronous Accesses in Nonmultiplexed Mode
            1. 15.4.4.10.3.1 Asynchronous Single-Read Operation on Nonmultiplexed Device
            2. 15.4.4.10.3.2 Asynchronous Single-Write Operation on Nonmultiplexed Device
            3. 15.4.4.10.3.3 Asynchronous Multiple (Page Mode) Read Operation on Nonmultiplexed Device
            4. 15.4.4.10.3.4 Synchronous Operations on a Nonmultiplexed Device
          4. 15.4.4.10.4 Page and Burst Support
          5. 15.4.4.10.5 System Burst vs External Device Burst Support
        11. 15.4.4.11 pSRAM Access Specificities
        12. 15.4.4.12 NAND Access Description
          1. 15.4.4.12.1 NAND Memory Device in Byte or 16-bit Word Stream Mode
            1. 15.4.4.12.1.1 Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
            2. 15.4.4.12.1.2 NAND Device Command and Address Phase Control
            3. 15.4.4.12.1.3 Command Latch Cycle
            4. 15.4.4.12.1.4 Address Latch Cycle
            5. 15.4.4.12.1.5 NAND Device Data Read and Write Phase Control in Stream Mode
            6. 15.4.4.12.1.6 NAND Device General Chip-Select Timing Control Requirement
            7. 15.4.4.12.1.7 Read and Write Access Size Adaptation
              1. 15.4.4.12.1.7.1 8-Bit-Wide NAND Device
              2. 15.4.4.12.1.7.2 16-Bit-Wide NAND Device
          2. 15.4.4.12.2 NAND Device-Ready Pin
            1. 15.4.4.12.2.1 Ready Pin Monitored by Software Polling
            2. 15.4.4.12.2.2 Ready Pin Monitored by Hardware Interrupt
          3. 15.4.4.12.3 ECC Calculator
            1. 15.4.4.12.3.1 Hamming Code
              1. 15.4.4.12.3.1.1 ECC Result Register and ECC Computation Accumulation Size
              2. 15.4.4.12.3.1.2 ECC Enabling
              3. 15.4.4.12.3.1.3 ECC Computation
              4. 15.4.4.12.3.1.4 ECC Comparison and Correction
              5. 15.4.4.12.3.1.5 ECC Calculation Based on 8-Bit Word
              6. 15.4.4.12.3.1.6 ECC Calculation Based on 16-Bit Word
            2. 15.4.4.12.3.2 BCH Code
              1. 15.4.4.12.3.2.1 Requirements
              2. 15.4.4.12.3.2.2 Memory Mapping of BCH Codeword
                1. 15.4.4.12.3.2.2.1 Memory Mapping of Data Message
                2. 15.4.4.12.3.2.2.2 Memory-Mapping of the ECC
                3. 15.4.4.12.3.2.2.3 Wrapping Modes
                  1. 4.4.12.3.2.2.3.1  Manual Mode (0x0)
                  2. 4.4.12.3.2.2.3.2  Mode 0x1
                  3. 4.4.12.3.2.2.3.3  Mode 0xA (10)
                  4. 4.4.12.3.2.2.3.4  Mode 0x2
                  5. 4.4.12.3.2.2.3.5  Mode 0x3
                  6. 4.4.12.3.2.2.3.6  Mode 0x7
                  7. 4.4.12.3.2.2.3.7  Mode 0x8
                  8. 4.4.12.3.2.2.3.8  Mode 0x4
                  9. 4.4.12.3.2.2.3.9  Mode 0x9
                  10. 4.4.12.3.2.2.3.10 Mode 0x5
                  11. 4.4.12.3.2.2.3.11 Mode 0xB (11)
                  12. 4.4.12.3.2.2.3.12 Mode 0x6
              3. 15.4.4.12.3.2.3 Supported NAND Page Mappings and ECC Schemes
                1. 15.4.4.12.3.2.3.1 Per-Sector Spare Mappings
                2. 15.4.4.12.3.2.3.2 Pooled Spare Mapping
                3. 15.4.4.12.3.2.3.3 Per-Sector Spare Mapping, with ECC Separated at the End of the Page
          4. 15.4.4.12.4 Prefetch and Write-Posting Engine
            1. 15.4.4.12.4.1 General Facts About the Engine Configuration
            2. 15.4.4.12.4.2 Prefetch Mode
            3. 15.4.4.12.4.3 FIFO Control in Prefetch Mode
            4. 15.4.4.12.4.4 Write-Posting Mode
            5. 15.4.4.12.4.5 FIFO Control in Write-Posting Mode
            6. 15.4.4.12.4.6 Optimizing NAND Access Using the Prefetch and Write-Posting Engine
            7. 15.4.4.12.4.7 Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
      5. 15.4.5 GPMC Basic Programming Model
        1. 15.4.5.1 GPMC High-Level Programming Model Overview
        2. 15.4.5.2 GPMC Initialization
        3. 15.4.5.3 GPMC Configuration in NOR Mode
        4. 15.4.5.4 GPMC Configuration in NAND Mode
        5. 15.4.5.5 Set Memory Access
        6. 15.4.5.6 GPMC Timing Parameters
          1. 15.4.5.6.1 GPMC Timing Parameters Formulas
            1. 15.4.5.6.1.1 NAND Flash Interface Timing Parameters Formulas
            2. 15.4.5.6.1.2 Synchronous NOR Flash Timing Parameters Formulas
            3. 15.4.5.6.1.3 Asynchronous NOR Flash Timing Parameters Formulas
      6. 15.4.6 GPMC Use Cases and Tips
        1. 15.4.6.1 How to Set GPMC Timing Parameters for Typical Accesses
          1. 15.4.6.1.1 External Memory Attached to the GPMC Module
          2. 15.4.6.1.2 Typical GPMC Setup
            1. 15.4.6.1.2.1 GPMC Configuration for Synchronous Burst Read Access
            2. 15.4.6.1.2.2 GPMC Configuration for Asynchronous Read Access
            3. 15.4.6.1.2.3 GPMC Configuration for Asynchronous Single Write Access
        2. 15.4.6.2 How to Choose a Suitable Memory to Use With the GPMC
          1. 15.4.6.2.1 Supported Memories or Devices
            1. 15.4.6.2.1.1 Memory Pin Multiplexing
            2. 15.4.6.2.1.2 NAND Interface Protocol
            3. 15.4.6.2.1.3 NOR Interface Protocol
            4. 15.4.6.2.1.4 Other Technologies
            5. 15.4.6.2.1.5 Supported Protocols
          2. 15.4.6.2.2 GPMC Features and Settings
      7. 15.4.7 GPMC Register Manual
        1. 15.4.7.1 GPMC Register Summary
        2. 15.4.7.2 GPMC Register Descriptions
    5. 15.5 Error Location Module
      1. 15.5.1 Error Location Module Overview
      2. 15.5.2 ELM Integration
      3. 15.5.3 ELM Functional Description
        1. 15.5.3.1 ELM Software Reset
        2. 15.5.3.2 ELM Power Management
        3. 15.5.3.3 ELM Interrupt Requests
        4. 15.5.3.4 Processing Initialization
        5. 15.5.3.5 Processing Sequence
        6. 15.5.3.6 Processing Completion
      4. 15.5.4 ELM Basic Programming Model
        1. 15.5.4.1 ELM Low-Level Programming Model
          1. 15.5.4.1.1 Processing Initialization
          2. 15.5.4.1.2 Read Results
          3. 15.5.4.1.3 2142
        2. 15.5.4.2 Use Case: ELM Used in Continuous Mode
        3. 15.5.4.3 Use Case: ELM Used in Page Mode
      5. 15.5.5 ELM Register Manual
        1. 15.5.5.1 ELM Instance Summary
        2. 15.5.5.2 ELM Registers
          1. 15.5.5.2.1 ELM Register Summary
          2. 15.5.5.2.2 ELM Register Description
    6. 15.6 On-Chip Memory (OCM) Subsystem
      1. 15.6.1 OCM Subsystem Overview
      2. 15.6.2 OCM Subsystem Integration
      3. 15.6.3 OCM Subsystem Functional Desctiption
        1. 15.6.3.1  Block Diagram
        2. 15.6.3.2  Resets
        3. 15.6.3.3  Clock Management
        4. 15.6.3.4  Interrupt Requests
        5. 15.6.3.5  OCM Subsystem Memory Regions
        6. 15.6.3.6  OCM Controller Modes Of Operation
        7. 15.6.3.7  ECC Associated FIFOs
        8. 15.6.3.8  ECC Counters And Corrected Bit Distribution Register
        9. 15.6.3.9  ECC Support
        10. 15.6.3.10 Circular Buffer (CBUF) Support
        11. 15.6.3.11 CBUF Mode Error Handling
          1. 15.6.3.11.1 VBUF Address Not Mapped to a CBUF Memory Space
          2. 15.6.3.11.2 VBUF Access Not Starting At The Base Address
          3. 15.6.3.11.3 Illegal Address Change Between Two Same Type Accesses
          4. 15.6.3.11.4 Illegal Frame SIze (Short Frame Detection)
          5. 15.6.3.11.5 CBUF Overflow
          6. 15.6.3.11.6 CBUF Underflow
        12. 15.6.3.12 Status Reporting
      4. 15.6.4 OCM Subsystem Register Manual
        1. 15.6.4.1 OCM Subsystem Instance Summary
        2. 15.6.4.2 OCM Subsystem Registers
          1. 15.6.4.2.1 OCM Subsystem Register Summary
          2. 15.6.4.2.2 OCM Subsystem Register Description
  18. 16DMA Controllers
    1. 16.1 System DMA
      1. 16.1.1 DMA_SYSTEM Module Overview
      2. 16.1.2 DMA_SYSTEM Controller Environment
      3. 16.1.3 DMA_SYSTEM Module Integration
        1. 16.1.3.1 DMA Requests to the DMA_SYSTEM Controller
        2. 16.1.3.2 Mapping of DMA Requests to DMA_CROSSBAR Inputs
      4. 16.1.4 DMA_SYSTEM Functional Description
        1. 16.1.4.1  DMA_SYSTEM Controller Power Management
        2. 16.1.4.2  DMA_SYSTEM Controller Interrupt Requests
          1. 16.1.4.2.1 Interrupt Generation
        3. 16.1.4.3  Logical Channel Transfer Overview
        4. 16.1.4.4  FIFO Queue Memory Pool
        5. 16.1.4.5  Addressing Modes
        6. 16.1.4.6  Packed Accesses
        7. 16.1.4.7  Burst Transactions
        8. 16.1.4.8  Endianism Conversion
        9. 16.1.4.9  Transfer Synchronization
          1. 16.1.4.9.1 Software Synchronization
          2. 16.1.4.9.2 Hardware Synchronization
        10. 16.1.4.10 Thread Budget Allocation
        11. 16.1.4.11 FIFO Budget Allocation
        12. 16.1.4.12 Chained Logical Channel Transfers
        13. 16.1.4.13 Reprogramming an Active Channel
        14. 16.1.4.14 Packet Synchronization
        15. 16.1.4.15 Graphics Acceleration Support
        16. 16.1.4.16 Supervisor Modes
        17. 16.1.4.17 Posted and Nonposted Writes
        18. 16.1.4.18 Disabling a Channel During Transfer
        19. 16.1.4.19 FIFO Draining Mechanism
        20. 16.1.4.20 Linked List
          1. 16.1.4.20.1 Overview
          2. 16.1.4.20.2 Link-List Transfer Profile
          3. 16.1.4.20.3 Descriptors
            1. 16.1.4.20.3.1 Type 1
            2. 16.1.4.20.3.2 Type 2
            3. 16.1.4.20.3.3 Type 3
          4. 16.1.4.20.4 Linked-List Control and Monitoring
            1. 16.1.4.20.4.1 Transfer Mode Setting
            2. 16.1.4.20.4.2 Starting a Linked List
            3. 16.1.4.20.4.3 Monitoring a Linked-List Progression
            4. 16.1.4.20.4.4 Interrupt During Linked-List Execution
            5. 16.1.4.20.4.5 Pause a Linked List
            6. 16.1.4.20.4.6 Stop a Linked List (Abort or Drain)
              1. 16.1.4.20.4.6.1 Drain
              2. 16.1.4.20.4.6.2 Abort
            7. 16.1.4.20.4.7 Status Bit Behavior
            8. 16.1.4.20.4.8 Linked-List Channel Linking
      5. 16.1.5 DMA_SYSTEM Basic Programming Model
        1. 16.1.5.1 Setup Configuration
        2. 16.1.5.2 Software-Triggered (Nonsynchronized) Transfer
        3. 16.1.5.3 Hardware-Synchronized Transfer
        4. 16.1.5.4 Synchronized Transfer Monitoring Using CDAC
        5. 16.1.5.5 Concurrent Software and Hardware Synchronization
        6. 16.1.5.6 Chained Transfer
        7. 16.1.5.7 90-Degree Clockwise Image Rotation
        8. 16.1.5.8 Graphic Operations
        9. 16.1.5.9 Linked-List Programming Guidelines
      6. 16.1.6 DMA_SYSTEM Register Manual
        1. 16.1.6.1 DMA_SYSTEM Instance Summary
        2. 16.1.6.2 DMA_SYSTEM Registers
          1. 16.1.6.2.1 DMA_SYSTEM Register Summary
          2. 16.1.6.2.2 DMA_SYSTEM Register Description
    2. 16.2 Enhanced DMA
      1. 16.2.1 EDMA Module Overview
        1. 16.2.1.1 EDMA Features
        2. 16.2.1.2 2243
        3. 16.2.1.3 EDMA Controllers Configuration
      2. 16.2.2 EDMA Controller Environment
      3. 16.2.3 EDMA Controller Integration
        1. 16.2.3.1 EDMA Requests to the EDMA Controller
      4. 16.2.4 EDMA Controller Functional Description
        1. 16.2.4.1  Block Diagram
          1. 16.2.4.1.1 Third-Party Channel Controller
          2. 16.2.4.1.2 Third-Party Transfer Controller
        2. 16.2.4.2  Types of EDMA controller Transfers
          1. 16.2.4.2.1 A-Synchronized Transfers
          2. 16.2.4.2.2 AB-Synchronized Transfers
        3. 16.2.4.3  Parameter RAM (PaRAM)
          1. 16.2.4.3.1 PaRAM
          2. 16.2.4.3.2 EDMA Channel PaRAM Set Entry Fields
            1. 16.2.4.3.2.1  Channel Options Parameter (OPT)
            2. 16.2.4.3.2.2  Channel Source Address (SRC)
            3. 16.2.4.3.2.3  Channel Destination Address (DST)
            4. 16.2.4.3.2.4  Count for 1st Dimension (ACNT)
            5. 16.2.4.3.2.5  Count for 2nd Dimension (BCNT)
            6. 16.2.4.3.2.6  Count for 3rd Dimension (CCNT)
            7. 16.2.4.3.2.7  BCNT Reload (BCNTRLD)
            8. 16.2.4.3.2.8  Source B Index (SBIDX)
            9. 16.2.4.3.2.9  Destination B Index (DBIDX)
            10. 16.2.4.3.2.10 Source C Index (SCIDX)
            11. 16.2.4.3.2.11 Destination C Index (DCIDX)
            12. 16.2.4.3.2.12 Link Address (LINK)
          3. 16.2.4.3.3 Null PaRAM Set
          4. 16.2.4.3.4 Dummy PaRAM Set
          5. 16.2.4.3.5 Dummy Versus Null Transfer Comparison
          6. 16.2.4.3.6 Parameter Set Updates
          7. 16.2.4.3.7 Linking Transfers
          8. 16.2.4.3.8 Constant Addressing Mode Transfers/Alignment Issues
          9. 16.2.4.3.9 Element Size
        4. 16.2.4.4  Initiating a DMA Transfer
          1. 16.2.4.4.1 DMA Channel
            1. 16.2.4.4.1.1 Event-Triggered Transfer Request
            2. 16.2.4.4.1.2 Manually-Triggered Transfer Request
            3. 16.2.4.4.1.3 Chain-Triggered Transfer Request
          2. 16.2.4.4.2 QDMA Channels
            1. 16.2.4.4.2.1 Auto-triggered and Link-Triggered Transfer Request
          3. 16.2.4.4.3 Comparison Between DMA and QDMA Channels
        5. 16.2.4.5  Completion of a DMA Transfer
          1. 16.2.4.5.1 Normal Completion
          2. 16.2.4.5.2 Early Completion
          3. 16.2.4.5.3 Dummy or Null Completion
        6. 16.2.4.6  Event, Channel, and PaRAM Mapping
          1. 16.2.4.6.1 DMA Channel to PaRAM Mapping
          2. 16.2.4.6.2 QDMA Channel to PaRAM Mapping
        7. 16.2.4.7  EDMA Channel Controller Regions
          1. 16.2.4.7.1 Region Overview
          2. 16.2.4.7.2 Channel Controller Regions
            1. 16.2.4.7.2.1 Resource Pool Division Across Two Regions
          3. 16.2.4.7.3 Region Interrupts
        8. 16.2.4.8  Chaining EDMA Channels
        9. 16.2.4.9  EDMA Interrupts
          1. 16.2.4.9.1 Transfer Completion Interrupts
            1. 16.2.4.9.1.1 Enabling Transfer Completion Interrupts
            2. 16.2.4.9.1.2 Clearing Transfer Completion Interrupts
          2. 16.2.4.9.2 EDMA Interrupt Servicing
          3. 16.2.4.9.3 Interrupt Servicing
          4. 16.2.4.9.4 2304
          5. 16.2.4.9.5 Interrupt Servicing
          6. 16.2.4.9.6 Interrupt Evaluation Operations
          7. 16.2.4.9.7 Error Interrupts
          8. 16.2.4.9.8 2308
        10. 16.2.4.10 Memory Protection
          1. 16.2.4.10.1 Active Memory Protection
          2. 16.2.4.10.2 Proxy Memory Protection
        11. 16.2.4.11 Event Queue(s)
          1. 16.2.4.11.1 DMA/QDMA Channel to Event Queue Mapping
          2. 16.2.4.11.2 Queue RAM Debug Visibility
          3. 16.2.4.11.3 Queue Resource Tracking
          4. 16.2.4.11.4 Performance Considerations
        12. 16.2.4.12 EDMA Transfer Controller (EDMA_TPTC)
          1. 16.2.4.12.1 Architecture Details
            1. 16.2.4.12.1.1 Command Fragmentation
            2. 16.2.4.12.1.2 TR Pipelining
            3. 16.2.4.12.1.3 Command Fragmentation (DBS = 64)
            4. 16.2.4.12.1.4 Performance Tuning
          2. 16.2.4.12.2 Memory Protection
          3. 16.2.4.12.3 Error Generation
          4. 16.2.4.12.4 Debug Features
            1. 16.2.4.12.4.1 Destination FIFO Register Pointer
          5. 16.2.4.12.5 EDMA_TPTC Configuration
        13. 16.2.4.13 Event Dataflow
        14. 16.2.4.14 EDMA controller Prioritization
          1. 16.2.4.14.1 Channel Priority
          2. 16.2.4.14.2 Trigger Source Priority
          3. 16.2.4.14.3 Dequeue Priority
        15. 16.2.4.15 EDMA Power, Reset and Clock Management
          1. 16.2.4.15.1 Clock and Power Management
          2. 16.2.4.15.2 Reset Considerations
        16. 16.2.4.16 Emulation Considerations
      5. 16.2.5 EDMA Transfer Examples
        1. 16.2.5.1 Block Move Example
        2. 16.2.5.2 Subframe Extraction Example
        3. 16.2.5.3 Data Sorting Example
        4. 16.2.5.4 Peripheral Servicing Example
          1. 16.2.5.4.1 Non-bursting Peripherals
          2. 16.2.5.4.2 Bursting Peripherals
          3. 16.2.5.4.3 Continuous Operation
            1. 16.2.5.4.3.1 Receive Channel
            2. 16.2.5.4.3.2 Transmit Channel
            3. 16.2.5.4.3.3 2347
          4. 16.2.5.4.4 Ping-Pong Buffering
            1. 16.2.5.4.4.1 Synchronization with the CPU
          5. 16.2.5.4.5 Transfer Chaining Examples
            1. 16.2.5.4.5.1 Servicing Input/Output FIFOs with a Single Event
            2. 16.2.5.4.5.2 Breaking Up Large Transfers with Intermediate Chaining
        5. 16.2.5.5 Setting Up an EDMA Transfer
          1. 16.2.5.5.1 2354
      6. 16.2.6 EDMA Debug Checklist and Programming Tips
        1. 16.2.6.1 EDMA Debug Checklist
        2. 16.2.6.2 EDMA Programming Tips
      7. 16.2.7 EDMA Register Manual
        1. 16.2.7.1 EDMA Instance Summary
        2. 16.2.7.2 EDMA Registers
          1. 16.2.7.2.1 EDMA Register Summary
          2. 16.2.7.2.2 EDMA Register Description
            1. 16.2.7.2.2.1 EDMA_TPCC Register Description
            2. 16.2.7.2.2.2 EDMA_TPTC0 and EDMA_TPTC1 Register Description
  19. 17Interrupt Controllers
    1. 17.1 Interrupt Controllers Overview
    2. 17.2 Interrupt Controllers Environment
    3. 17.3 Interrupt Controllers Integration
      1. 17.3.1 Interrupt Requests to MPU_INTC
      2. 17.3.2 Interrupt Requests to DSP1_INTC
      3. 17.3.3 Interrupt Requests to IPU1_Cx_INTC
      4. 17.3.4 Interrupt Requests to IPU2_Cx_INTC
      5. 17.3.5 Interrupt Requests to PRUSS1_INTC
      6. 17.3.6 Interrupt Requests to PRUSS2_INTC
      7. 17.3.7 Mapping of Device Interrupts to IRQ_CROSSBAR Inputs
    4. 17.4 Interrupt Controllers Functional Description
  20. 18Control Module
    1. 18.1 Control Module Overview
    2. 18.2 Control Module Environment
    3. 18.3 Control Module Integration
    4. 18.4 Control Module Functional Description
      1. 18.4.1 Control Module Clock Configuration
      2. 18.4.2 Control Module Resets
      3. 18.4.3 Control Module Power Management
        1. 18.4.3.1 Power Management Protocols
      4. 18.4.4 Hardware Requests
      5. 18.4.5 Control Module Initialization
      6. 18.4.6 Functional Description Of The Various Register Types In CTRL_MODULE_CORE Submodule
        1. 18.4.6.1  Pad Configuration
          1. 18.4.6.1.1 Pad Configuration Registers
            1. 18.4.6.1.1.1 Permanent PU/PD disabling (SR 2.x only)
          2. 18.4.6.1.2 Pull Selection
          3. 18.4.6.1.3 Pad multiplexing
          4. 18.4.6.1.4 IOSETs
          5. 18.4.6.1.5 Virtual IO Timing Modes
          6. 18.4.6.1.6 Manual IO Timing Modes
          7. 18.4.6.1.7 Isolation Requirements
          8. 18.4.6.1.8 IO Delay Recalibration
        2. 18.4.6.2  Thermal Management Related Registers
          1. 18.4.6.2.1 Temperature Sensors Control Registers
          2. 18.4.6.2.2 Registers For The Thermal Alert Comparators
          3. 18.4.6.2.3 Thermal Shutdown Comparators
          4. 18.4.6.2.4 Temperature Timestamp Registers
          5. 18.4.6.2.5 Other Thermal Management Related Registers
          6. 18.4.6.2.6 Summary Of The Thermal Management Related Registers
          7. 18.4.6.2.7 ADC Values Versus Temperature
        3. 18.4.6.3  PBIAS Cell And MMC1 I/O Cells Control Registers
        4. 18.4.6.4  IRQ_CROSSBAR Module Functional Description
        5. 18.4.6.5  DMA_CROSSBAR Module Functional Description
        6. 18.4.6.6  SDRAM Initiator Priority Registers
        7. 18.4.6.7  L3_MAIN Initiator Priority Registers
        8. 18.4.6.8  Memory Region Lock Registers
        9. 18.4.6.9  NMI Mapping To Respective Cores
        10. 18.4.6.10 Software Controls for the DDR3 I/O Cells
        11. 18.4.6.11 Reference Voltage for the Device DDR3 Receivers
        12. 18.4.6.12 AVS Class 0 Associated Registers
        13. 18.4.6.13 ABB Associated Registers
        14. 18.4.6.14 Registers For Other Miscellaneous Functions
          1. 18.4.6.14.1 System Boot Status Settings
          2. 18.4.6.14.2 Force MPU Write Nonposted Transactions
          3. 18.4.6.14.3 Firewall Error Status Registers
          4. 18.4.6.14.4 Settings Related To Different Peripheral Modules
      7. 18.4.7 Functional Description Of The Various Register Types In CTRL_MODULE_WKUP Submodule
        1. 18.4.7.1 Registers For Basic EMIF configuration
    5. 18.5 Control Module Register Manual
    6. 18.6 IODELAYCONFIG Module Integration
    7. 18.7 IODELAYCONFIG Module Register Manual
  21. 19Mailbox
    1. 19.1 Mailbox Overview
    2. 19.2 Mailbox Integration
      1. 19.2.1 System MAILBOX Integration
      2. 19.2.2 IVA Mailbox Integration
    3. 19.3 Mailbox Functional Description
      1. 19.3.1 Mailbox Block Diagram
        1. 19.3.1.1 2435
      2. 19.3.2 Mailbox Software Reset
      3. 19.3.3 Mailbox Power Management
      4. 19.3.4 Mailbox Interrupt Requests
      5. 19.3.5 Mailbox Assignment
        1. 19.3.5.1 Description
      6. 19.3.6 Sending and Receiving Messages
        1. 19.3.6.1 Description
      7. 19.3.7 16-Bit Register Access
        1. 19.3.7.1 Description
      8. 19.3.8 Example of Communication
    4. 19.4 Mailbox Programming Guide
      1. 19.4.1 Mailbox Low-level Programming Models
        1. 19.4.1.1 Global Initialization
          1. 19.4.1.1.1 Surrounding Modules Global Initialization
          2. 19.4.1.1.2 Mailbox Global Initialization
            1. 19.4.1.1.2.1 Main Sequence - Mailbox Global Initialization
        2. 19.4.1.2 Mailbox Operational Modes Configuration
          1. 19.4.1.2.1 Mailbox Processing modes
            1. 19.4.1.2.1.1 Main Sequence - Sending a Message (Polling Method)
            2. 19.4.1.2.1.2 Main Sequence - Sending a Message (Interrupt Method)
            3. 19.4.1.2.1.3 Main Sequence - Receiving a Message (Polling Method)
            4. 19.4.1.2.1.4 Main Sequence - Receiving a Message (Interrupt Method)
        3. 19.4.1.3 Mailbox Events Servicing
          1. 19.4.1.3.1 Events Servicing in Sending Mode
          2. 19.4.1.3.2 Events Servicing in Receiving Mode
    5. 19.5 Mailbox Register Manual
      1. 19.5.1 Mailbox Instance Summary
      2. 19.5.2 Mailbox Registers
        1. 19.5.2.1 Mailbox Register Summary
        2. 19.5.2.2 Mailbox Register Description
  22. 20Memory Management Units
    1. 20.1 MMU Overview
    2. 20.2 MMU Integration
    3. 20.3 MMU Functional Description
      1. 20.3.1 MMU Block Diagram
        1. 20.3.1.1 MMU Address Translation Process
        2. 20.3.1.2 Translation Tables
          1. 20.3.1.2.1 Translation Table Hierarchy
          2. 20.3.1.2.2 First-Level Translation Table
            1. 20.3.1.2.2.1 First-Level Descriptor Format
            2. 20.3.1.2.2.2 First-Level Page Descriptor Format
            3. 20.3.1.2.2.3 First-Level Section Descriptor Format
            4. 20.3.1.2.2.4 Section Translation Summary
            5. 20.3.1.2.2.5 Supersection Translation Summary
          3. 20.3.1.2.3 Two-Level Translation
            1. 20.3.1.2.3.1 Second-Level Descriptor Format
            2. 20.3.1.2.3.2 Small Page Translation Summary
            3. 20.3.1.2.3.3 Large Page Translation Summary
        3. 20.3.1.3 Translation Lookaside Buffer
          1. 20.3.1.3.1 TLB Entry Format
        4. 20.3.1.4 No Translation (Bypass) Regions
      2. 20.3.2 MMU Software Reset
      3. 20.3.3 MMU Power Management
      4. 20.3.4 MMU Interrupt Requests
      5. 20.3.5 MMU Error Handling
    4. 20.4 MMU Low-level Programming Models
      1. 20.4.1 Global Initialization
        1. 20.4.1.1 Surrounding Modules Global Initialization
        2. 20.4.1.2 MMU Global Initialization
          1. 20.4.1.2.1 Main Sequence - MMU Global Initialization
          2. 20.4.1.2.2 Subsequence - Configure a TLB entry
        3. 20.4.1.3 Operational Modes Configuration
          1. 20.4.1.3.1 Main Sequence - Writing TLB Entries Statically
          2. 20.4.1.3.2 Main Sequence - Protecting TLB Entries
          3. 20.4.1.3.3 Main Sequence - Deleting TLB Entries
          4. 20.4.1.3.4 Main Sequence - Read TLB Entries
    5. 20.5 MMU Register Manual
      1. 20.5.1 MMU Instance Summary
      2. 20.5.2 MMU Registers
        1. 20.5.2.1 MMU Register Summary
        2. 20.5.2.2 MMU Register Description
  23. 21Spinlock
    1. 21.1 Spinlock Overview
    2. 21.2 Spinlock Integration
    3. 21.3 Spinlock Functional Description
      1. 21.3.1 Spinlock Software Reset
      2. 21.3.2 Spinlock Power Management
      3. 21.3.3 About Spinlocks
      4. 21.3.4 Spinlock Functional Operation
    4. 21.4 Spinlock Programming Guide
      1. 21.4.1 Spinlock Low-level Programming Models
        1. 21.4.1.1 Surrounding Modules Global Initialization
        2. 21.4.1.2 Basic Spinlock Operations
          1. 21.4.1.2.1 Spinlocks Clearing After a System Bug Recovery
          2. 21.4.1.2.2 Take and Release Spinlock
    5. 21.5 Spinlock Register Manual
      1. 21.5.1 Spinlock Instance Summary
      2. 21.5.2 Spinlock Registers
        1. 21.5.2.1 Spinlock Register Summary
        2. 21.5.2.2 Spinlock Register Description
  24. 22Timers
    1. 22.1 Timers Overview
    2. 22.2 General-Purpose Timers
      1. 22.2.1 General-Purpose Timers Overview
        1. 22.2.1.1 GP Timer Features
      2. 22.2.2 GP Timer Environment
        1. 22.2.2.1 GP Timer External System Interface
      3. 22.2.3 GP Timer Integration
      4. 22.2.4 GP Timer Functional Description
        1. 22.2.4.1  GP Timer Block Diagram
        2. 22.2.4.2  TIMER1, TIMER2 and TIMER10 Power Management
          1. 22.2.4.2.1 Wake-Up Capability
        3. 22.2.4.3  Power Management of Other GP Timers
          1. 22.2.4.3.1 Wake-Up Capability
        4. 22.2.4.4  Software Reset
        5. 22.2.4.5  GP Timer Interrupts
        6. 22.2.4.6  Timer Mode Functionality
          1. 22.2.4.6.1 1-ms Tick Generation (Only TIMER1, TIMER2 and TIMER10)
        7. 22.2.4.7  Capture Mode Functionality
        8. 22.2.4.8  Compare Mode Functionality
        9. 22.2.4.9  Prescaler Functionality
        10. 22.2.4.10 Pulse-Width Modulation
        11. 22.2.4.11 Timer Counting Rate
        12. 22.2.4.12 Timer Under Emulation
        13. 22.2.4.13 Accessing GP Timer Registers
          1. 22.2.4.13.1 Writing to Timer Registers
            1. 22.2.4.13.1.1 Write Posting Synchronization Mode
            2. 22.2.4.13.1.2 Write Nonposting Synchronization Mode
          2. 22.2.4.13.2 Reading From Timer Counter Registers
            1. 22.2.4.13.2.1 Read Posted
            2. 22.2.4.13.2.2 Read Non-Posted
        14. 22.2.4.14 Posted Mode Selection
      5. 22.2.5 GP Timer Low-Level Programming Models
        1. 22.2.5.1 Global Initialization
          1. 22.2.5.1.1 Global Initialization of Surrounding Modules
          2. 22.2.5.1.2 GP Timer Module Global Initialization
            1. 22.2.5.1.2.1 Main Sequence – GP Timer Module Global Initialization
        2. 22.2.5.2 Operational Mode Configuration
          1. 22.2.5.2.1 GP Timer Mode
            1. 22.2.5.2.1.1 Main Sequence – GP Timer Mode Configuration
          2. 22.2.5.2.2 GP Timer Compare Mode
            1. 22.2.5.2.2.1 Main Sequence – GP Timer Compare Mode Configuration
          3. 22.2.5.2.3 GP Timer Capture Mode
            1. 22.2.5.2.3.1 Main Sequence – GP Timer Capture Mode Configuration
            2. 22.2.5.2.3.2 Subsequence – Initialize Capture Mode
            3. 22.2.5.2.3.3 Subsequence – Detect Event
          4. 22.2.5.2.4 GP Timer PWM Mode
            1. 22.2.5.2.4.1 Main Sequence – GP Timer PWM Mode Configuration
      6. 22.2.6 GP Timer Register Manual
        1. 22.2.6.1 GP Timer Instance Summary
        2. 22.2.6.2 GP Timer Registers
          1. 22.2.6.2.1 GP Timer Register Summary
          2. 22.2.6.2.2 GP Timer Register Description
          3. 22.2.6.2.3 TIMER1, TIMER2, and TIMER10 Register Description
    3. 22.3 32-kHz Synchronized Timer (COUNTER_32K)
      1. 22.3.1 32-kHz Synchronized Timer Overview
        1. 22.3.1.1 32-kHz Synchronized Timer Features
      2. 22.3.2 32-kHz Synchronized Timer Integration
      3. 22.3.3 32-kHz Synchronized Timer Functional Description
        1. 22.3.3.1 Reading the 32-kHz Synchronized Timer
      4. 22.3.4 COUNTER_32K Timer Register Manual
        1. 22.3.4.1 COUNTER_32K Timer Register Mapping Summary
        2. 22.3.4.2 COUNTER_32K Timer Register Description
    4. 22.4 Watchdog Timer
      1. 22.4.1 Watchdog Timer Overview
        1. 22.4.1.1 Watchdog Timer Features
      2. 22.4.2 Watchdog Timer Integration
      3. 22.4.3 Watchdog Timer Functional Description
        1. 22.4.3.1  Power Management
          1. 22.4.3.1.1 Wake-Up Capability
        2. 22.4.3.2  Interrupts
        3. 22.4.3.3  General Watchdog Timer Operation
        4. 22.4.3.4  Reset Context
        5. 22.4.3.5  Overflow/Reset Generation
        6. 22.4.3.6  Prescaler Value/Timer Reset Frequency
        7. 22.4.3.7  Triggering a Timer Reload
        8. 22.4.3.8  Start/Stop Sequence for Watchdog Timer (Using the WSPR Register)
        9. 22.4.3.9  Modifying Timer Count/Load Values and Prescaler Setting
        10. 22.4.3.10 Watchdog Counter Register Access Restriction (WCRR)
        11. 22.4.3.11 Watchdog Timer Interrupt Generation
        12. 22.4.3.12 Watchdog Timer Under Emulation
        13. 22.4.3.13 Accessing Watchdog Timer Registers
      4. 22.4.4 Watchdog Timer Low-Level Programming Model
        1. 22.4.4.1 Global Initialization
          1. 22.4.4.1.1 Surrounding Modules Global Initialization
          2. 22.4.4.1.2 Watchdog Timer Module Global Initialization
            1. 22.4.4.1.2.1 Main Sequence – Watchdog Timer Module Global Initialization
        2. 22.4.4.2 Operational Mode Configuration
          1. 22.4.4.2.1 Watchdog Timer Basic Configuration
            1. 22.4.4.2.1.1 Main Sequence – Watchdog Timer Basic Configuration
            2. 22.4.4.2.1.2 Subsequence – Disable the Watchdog Timer
            3. 22.4.4.2.1.3 Subsequence – Enable the Watchdog Timer
      5. 22.4.5 Watchdog Timer Register Manual
        1. 22.4.5.1 Watchdog Timer Instance Summary
        2. 22.4.5.2 Watchdog Timer Registers
          1. 22.4.5.2.1 Watchdog Timer Register Summary
          2. 22.4.5.2.2 2622
          3. 22.4.5.2.3 Watchdog Timer Register Description
  25. 23Real-Time Clock (RTC)
    1. 23.1 RTC Overview
      1. 23.1.1 RTC Features
    2. 23.2 RTC Environment
      1. 23.2.1 RTC External Interface
    3. 23.3 RTC Integration
    4. 23.4 RTC Functional Description
      1. 23.4.1 Clock Source
      2. 23.4.2 Interrupt Support
        1. 23.4.2.1 CPU Interrupts
        2. 23.4.2.2 Interrupt Description
          1. 23.4.2.2.1 Timer Interrupt (timer_intr)
          2. 23.4.2.2.2 Alarm Interrupt (alarm_intr)
      3. 23.4.3 RTC Programming/Usage Guide
        1. 23.4.3.1 Time/Calendar Data Format
        2. 23.4.3.2 Register Access
        3. 23.4.3.3 Register Spurious Write Protection
        4. 23.4.3.4 Reading the Timer/Calendar (TC) Registers
          1. 23.4.3.4.1 Rounding Seconds
        5. 23.4.3.5 Modifying the TC Registers
          1. 23.4.3.5.1 General Registers
        6. 23.4.3.6 Crystal Compensation
      4. 23.4.4 Scratch Registers
      5. 23.4.5 Debouncing
      6. 23.4.6 Power Management
        1. 23.4.6.1 Device-Level Power Management
        2. 23.4.6.2 Subsystem-Level Power Management — PMIC Mode
    5. 23.5 RTC Low-Level Programming Guide
      1. 23.5.1 Global Initialization
        1. 23.5.1.1 Surrounding Modules Global Initialization
        2. 23.5.1.2 RTC Module Global Initialization
          1. 23.5.1.2.1 Main Sequence – RTC Module Global Initialization
    6. 23.6 RTC Register Manual
      1. 23.6.1 RTC Instance Summary
      2. 23.6.2 RTC_SS Registers
        1. 23.6.2.1 RTC_SS Register Summary
        2. 23.6.2.2 RTC_SS Register Description
  26. 24Serial Communication Interfaces
    1. 24.1  Multimaster High-Speed I2C Controller
      1. 24.1.1 HS I2C Overview
      2. 24.1.2 HS I2C Environment
        1. 24.1.2.1 HS I2C Typical Application
          1. 24.1.2.1.1 HS I2C Pins for Typical Connections in I2C Mode
          2. 24.1.2.1.2 HS I2C Interface Typical Connections
          3. 24.1.2.1.3 2668
        2. 24.1.2.2 HS I2C Typical Connection Protocol and Data Format
          1. 24.1.2.2.1  HS I2C Serial Data Format
          2. 24.1.2.2.2  HS I2C Data Validity
          3. 24.1.2.2.3  HS I2C Start and Stop Conditions
          4. 24.1.2.2.4  HS I2C Addressing
            1. 24.1.2.2.4.1 Data Transfer Formats in F/S Mode
            2. 24.1.2.2.4.2 Data Transfer Format in HS Mode
          5. 24.1.2.2.5  HS I2C Master Transmitter
          6. 24.1.2.2.6  HS I2C Master Receiver
          7. 24.1.2.2.7  HS I2C Slave Transmitter
          8. 24.1.2.2.8  HS I2C Slave Receiver
          9. 24.1.2.2.9  HS I2C Bus Arbitration
          10. 24.1.2.2.10 HS I2C Clock Generation and Synchronization
      3. 24.1.3 HS I2C Integration
      4. 24.1.4 HS I2C Functional Description
        1. 24.1.4.1  HS I2C Block Diagram
        2. 24.1.4.2  HS I2C Clocks
          1. 24.1.4.2.1 HS I2C Clocking
          2. 24.1.4.2.2 HS I2C Automatic Blocking of the I2C Clock Feature
        3. 24.1.4.3  HS I2C Software Reset
        4. 24.1.4.4  HS I2C Power Management
        5. 24.1.4.5  HS I2C Interrupt Requests
        6. 24.1.4.6  HS I2C DMA Requests
        7. 24.1.4.7  HS I2C Programmable Multislave Channel Feature
        8. 24.1.4.8  HS I2C FIFO Management
          1. 24.1.4.8.1 HS I2C FIFO Interrupt Mode
          2. 24.1.4.8.2 HS I2C FIFO Polling Mode
          3. 24.1.4.8.3 HS I2C FIFO DMA Mode
          4. 24.1.4.8.4 HS I2C Draining Feature
        9. 24.1.4.9  HS I2C Noise Filter
        10. 24.1.4.10 HS I2C System Test Mode
      5. 24.1.5 HS I2C Programming Guide
        1. 24.1.5.1 HS I2C Low-Level Programming Models
          1. 24.1.5.1.1 HS I2C Programming Model
            1. 24.1.5.1.1.1 Main Program
              1. 24.1.5.1.1.1.1 Configure the Module Before Enabling the I2C Controller
              2. 24.1.5.1.1.1.2 Initialize the I2C Controller
              3. 24.1.5.1.1.1.3 Configure Slave Address and the Data Control Register
              4. 24.1.5.1.1.1.4 Initiate a Transfer
              5. 24.1.5.1.1.1.5 Receive Data
              6. 24.1.5.1.1.1.6 Transmit Data
            2. 24.1.5.1.1.2 Interrupt Subroutine Sequence
            3. 24.1.5.1.1.3 Programming Flow-Diagrams
      6. 24.1.6 HS I2C Register Manual
        1. 24.1.6.1 HS I2C Instance Summary
        2. 24.1.6.2 HS I2C Registers
          1. 24.1.6.2.1 HS I2C Register Summary
          2. 24.1.6.2.2 HS I2C Register Description
    2. 24.2  HDQ/1-Wire
      1. 24.2.1 HDQ1W Overview
      2. 24.2.2 HDQ1W Environment
        1. 24.2.2.1 HDQ1W Functional Modes
        2. 24.2.2.2 HDQ and 1-Wire (SDQ) Protocols
          1. 24.2.2.2.1 HDQ Protocol Initialization (Default)
          2. 24.2.2.2.2 1-Wire (SDQ) Protocol Initialization
          3. 24.2.2.2.3 Communication Sequence (HDQ and 1-Wire Protocols)
      3. 24.2.3 HDQ1W Integration
      4. 24.2.4 HDQ1W Functional Description
        1. 24.2.4.1 HDQ1W Block Diagram
        2. 24.2.4.2 HDQ1W Clocking Configuration
          1. 24.2.4.2.1 HDQ1W Clocks
        3. 24.2.4.3 HDQ1W Hardware and Software Reset
        4. 24.2.4.4 HDQ1W Power Management
          1. 24.2.4.4.1 Auto-Idle Mode
          2. 24.2.4.4.2 Power-Down Mode
          3. 24.2.4.4.3 2734
        5. 24.2.4.5 HDQ Interrupt Requests
        6. 24.2.4.6 HDQ Mode (Default)
          1. 24.2.4.6.1 HDQ Mode Features
          2. 24.2.4.6.2 Description
          3. 24.2.4.6.3 Single-Bit Mode
          4. 24.2.4.6.4 Interrupt Conditions
        7. 24.2.4.7 1-Wire Mode
          1. 24.2.4.7.1 1-Wire Mode Features
          2. 24.2.4.7.2 Description
          3. 24.2.4.7.3 1-Wire Single-Bit Mode Operation
          4. 24.2.4.7.4 Interrupt Conditions
          5. 24.2.4.7.5 Status Flags
        8. 24.2.4.8 BITFSM Delay
      5. 24.2.5 HDQ1W Low-Level Programming Model
        1. 24.2.5.1 Global Initialization
          1. 24.2.5.1.1 Surrounding Modules Global Initialization
          2. 24.2.5.1.2 HDQ1W Module Global Initialization
        2. 24.2.5.2 HDQ Operational Modes Configuration
          1. 24.2.5.2.1 Main Sequence - HDQ Write Operation Mode
          2. 24.2.5.2.2 Main Sequence - HDQ Read Operation Mode
            1. 24.2.5.2.2.1 Sub-sequence - Initialize HDQ Slave
        3. 24.2.5.3 1-Wire Operational Modes Configuration
          1. 24.2.5.3.1 Main Sequence - 1-Wire Write Operation Mode
          2. 24.2.5.3.2 Main Sequence - 1-Wire Read Operation Mode
          3. 24.2.5.3.3 Sub-sequence - Initialize 1-Wire Slave
      6. 24.2.6 HDQ1W Register Manual
        1. 24.2.6.1 HDQ1W Instance Summary
        2. 24.2.6.2 HDQ1W Registers
          1. 24.2.6.2.1 HDQ1W Register Summary
          2. 24.2.6.2.2 HDQ1W Register Description
    3. 24.3  UART/IrDA/CIR
      1. 24.3.1 UART/IrDA/CIR Overview
        1. 24.3.1.1 UART Features
        2. 24.3.1.2 IrDA Features
        3. 24.3.1.3 CIR Features
      2. 24.3.2 UART/IrDA/CIR Environment
        1. 24.3.2.1 UART Interface
          1. 24.3.2.1.1 System Using UART Communication With Hardware Handshake
          2. 24.3.2.1.2 UART Interface Description
          3. 24.3.2.1.3 UART Protocol and Data Format
        2. 24.3.2.2 IrDA Functional Interfaces
          1. 24.3.2.2.1 System Using IrDA Communication Protocol
          2. 24.3.2.2.2 IrDA Interface Description
          3. 24.3.2.2.3 IrDA Protocol and Data Format
            1. 24.3.2.2.3.1 SIR Mode
              1. 24.3.2.2.3.1.1 Frame Format
              2. 24.3.2.2.3.1.2 Asynchronous Transparency
              3. 24.3.2.2.3.1.3 Abort Sequence
              4. 24.3.2.2.3.1.4 Pulse Shaping
              5. 24.3.2.2.3.1.5 Encoder
              6. 24.3.2.2.3.1.6 Decoder
              7. 24.3.2.2.3.1.7 IR Address Checking
            2. 24.3.2.2.3.2 SIR Free-Format Mode
            3. 24.3.2.2.3.3 MIR Mode
              1. 24.3.2.2.3.3.1 MIR Encoder/Decoder
              2. 24.3.2.2.3.3.2 SIP Generation
            4. 24.3.2.2.3.4 FIR Mode
        3. 24.3.2.3 CIR Functional Interfaces
          1. 24.3.2.3.1 System Using CIR Communication Protocol With Remote Control
          2. 24.3.2.3.2 CIR Interface Description
          3. 24.3.2.3.3 CIR Protocol and Data Format
            1. 24.3.2.3.3.1 Carrier Modulation
            2. 24.3.2.3.3.2 Pulse Duty Cycle
            3. 24.3.2.3.3.3 Consumer IR Encoding/Decoding
      3. 24.3.3 UART/IrDA/CIR Integration
        1. 24.3.3.1 2800
      4. 24.3.4 UART/IrDA/CIR Functional Description
        1. 24.3.4.1 Block Diagram
        2. 24.3.4.2 Clock Configuration
        3. 24.3.4.3 Software Reset
        4. 24.3.4.4 Power Management
          1. 24.3.4.4.1 UART Mode Power Management
            1. 24.3.4.4.1.1 Module Power Saving
            2. 24.3.4.4.1.2 System Power Saving
          2. 24.3.4.4.2 IrDA Mode Power Management (UART3 Only)
            1. 24.3.4.4.2.1 Module Power Saving
            2. 24.3.4.4.2.2 System Power Saving
          3. 24.3.4.4.3 CIR Mode Power Management (UART3 Only)
            1. 24.3.4.4.3.1 Module Power Saving
            2. 24.3.4.4.3.2 System Power Saving
          4. 24.3.4.4.4 Local Power Management
        5. 24.3.4.5 Interrupt Requests
          1. 24.3.4.5.1 UART Mode Interrupt Management
            1. 24.3.4.5.1.1 UART Interrupts
            2. 24.3.4.5.1.2 Wake-Up Interrupt
          2. 24.3.4.5.2 IrDA Mode Interrupt Management
            1. 24.3.4.5.2.1 IrDA Interrupts
            2. 24.3.4.5.2.2 Wake-Up Interrupts
          3. 24.3.4.5.3 CIR Mode Interrupt Management
            1. 24.3.4.5.3.1 CIR Interrupts
            2. 24.3.4.5.3.2 Wake-Up Interrupts
        6. 24.3.4.6 FIFO Management
          1. 24.3.4.6.1 FIFO Trigger
            1. 24.3.4.6.1.1 Transmit FIFO Trigger
            2. 24.3.4.6.1.2 Receive FIFO Trigger
          2. 24.3.4.6.2 FIFO Interrupt Mode
          3. 24.3.4.6.3 FIFO Polled Mode Operation
          4. 24.3.4.6.4 FIFO DMA Mode Operation
            1. 24.3.4.6.4.1 DMA sequence to disable TX DMA
            2. 24.3.4.6.4.2 DMA Transfers (DMA Mode 1, 2, or 3)
            3. 24.3.4.6.4.3 DMA Transmission
            4. 24.3.4.6.4.4 DMA Reception
        7. 24.3.4.7 Mode Selection
          1. 24.3.4.7.1 Register Access Modes
            1. 24.3.4.7.1.1 Operational Mode and Configuration Modes
            2. 24.3.4.7.1.2 Register Access Submode
            3. 24.3.4.7.1.3 Registers Available for the Register Access Modes
          2. 24.3.4.7.2 UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
            1. 24.3.4.7.2.1 Registers Available for the UART Function
            2. 24.3.4.7.2.2 Registers Available for the IrDA Function (UART3 Only)
            3. 24.3.4.7.2.3 Registers Available for the CIR Function (UART3 Only)
        8. 24.3.4.8 Protocol Formatting
          1. 24.3.4.8.1 UART Mode
            1. 24.3.4.8.1.1 UART Clock Generation: Baud Rate Generation
            2. 24.3.4.8.1.2 Choosing the Appropriate Divisor Value
            3. 24.3.4.8.1.3 UART Data Formatting
              1. 24.3.4.8.1.3.1 Frame Formatting
              2. 24.3.4.8.1.3.2 Hardware Flow Control
              3. 24.3.4.8.1.3.3 Software Flow Control
                1. 24.3.4.8.1.3.3.1 Receive (RX)
                2. 24.3.4.8.1.3.3.2 Transmit (TX)
              4. 24.3.4.8.1.3.4 Autobauding Modes
              5. 24.3.4.8.1.3.5 Error Detection
              6. 24.3.4.8.1.3.6 Overrun During Receive
              7. 24.3.4.8.1.3.7 Time-Out and Break Conditions
                1. 24.3.4.8.1.3.7.1 Time-Out Counter
                2. 24.3.4.8.1.3.7.2 Break Condition
          2. 24.3.4.8.2 IrDA Mode (UART3 Only)
            1. 24.3.4.8.2.1 IrDA Clock Generation: Baud Generator
            2. 24.3.4.8.2.2 Choosing the Appropriate Divisor Value
            3. 24.3.4.8.2.3 IrDA Data Formatting
              1. 24.3.4.8.2.3.1 IR RX Polarity Control
              2. 24.3.4.8.2.3.2 IrDA Reception Control
              3. 24.3.4.8.2.3.3 IR Address Checking
              4. 24.3.4.8.2.3.4 Frame Closing
              5. 24.3.4.8.2.3.5 Store and Controlled Transmission
              6. 24.3.4.8.2.3.6 Error Detection
              7. 24.3.4.8.2.3.7 Underrun During Transmission
              8. 24.3.4.8.2.3.8 Overrun During Receive
              9. 24.3.4.8.2.3.9 Status FIFO
            4. 24.3.4.8.2.4 SIR Mode Data Formatting
              1. 24.3.4.8.2.4.1 Abort Sequence
              2. 24.3.4.8.2.4.2 Pulse Shaping
              3. 24.3.4.8.2.4.3 SIR Free Format Programming
            5. 24.3.4.8.2.5 MIR and FIR Mode Data Formatting
          3. 24.3.4.8.3 CIR Mode (UART3 Only)
            1. 24.3.4.8.3.1 CIR Mode Clock Generation
            2. 24.3.4.8.3.2 CIR Data Formatting
              1. 24.3.4.8.3.2.1 IR RX Polarity Control
              2. 24.3.4.8.3.2.2 CIR Transmission
      5. 24.3.5 UART/IrDA/CIR Basic Programming Model
        1. 24.3.5.1 Global Initialization
          1. 24.3.5.1.1 Surrounding Modules Global Initialization
          2. 24.3.5.1.2 UART/IrDA/CIR Module Global Initialization
        2. 24.3.5.2 Mode selection
        3. 24.3.5.3 Submode selection
        4. 24.3.5.4 Load FIFO trigger and DMA mode settings
          1. 24.3.5.4.1 DMA mode Settings
          2. 24.3.5.4.2 FIFO Trigger Settings
        5. 24.3.5.5 Protocol, Baud rate and interrupt settings
          1. 24.3.5.5.1 Baud rate settings
          2. 24.3.5.5.2 Interrupt settings
          3. 24.3.5.5.3 Protocol settings
          4. 24.3.5.5.4 UART/IrDA(SIR/MIR/FIR)/CIR
        6. 24.3.5.6 Hardware and Software Flow Control Configuration
          1. 24.3.5.6.1 Hardware Flow Control Configuration
          2. 24.3.5.6.2 Software Flow Control Configuration
        7. 24.3.5.7 IrDA Programming Model (UART3 Only)
          1. 24.3.5.7.1 SIR mode
            1. 24.3.5.7.1.1 Receive
            2. 24.3.5.7.1.2 Transmit
          2. 24.3.5.7.2 MIR mode
            1. 24.3.5.7.2.1 Receive
            2. 24.3.5.7.2.2 Transmit
          3. 24.3.5.7.3 FIR mode
            1. 24.3.5.7.3.1 Receive
            2. 24.3.5.7.3.2 Transmit
      6. 24.3.6 UART/IrDA/CIR Register Manual
        1. 24.3.6.1 UART/IrDA/CIR Instance Summary
        2. 24.3.6.2 UART/IrDA/CIR Registers
          1. 24.3.6.2.1 UART/IrDA/CIR Register Summary
          2. 24.3.6.2.2 UART/IrDA/CIR Register Description
    4. 24.4  Multichannel Serial Peripheral Interface
      1. 24.4.1 McSPI Overview
      2. 24.4.2 McSPI Environment
        1. 24.4.2.1 Basic McSPI Pins for Master Mode
        2. 24.4.2.2 Basic McSPI Pins for Slave Mode
        3. 24.4.2.3 Multichannel SPI Protocol and Data Format
          1. 24.4.2.3.1 Transfer Format
        4. 24.4.2.4 SPI in Master Mode
        5. 24.4.2.5 SPI in Slave Mode
      3. 24.4.3 McSPI Integration
      4. 24.4.4 McSPI Functional Description
        1. 24.4.4.1 McSPI Block Diagram
        2. 24.4.4.2 Reset
        3. 24.4.4.3 Master Mode
          1. 24.4.4.3.1 Master Mode Features
          2. 24.4.4.3.2 Master Transmit-and-Receive Mode (Full Duplex)
          3. 24.4.4.3.3 Master Transmit-Only Mode (Half Duplex)
          4. 24.4.4.3.4 Master Receive-Only Mode (Half Duplex)
          5. 24.4.4.3.5 Single-Channel Master Mode
            1. 24.4.4.3.5.1 Programming Tips When Switching to Another Channel
            2. 24.4.4.3.5.2 Force SPIEN[x] Mode
            3. 24.4.4.3.5.3 Turbo Mode
          6. 24.4.4.3.6 Start-Bit Mode
          7. 24.4.4.3.7 Chip-Select Timing Control
          8. 24.4.4.3.8 Programmable SPI Clock
            1. 24.4.4.3.8.1 Clock Ratio Granularity
        4. 24.4.4.4 Slave Mode
          1. 24.4.4.4.1 Dedicated Resources
          2. 24.4.4.4.2 Slave Transmit-and-Receive Mode
          3. 24.4.4.4.3 Slave Transmit-Only Mode
          4. 24.4.4.4.4 Slave Receive-Only Mode
        5. 24.4.4.5 3-Pin or 4-Pin Mode
        6. 24.4.4.6 FIFO Buffer Management
          1. 24.4.4.6.1 Buffer Almost Full
          2. 24.4.4.6.2 Buffer Almost Empty
          3. 24.4.4.6.3 End of Transfer Management
        7. 24.4.4.7 Interrupts
          1. 24.4.4.7.1 Interrupt Events in Master Mode
            1. 24.4.4.7.1.1 TXx_EMPTY
            2. 24.4.4.7.1.2 TXx_UNDERFLOW
            3. 24.4.4.7.1.3 RXx_ FULL
            4. 24.4.4.7.1.4 End Of Word Count
          2. 24.4.4.7.2 Interrupt Events in Slave Mode
            1. 24.4.4.7.2.1 TXx_EMPTY
            2. 24.4.4.7.2.2 TXx_UNDERFLOW
            3. 24.4.4.7.2.3 RXx_FULL
            4. 24.4.4.7.2.4 RX0_OVERFLOW
            5. 24.4.4.7.2.5 End Of Word Count
          3. 24.4.4.7.3 Interrupt-Driven Operation
          4. 24.4.4.7.4 Polling
        8. 24.4.4.8 DMA Requests
        9. 24.4.4.9 Power Saving Management
          1. 24.4.4.9.1 Normal Mode
          2. 24.4.4.9.2 Idle Mode
            1. 24.4.4.9.2.1 Wake-Up Event in Smart-Idle Mode
            2. 24.4.4.9.2.2 Transitions From Smart-Idle Mode to Normal Mode
            3. 24.4.4.9.2.3 Force-Idle Mode
      5. 24.4.5 McSPI Programming Guide
        1. 24.4.5.1 Global Initialization
          1. 24.4.5.1.1 Surrounding Modules Global Initialization
          2. 24.4.5.1.2 McSPI Global Initialization
            1. 24.4.5.1.2.1 Main Sequence – McSPI Global Initialization
        2. 24.4.5.2 Operational Mode Configuration
          1. 24.4.5.2.1 McSPI Operational Modes
            1. 24.4.5.2.1.1 Common Transfer Sequence
            2. 24.4.5.2.1.2 End of Transfer Sequences
            3. 24.4.5.2.1.3 Transmit-and-Receive (Master and Slave)
            4. 24.4.5.2.1.4 Transmit-Only (Master and Slave)
              1. 24.4.5.2.1.4.1 Based on Interrupt Requests
              2. 24.4.5.2.1.4.2 Based on DMA Write Requests
            5. 24.4.5.2.1.5 Master Normal Receive-Only
              1. 24.4.5.2.1.5.1 Based on Interrupt Requests
              2. 24.4.5.2.1.5.2 Based on DMA Read Requests
            6. 24.4.5.2.1.6 Master Turbo Receive-Only
              1. 24.4.5.2.1.6.1 Based on Interrupt Requests
              2. 24.4.5.2.1.6.2 Based on DMA Read Requests
            7. 24.4.5.2.1.7 Slave Receive-Only
            8. 24.4.5.2.1.8 Transfer Procedures With FIFO
              1. 24.4.5.2.1.8.1 Common Transfer Sequence in FIFO Mode
              2. 24.4.5.2.1.8.2 End of Transfer Sequences in FIFO Mode
              3. 24.4.5.2.1.8.3 Transmit-and-Receive With Word Count
              4. 24.4.5.2.1.8.4 Transmit-and-Receive Without Word Count
              5. 24.4.5.2.1.8.5 Transmit-Only
              6. 24.4.5.2.1.8.6 Receive-Only With Word Count
              7. 24.4.5.2.1.8.7 Receive-Only Without Word Count
        3. 24.4.5.3 Common Transfer Procedures Without FIFO – Polling Method
          1. 24.4.5.3.1 Receive-Only Procedure – Polling Method
          2. 24.4.5.3.2 Receive-Only Procedure – Interrupt Method
          3. 24.4.5.3.3 Transmit-Only Procedure – Polling Method
          4. 24.4.5.3.4 Transmit-and-Receive Procedure – Polling Method
      6. 24.4.6 McSPI Register Manual
        1. 24.4.6.1 McSPI Instance Summary
        2. 24.4.6.2 McSPI Registers
          1. 24.4.6.2.1 McSPI Register Summary
          2. 24.4.6.2.2 McSPI Register Description
    5. 24.5  Quad Serial Peripheral Interface
      1. 24.5.1 Quad Serial Peripheral Interface Overview
      2. 24.5.2 QSPI Environment
      3. 24.5.3 QSPI Integration
      4. 24.5.4 QSPI Functional Description
        1. 24.5.4.1 QSPI Block Diagram
          1. 24.5.4.1.1 SFI Register Control
          2. 24.5.4.1.2 SFI Translator
          3. 24.5.4.1.3 SPI Control Interface
          4. 24.5.4.1.4 SPI Clock Generator
          5. 24.5.4.1.5 SPI Control State-Machine
          6. 24.5.4.1.6 SPI Data Shifter
        2. 24.5.4.2 QSPI Clock Configuration
        3. 24.5.4.3 QSPI Interrupt Requests
        4. 24.5.4.4 QSPI Memory Regions
      5. 24.5.5 QSPI Register Manual
        1. 24.5.5.1 QSPI Instance Summary
        2. 24.5.5.2 QSPI registers
          1. 24.5.5.2.1 QSPI Register Summary
          2. 24.5.5.2.2 QSPI Register Description
    6. 24.6  Multichannel Audio Serial Port
      1. 24.6.1 McASP Overview
      2. 24.6.2 McASP Environment
        1. 24.6.2.1 McASP Signals
        2. 24.6.2.2 Protocols and Data Formats
          1. 24.6.2.2.1 Protocols Supported
          2. 24.6.2.2.2 Definition of Terms
          3. 24.6.2.2.3 TDM Format
          4. 24.6.2.2.4 I2S Format
          5. 24.6.2.2.5 S/PDIF Coding Format
            1. 24.6.2.2.5.1 Biphase-Mark Code
            2. 24.6.2.2.5.2 S/PDIF Subframe Format
            3. 24.6.2.2.5.3 Frame Format
      3. 24.6.3 McASP Integration
      4. 24.6.4 McASP Functional Description
        1. 24.6.4.1  McASP Block Diagram
        2. 24.6.4.2  McASP Clock and Frame-Sync Configurations
          1. 24.6.4.2.1 McASP Transmit Clock
          2. 24.6.4.2.2 McASP Receive Clock
          3. 24.6.4.2.3 Frame-Sync Generator
          4. 24.6.4.2.4 Synchronous and Asynchronous Transmit and Receive Operations
        3. 24.6.4.3  Serializers
        4. 24.6.4.4  Format Units
          1. 24.6.4.4.1 Transmit Format Unit
            1. 24.6.4.4.1.1 TDM Mode Transmission Data Alignment Settings
            2. 24.6.4.4.1.2 DIT Mode Transmission Data Alignment Settings
          2. 24.6.4.4.2 Receive Format Unit
            1. 24.6.4.4.2.1 TDM Mode Reception Data Alignment Settings
        5. 24.6.4.5  State-Machines
        6. 24.6.4.6  TDM Sequencers
        7. 24.6.4.7  McASP Software Reset
        8. 24.6.4.8  McASP Power Management
        9. 24.6.4.9  Transfer Modes
          1. 24.6.4.9.1 Burst Transfer Mode
          2. 24.6.4.9.2 Time-Division Multiplexed (TDM) Transfer Mode
            1. 24.6.4.9.2.1 TDM Time Slots Generation and Processing
            2. 24.6.4.9.2.2 Special 384-Slot TDM Mode for Connection to External DIR
          3. 24.6.4.9.3 DIT Transfer Mode
            1. 24.6.4.9.3.1 Transmit DIT Encoding
            2. 24.6.4.9.3.2 Transmit DIT Clock and Frame-Sync Generation
            3. 24.6.4.9.3.3 DIT Channel Status and User Data Register Files
        10. 24.6.4.10 Data Transmission and Reception
          1. 24.6.4.10.1 Data Ready Status and Event/Interrupt Generation
            1. 24.6.4.10.1.1 Transmit Data Ready
            2. 24.6.4.10.1.2 Receive Data Ready
            3. 24.6.4.10.1.3 Transfers Through the Data Port (DATA)
            4. 24.6.4.10.1.4 Transfers Through the Configuration Bus (CFG)
            5. 24.6.4.10.1.5 Using a Device CPU for McASP Servicing
            6. 24.6.4.10.1.6 Using the DMA for McASP Servicing
        11. 24.6.4.11 McASP Audio FIFO (AFIFO)
          1. 24.6.4.11.1 AFIFO Data Transmission
            1. 24.6.4.11.1.1 Transmit DMA Event Pacer
          2. 24.6.4.11.2 AFIFO Data Reception
            1. 24.6.4.11.2.1 Receive DMA Event Pacer
          3. 24.6.4.11.3 Arbitration Between Transmit and Receive DMA Requests
        12. 24.6.4.12 McASP Events and Interrupt Requests
          1. 24.6.4.12.1 Transmit Data Ready Event and Interrupt
          2. 24.6.4.12.2 Receive Data Ready Event and Interrupt
          3. 24.6.4.12.3 Error Interrupt
          4. 24.6.4.12.4 Multiple Interrupts
        13. 24.6.4.13 DMA Requests
        14. 24.6.4.14 Loopback Modes
          1. 24.6.4.14.1 Loopback Mode Configurations
        15. 24.6.4.15 Error Reporting
          1. 24.6.4.15.1 Buffer Underrun Error -Transmitter
          2. 24.6.4.15.2 Buffer Overrun Error-Receiver
          3. 24.6.4.15.3 DATA Port Error - Transmitter
          4. 24.6.4.15.4 DATA Port Error - Receiver
          5. 24.6.4.15.5 Unexpected Frame Sync Error
          6. 24.6.4.15.6 Clock Failure Detection
            1. 24.6.4.15.6.1 Clock Failure Check Startup
            2. 24.6.4.15.6.2 Transmit Clock Failure Check and Recovery
            3. 24.6.4.15.6.3 Receive Clock Failure Check and Recovery
      5. 24.6.5 McASP Low-Level Programming Model
        1. 24.6.5.1 Global Initialization
          1. 24.6.5.1.1 Surrounding Modules Global Initialization
          2. 24.6.5.1.2 McASP Global Initialization
            1. 24.6.5.1.2.1 Main Sequence – McASP Global Initialization for DIT-Transmission
              1. 24.6.5.1.2.1.1 Subsequence – Transmit Format Unit Configuration for DIT-Transmission
              2. 24.6.5.1.2.1.2 Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
              3. 24.6.5.1.2.1.3 Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
              4. 24.6.5.1.2.1.4 Subsequence - McASP Pins Functional Configuration
              5. 24.6.5.1.2.1.5 Subsequence – DIT-specific Subframe Fields Configuration
            2. 24.6.5.1.2.2 Main Sequence – McASP Global Initialization for TDM-Reception
              1. 24.6.5.1.2.2.1 Subsequence – Receive Format Unit Configuration in TDM Mode
              2. 24.6.5.1.2.2.2 Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
              3. 24.6.5.1.2.2.3 Subsequence – Receive Clock Generator Configuration
              4. 24.6.5.1.2.2.4 Subsequence—McASP Receiver Pins Functional Configuration
            3. 24.6.5.1.2.3 Main Sequence – McASP Global Initialization for TDM -Transmission
              1. 24.6.5.1.2.3.1 Subsequence – Transmit Format Unit Configuration in TDM Mode
              2. 24.6.5.1.2.3.2 Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
              3. 24.6.5.1.2.3.3 Subsequence – Transmit Clock Generator Configuration for TDM Cases
              4. 24.6.5.1.2.3.4 Subsequence—McASP Transmit Pins Functional Configuration
        2. 24.6.5.2 Operational Modes Configuration
          1. 24.6.5.2.1 McASP Transmission Modes
            1. 24.6.5.2.1.1 Main Sequence – McASP DIT- /TDM- Polling Transmission Method
            2. 24.6.5.2.1.2 Main Sequence – McASP DIT- /TDM - Interrupt Transmission Method
            3. 24.6.5.2.1.3 Main Sequence –McASP DIT- /TDM - Mode DMA Transmission Method
          2. 24.6.5.2.2 McASP Reception Modes
            1. 24.6.5.2.2.1 Main Sequence – McASP Polling Reception Method
            2. 24.6.5.2.2.2 Main Sequence – McASP TDM - Interrupt Reception Method
            3. 24.6.5.2.2.3 Main Sequence – McASP TDM - Mode DMA Reception Method
          3. 24.6.5.2.3 McASP Event Servicing
            1. 24.6.5.2.3.1 McASP DIT-/TDM- Transmit Interrupt Events Servicing
            2. 24.6.5.2.3.2 McASP TDM- Receive Interrupt Events Servicing
            3. 24.6.5.2.3.3 3137
            4. 24.6.5.2.3.4 Subsequence – McASP DIT-/TDM -Modes Transmit Error Handling
            5. 24.6.5.2.3.5 Subsequence – McASP Receive Error Handling
      6. 24.6.6 McASP Register Manual
        1. 24.6.6.1 McASP Instance Summary
        2. 24.6.6.2 McASP Registers
          1. 24.6.6.2.1 MCASP_CFG Register Summary
          2. 24.6.6.2.2 MCASP_CFG Register Description
          3. 24.6.6.2.3 MCASP_AFIFO Register Summary
          4. 24.6.6.2.4 MCASP_AFIFO Register Description
          5. 24.6.6.2.5 MCASP_DAT Register Summary
          6. 24.6.6.2.6 MCASP_DAT Register Description
    7. 24.7  SuperSpeed USB DRD
      1. 24.7.1 SuperSpeed USB DRD Subsystem Overview
        1. 24.7.1.1 Main Features
        2. 24.7.1.2 Unsupported Features
      2. 24.7.2 SuperSpeed USB DRD Subsystem Environment
        1. 24.7.2.1 SuperSpeed USB DRD Subsystem I/O Interfaces
        2. 24.7.2.2 SuperSpeed USB Subsystem Application
      3. 24.7.3 SuperSpeed USB Subsystem Integration
    8. 24.8  SATA Controller
      1. 24.8.1 SATA Controller Overview
        1. 24.8.1.1 SATA Controller
          1. 24.8.1.1.1 AHCI Mode Overview
          2. 24.8.1.1.2 Native Command Queuing
          3. 24.8.1.1.3 SATA Transport Layer Functionalities
          4. 24.8.1.1.4 SATA Link Layer Functionalities
        2. 24.8.1.2 SATA Controller Features
      2. 24.8.2 SATA Controller Environment
      3. 24.8.3 SATA Controller Integration
      4. 24.8.4 SATA Controller Functional Description
        1. 24.8.4.1  SATA Controller Block Diagram
        2. 24.8.4.2  SATA Controller Link Layer Protocol and Data Format
          1. 24.8.4.2.1 SATA 8b/10b Parallel Encoding/Decoding
          2. 24.8.4.2.2 SATA Stream Dword Components
          3. 24.8.4.2.3 Scrambling/Descrambling Processing
        3. 24.8.4.3  Resets
          1. 24.8.4.3.1 Hardware Reset
          2. 24.8.4.3.2 Software Initiated Resets
            1. 24.8.4.3.2.1 Software Reset
            2. 24.8.4.3.2.2 Port Reset
            3. 24.8.4.3.2.3 HBA Reset
        4. 24.8.4.4  Power Management
          1. 24.8.4.4.1 SATA Specific Power Management
            1. 24.8.4.4.1.1 PARTIAL Power Mode
            2. 24.8.4.4.1.2 Slumber Power Mode
            3. 24.8.4.4.1.3 Software Control over Low Power States
            4. 24.8.4.4.1.4 Aggressive Power Management
          2. 24.8.4.4.2 Master Standby and Slave Idle Management Protocols
          3. 24.8.4.4.3 Clock Gating Synchronization
          4. 24.8.4.4.4 3187
        5. 24.8.4.5  Interrupt Requests
          1. 24.8.4.5.1 Interrupt Generation
          2. 24.8.4.5.2 Levels of Interrupt Control
          3. 24.8.4.5.3 Interrupt Events Description
            1. 24.8.4.5.3.1  Task File Error Status
            2. 24.8.4.5.3.2  Host Bus Fatal Error
            3. 24.8.4.5.3.3  Interface Fatal Error Status
            4. 24.8.4.5.3.4  Interface Non-Fatal Error Status
            5. 24.8.4.5.3.5  Overflow Status
            6. 24.8.4.5.3.6  Incorrect Port Multiplier Status
            7. 24.8.4.5.3.7  PHYReady Change Status
            8. 24.8.4.5.3.8  Port Connect Change Status
            9. 24.8.4.5.3.9  Descriptor Processed
            10. 24.8.4.5.3.10 Unknown FIS Interrupt
            11. 24.8.4.5.3.11 Set Device Bits Interrupt
            12. 24.8.4.5.3.12 DMA Setup FIS Interrupt
            13. 24.8.4.5.3.13 PIO Setup FIS Interrupt
            14. 24.8.4.5.3.14 Device to Host Register FIS Interrupt
          4. 24.8.4.5.4 Interrupt Condition Control
          5. 24.8.4.5.5 Command Completion Coalescing Interrupts
            1. 24.8.4.5.5.1 CCC Interrupt Based on Expired Timeout Value
            2. 24.8.4.5.5.2 CCC Interrupt Based on Completion Count
        6. 24.8.4.6  System Memory FIS Descriptors
          1. 24.8.4.6.1 Command List Structure Basics
          2. 24.8.4.6.2 Supported Types of Commands
          3. 24.8.4.6.3 Received FIS Structures
          4. 24.8.4.6.4 FIS Descriptors Summary
        7. 24.8.4.7  Transport Layer FIS-Based Interactions
          1. 24.8.4.7.1 Software Processing of the Port Command List
          2. 24.8.4.7.2 Handling the Received FIS Descriptors
        8. 24.8.4.8  DMA Port Configuration
        9. 24.8.4.9  Port Multiplier Operation
          1. 24.8.4.9.1 Command-Based Switching Mode
            1. 24.8.4.9.1.1 Port Multiplier NCQ and Non-NCQ Commands Generation
          2. 24.8.4.9.2 Port Multiplier Enumeration
        10. 24.8.4.10 Activity LED Generation Functionality
        11. 24.8.4.11 Supported Types of SATA Transfers
          1. 24.8.4.11.1 Supported Higher Level Protocols
        12. 24.8.4.12 SATA Controller AHCI Hardware Register Interface
      5. 24.8.5 SATA Controller Low Level Programming Model
        1. 24.8.5.1 Global Initialization
          1. 24.8.5.1.1 Surrounding Modules Global Initialization
          2. 24.8.5.1.2 SATA Controller Global Initialization
            1. 24.8.5.1.2.1 Main Sequence SATA Controller Global Initialization
            2. 24.8.5.1.2.2 SubSequence – Firmware Capability Writes
          3. 24.8.5.1.3 Issue Command - Main Sequence
          4. 24.8.5.1.4 Receive FIS—Main Sequence
      6. 24.8.6 SATA Controller Register Manual
        1. 24.8.6.1 SATA Controller Instance Summary
        2. 24.8.6.2 DWC_ahsata Registers
          1. 24.8.6.2.1 DWC_ahsata Register Summary
          2. 24.8.6.2.2 DWC_ahsata Register Description
        3. 24.8.6.3 SATAMAC_wrapper Registers
          1. 24.8.6.3.1 SATAMAC_wrapper Register Summary
          2. 24.8.6.3.2 SATAMAC_wrapper Register Description
    9. 24.9  PCIe Controller
      1. 24.9.1 PCIe Controller Subsystem Overview
        1. 24.9.1.1 PCIe Controllers Key Features
      2. 24.9.2 PCIe Controller Environment
      3. 24.9.3 PCIe Controllers Integration
      4. 24.9.4 PCIe SS Controller Functional Description
        1. 24.9.4.1 PCIe Controller Functional Block Diagram
        2. 24.9.4.2 PCIe Traffics
        3. 24.9.4.3 PCIe Controller Ports on L3_MAIN Interconnect
          1. 24.9.4.3.1 PCIe Controller Master Port
            1. 24.9.4.3.1.1 PCIe Controller Master Port to MMU Routing
          2. 24.9.4.3.2 PCIe Controller Slave Port
          3. 24.9.4.3.3 3255
        4. 24.9.4.4 PCIe Controller Reset Management
          1. 24.9.4.4.1 PCIe Reset Types and Stickiness
          2. 24.9.4.4.2 PCIe Reset Conditions
            1. 24.9.4.4.2.1 PCIe Main Reset
              1. 24.9.4.4.2.1.1 PCIe Subsystem Cold Main Reset Source
              2. 24.9.4.4.2.1.2 PCIe Subsystem Warm Main Reset Sources
            2. 24.9.4.4.2.2 PCIe Standard Specific Resets to the PCIe Core Logic
        5. 24.9.4.5 PCIe Controller Power Management
          1. 24.9.4.5.1 PCIe Protocol Power Management
            1. 24.9.4.5.1.1 PCIe Device/function power state (D-state)
            2. 24.9.4.5.1.2 PCIe Controller PIPE Powerstate (Powerdown Control)
          2. 24.9.4.5.2 PCIE Controller Clocks Management
            1. 24.9.4.5.2.1 PCIe Clock Domains
            2. 24.9.4.5.2.2 PCIe Controller Idle/Standby Clock Management Interfaces
              1. 24.9.4.5.2.2.1 PCIe Controller Master Standby Behavior
              2. 24.9.4.5.2.2.2 PCIe Controller Slave Idle/Disconnect Behavior
                1. 24.9.4.5.2.2.2.1 PCIe Controller Idle Sequence During D3cold/L3 State
        6. 24.9.4.6 PCIe Controller Interrupt Requests
          1. 24.9.4.6.1 PCIe Controller Main Hardware Management
            1. 24.9.4.6.1.1 PCIe Management Interrupt Events
            2. 24.9.4.6.1.2 PCIe Error Interrupt Events
            3. 24.9.4.6.1.3 Summary of PCIe Controller Main Hardware Interrupt Events
          2. 24.9.4.6.2 PCIe Controller Legacy and MSI Virtual Interrupts Management
            1. 24.9.4.6.2.1 Legacy PCI Interrupts (INTx)
              1. 24.9.4.6.2.1.1 Legacy PCI Interrupt Events Overview
              2. 24.9.4.6.2.1.2 Legacy PCI Interrupt Transmission (EP mode only)
              3. 24.9.4.6.2.1.3 Legacy PCI Interrupt Reception (RC mode only)
            2. 24.9.4.6.2.2 PCIe Controller Message Signaled Interrupts (MSI)
              1. 24.9.4.6.2.2.1 PCIe Specific MSI Interrupt Event Overview
              2. 24.9.4.6.2.2.2 PCIe Controller MSI Transmission Methods (EP mode)
                1. 24.9.4.6.2.2.2.1 PCIe Controller MSI transmission, hardware method
                2. 24.9.4.6.2.2.2.2 PCIe Controller MSI transmission, software method
              3. 24.9.4.6.2.2.3 PCIe Controller MSI Reception (RC mode)
          3. 24.9.4.6.3 PCIe Controller MSI Hardware Interrupt Events
        7. 24.9.4.7 PCIe Controller Address Spaces and Address Translation
        8. 24.9.4.8 PCIe Traffic Requesting and Responding
          1. 24.9.4.8.1 PCIe Memory-type (Mem) Traffic Management
            1. 24.9.4.8.1.1 PCIe Memory Requesting
            2. 24.9.4.8.1.2 PCIe Memory Responding
          2. 24.9.4.8.2 PCIe Configuration Type (Cfg) Traffic Management
            1. 24.9.4.8.2.1 RC Self-configuration (RC Only)
            2. 24.9.4.8.2.2 Configuration Requests over PCIe (RC Only)
            3. 24.9.4.8.2.3 Configuration Responding over PCIe (EP Only)
          3. 24.9.4.8.3 PCIe I/O-type (IO) traffic management
            1. 24.9.4.8.3.1 PCIe I/O requesting (RC only)
            2. 24.9.4.8.3.2 PCIe IO BAR initialization before enumeration (EP only)
            3. 24.9.4.8.3.3 PCIe I/O responding (PCI legacy EP only)
          4. 24.9.4.8.4 PCIe Message-type (Msg) traffic management
        9. 24.9.4.9 PCIe Programming Register Interface
          1. 24.9.4.9.1 PCIe Register Access
          2. 24.9.4.9.2 Double Mapping of the PCIe Local Control Registers
          3. 24.9.4.9.3 Base Address Registers (BAR) Initialization
      5. 24.9.5 PCIe Controller Low Level Programming Model
        1. 24.9.5.1 Surrounding Modules Global Initialization
        2. 24.9.5.2 Main Sequence of PCIe Controllers Initalization
      6. 24.9.6 PCIe Standard Registers vs PCIe Subsystem Hardware Registers Mapping
      7. 24.9.7 PCIe Controller Register Manual
        1. 24.9.7.1 PCIe Controller Instance Summary
        2. 24.9.7.2 PCIe_SS_EP_CFG_PCIe Registers
          1. 24.9.7.2.1 PCIe_SS_EP_CFG_PCIe Register Summary
          2. 24.9.7.2.2 PCIe_SS_EP_CFG_PCIe Register Description
          3. 24.9.7.2.3 3317
        3. 24.9.7.3 PCIe_SS_EP_CFG_DBICS Registers
          1. 24.9.7.3.1 PCIe_SS_EP_CFG_DBICS Register Summary
          2. 24.9.7.3.2 PCIe_SS_EP_CFG_DBICS Register Description
        4. 24.9.7.4 PCIe_SS_RC_CFG_DBICS Registers
          1. 24.9.7.4.1 PCIe_SS_RC_CFG_DBICS Register Summary
          2. 24.9.7.4.2 PCIe_SS_RC_CFG_DBICS Register Description
        5. 24.9.7.5 PCIe_SS_PL_CONF Registers
          1. 24.9.7.5.1 PCIe_SS_PL_CONF Register Summary
          2. 24.9.7.5.2 PCIe_SS_PL_CONF Register Description
        6. 24.9.7.6 PCIe_SS_EP_CFG_DBICS2 Registers
          1. 24.9.7.6.1 PCIe_SS_EP_CFG_DBICS2 Register Summary
          2. 24.9.7.6.2 PCIe_SS_EP_CFG_DBICS2 Register Description
        7. 24.9.7.7 PCIe_SS_RC_CFG_DBICS2 Registers
          1. 24.9.7.7.1 PCIe_SS_RC_CFG_DBICS2 Register Summary
          2. 24.9.7.7.2 PCIe_SS_RC_CFG_DBICS2 Register Description
        8. 24.9.7.8 PCIe_SS_TI_CONF Registers
          1. 24.9.7.8.1 PCIe_SS_TI_CONF Register Summary
          2. 24.9.7.8.2 PCIe_SS_TI_CONF Register Description
    10. 24.10 DCAN
      1. 24.10.1 DCAN Overview
        1. 24.10.1.1 Features
      2. 24.10.2 DCAN Environment
        1. 24.10.2.1 CAN Network Basics
      3. 24.10.3 DCAN Integration
      4. 24.10.4 DCAN Functional Description
        1. 24.10.4.1  Module Clocking Requirements
        2. 24.10.4.2  Interrupt Functionality
          1. 24.10.4.2.1 Message Object Interrupts
          2. 24.10.4.2.2 Status Change Interrupts
          3. 24.10.4.2.3 Error Interrupts
        3. 24.10.4.3  DMA Functionality
        4. 24.10.4.4  Local Power-Down Mode
          1. 24.10.4.4.1 Entering Local Power-Down Mode
          2. 24.10.4.4.2 Wakeup From Local Power Down
        5. 24.10.4.5  Parity Check Mechanism
          1. 24.10.4.5.1 Behavior on Parity Error
          2. 24.10.4.5.2 Parity Testing
        6. 24.10.4.6  Debug/Suspend Mode
        7. 24.10.4.7  Configuration of Message Objects Description
          1. 24.10.4.7.1 Configuration of a Transmit Object for Data Frames
          2. 24.10.4.7.2 Configuration of a Transmit Object for Remote Frames
          3. 24.10.4.7.3 Configuration of a Single Receive Object for Data Frames
          4. 24.10.4.7.4 Configuration of a Single Receive Object for Remote Frames
          5. 24.10.4.7.5 Configuration of a FIFO Buffer
        8. 24.10.4.8  Message Handling
          1. 24.10.4.8.1  Message Handler Overview
          2. 24.10.4.8.2  Receive/Transmit Priority
          3. 24.10.4.8.3  Transmission of Messages in Event Driven CAN Communication
          4. 24.10.4.8.4  Updating a Transmit Object
          5. 24.10.4.8.5  Changing a Transmit Object
          6. 24.10.4.8.6  Acceptance Filtering of Received Messages
          7. 24.10.4.8.7  Reception of Data Frames
          8. 24.10.4.8.8  Reception of Remote Frames
          9. 24.10.4.8.9  Reading Received Messages
          10. 24.10.4.8.10 Requesting New Data for a Receive Object
          11. 24.10.4.8.11 Storing Received Messages in FIFO Buffers
          12. 24.10.4.8.12 Reading From a FIFO Buffer
        9. 24.10.4.9  CAN Bit Timing
          1. 24.10.4.9.1 Bit Time and Bit Rate
            1. 24.10.4.9.1.1 Synchronization Segment
            2. 24.10.4.9.1.2 Propagation Time Segment
            3. 24.10.4.9.1.3 Phase Buffer Segments and Synchronization
            4. 24.10.4.9.1.4 Oscillator Tolerance Range
          2. 24.10.4.9.2 DCAN Bit Timing Registers
            1. 24.10.4.9.2.1 Calculation of the Bit Timing Parameters
            2. 24.10.4.9.2.2 Example for Bit Timing Calculation
        10. 24.10.4.10 Message Interface Register Sets
          1. 24.10.4.10.1 Message Interface Register Sets 1 and 2
          2. 24.10.4.10.2 IF3 Register Set
        11. 24.10.4.11 Message RAM
          1. 24.10.4.11.1 Structure of Message Objects
          2. 24.10.4.11.2 Addressing Message Objects in RAM
          3. 24.10.4.11.3 Message RAM Representation in Debug/Suspend Mode
          4. 24.10.4.11.4 Message RAM Representation in Direct Access Mode
        12. 24.10.4.12 CAN Operation
          1. 24.10.4.12.1 CAN Module Initialization
            1. 24.10.4.12.1.1 Configuration of CAN Bit Timing
            2. 24.10.4.12.1.2 Configuration of Message Objects
            3. 24.10.4.12.1.3 DCAN RAM Hardware Initialization
          2. 24.10.4.12.2 CAN Message Transfer (Normal Operation)
            1. 24.10.4.12.2.1 Automatic Retransmission
            2. 24.10.4.12.2.2 Auto-Bus-On
          3. 24.10.4.12.3 Test Modes
            1. 24.10.4.12.3.1 Silent Mode
            2. 24.10.4.12.3.2 Loopback Mode
            3. 24.10.4.12.3.3 External Loopback Mode
            4. 24.10.4.12.3.4 Loopback Mode Combined With Silent Mode
            5. 24.10.4.12.3.5 Software Control of CAN_TX Pin
        13. 24.10.4.13 GPIO Support
      5. 24.10.5 DCAN Register Manual
        1. 24.10.5.1 DCAN Instance Summary
        2. 24.10.5.2 DCAN Registers
          1. 24.10.5.2.1 DCAN Register Summary
          2. 24.10.5.2.2 DCAN Register Description
    11. 24.11 Gigabit Ethernet Switch (GMAC_SW)
      1. 24.11.1 GMAC_SW Overview
        1. 24.11.1.1 Features
        2. 24.11.1.2 3415
      2. 24.11.2 GMAC_SW Environment
        1. 24.11.2.1 G/MII Interface
        2. 24.11.2.2 RMII Interface
        3. 24.11.2.3 RGMII Interface
      3. 24.11.3 GMAC_SW Integration
      4. 24.11.4 GMAC_SW Functional Description
        1. 24.11.4.1  Functional Block Diagram
        2. 24.11.4.2  GMAC_SW Ports
          1. 24.11.4.2.1 Interface Mode Selection
        3. 24.11.4.3  Clocking
          1. 24.11.4.3.1 Subsystem Clocking
          2. 24.11.4.3.2 Interface Clocking
            1. 24.11.4.3.2.1 G/MII Interface Clocking
            2. 24.11.4.3.2.2 RGMII Interface Clocking
            3. 24.11.4.3.2.3 RMII Interface Clocking
            4. 24.11.4.3.2.4 MDIO Clocking
        4. 24.11.4.4  Software IDLE
        5. 24.11.4.5  Interrupt Functionality
          1. 24.11.4.5.1 Receive Packet Completion Pulse Interrupt (RX_PULSE)
          2. 24.11.4.5.2 Transmit Packet Completion Pulse Interrupt (TX_PULSE)
          3. 24.11.4.5.3 Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
          4. 24.11.4.5.4 Miscellaneous Pulse Interrupt (MISC_PULSE)
            1. 24.11.4.5.4.1 EVNT_PEND( CPTS_PEND) Interrupt
            2. 24.11.4.5.4.2 Statistics Interrupt
            3. 24.11.4.5.4.3 Host Error interrupt
            4. 24.11.4.5.4.4 MDIO Interrupts
          5. 24.11.4.5.5 Interrupt Pacing
        6. 24.11.4.6  Reset Isolation
          1. 24.11.4.6.1 Reset Isolation Functional Description
        7. 24.11.4.7  Software Reset
        8. 24.11.4.8  CPSW_3G
          1. 24.11.4.8.1  CPDMA RX and TX Interfaces
            1. 24.11.4.8.1.1 Functional Operation
            2. 24.11.4.8.1.2 Receive DMA Interface
              1. 24.11.4.8.1.2.1 Receive DMA Host Configuration
              2. 24.11.4.8.1.2.2 Receive Channel Teardown
            3. 24.11.4.8.1.3 Transmit DMA Interface
              1. 24.11.4.8.1.3.1 Transmit DMA Host Configuration
              2. 24.11.4.8.1.3.2 Transmit Channel Teardown
            4. 24.11.4.8.1.4 Transmit Rate Limiting
            5. 24.11.4.8.1.5 Command IDLE
          2. 24.11.4.8.2  Address Lookup Engine (ALE)
            1. 24.11.4.8.2.1 Address Table Entry
              1. 24.11.4.8.2.1.1 Free Table Entry
              2. 24.11.4.8.2.1.2 Multicast Address Table Entry
              3. 24.11.4.8.2.1.3 VLAN/Multicast Address Table Entry
              4. 24.11.4.8.2.1.4 Unicast Address Table Entry
              5. 24.11.4.8.2.1.5 OUI Unicast Address Table Entry
              6. 24.11.4.8.2.1.6 VLAN/Unicast Address Table Entry
              7. 24.11.4.8.2.1.7 VLAN Table Entry
            2. 24.11.4.8.2.2 Packet Forwarding Processes
            3. 24.11.4.8.2.3 Learning Process
            4. 24.11.4.8.2.4 VLAN Aware Mode
            5. 24.11.4.8.2.5 VLAN Unaware Mode
          3. 24.11.4.8.3  Packet Priority Handling
          4. 24.11.4.8.4  FIFO Memory Control
          5. 24.11.4.8.5  FIFO Transmit Queue Control
            1. 24.11.4.8.5.1 Normal Priority Mode
            2. 24.11.4.8.5.2 Dual MAC Mode
            3. 24.11.4.8.5.3 Rate Limit Mode
          6. 24.11.4.8.6  Audio Video Bridging
            1. 24.11.4.8.6.1 IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
              1. 24.11.4.8.6.1.1 IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
              2. 24.11.4.8.6.1.2 IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
            2. 24.11.4.8.6.2 IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
              1. 24.11.4.8.6.2.1 Configuring the Device for 802.1Qav Operation:
          7. 24.11.4.8.7  Ethernet MAC Sliver (CPGMAC_SL)
            1. 24.11.4.8.7.1 G/MII Media Independent Interface
              1. 24.11.4.8.7.1.1 Data Reception
                1. 24.11.4.8.7.1.1.1 Receive Control
                2. 24.11.4.8.7.1.1.2 Receive Inter-Frame Interval
              2. 24.11.4.8.7.1.2 Data Transmission
                1. 24.11.4.8.7.1.2.1 Transmit Control
                2. 24.11.4.8.7.1.2.2 CRC Insertion
                3. 24.11.4.8.7.1.2.3 MTXER
                4. 24.11.4.8.7.1.2.4 Adaptive Performance Optimization (APO)
                5. 24.11.4.8.7.1.2.5 Inter-Packet-Gap Enforcement
                6. 24.11.4.8.7.1.2.6 Back Off
                7. 24.11.4.8.7.1.2.7 Programmable Transmit Inter-Packet Gap
                8. 24.11.4.8.7.1.2.8 Speed, Duplex and Pause Frame Support Negotiation
            2. 24.11.4.8.7.2 RMII Interface
              1. 24.11.4.8.7.2.1 Features
              2. 24.11.4.8.7.2.2 RMII Receive (RX)
              3. 24.11.4.8.7.2.3 RMII Transmit (TX)
            3. 24.11.4.8.7.3 RGMII Interface
              1. 24.11.4.8.7.3.1 RGMII Features
              2. 24.11.4.8.7.3.2 RGMII Receive (RX)
              3. 24.11.4.8.7.3.3 In-Band Mode of Operation
              4. 24.11.4.8.7.3.4 Forced Mode of Operation
              5. 24.11.4.8.7.3.5 RGMII Transmit (TX)
            4. 24.11.4.8.7.4 Frame Classification
          8. 24.11.4.8.8  Embedded Memories
          9. 24.11.4.8.9  Flow Control
            1. 24.11.4.8.9.1 CPPI Port Flow Control
            2. 24.11.4.8.9.2 Ethernet Port Flow Control
              1. 24.11.4.8.9.2.1 Receive Flow Control
                1. 24.11.4.8.9.2.1.1 Collision Based Receive Buffer Flow Control
                2. 24.11.4.8.9.2.1.2 IEEE 802.3X Based Receive Flow Control
              2. 24.11.4.8.9.2.2 Transmit Flow Control
          10. 24.11.4.8.10 Short Gap
          11. 24.11.4.8.11 Switch Latency
          12. 24.11.4.8.12 Emulation Control
          13. 24.11.4.8.13 FIFO Loopback
          14. 24.11.4.8.14 Device Level Ring (DLR) Support
          15. 24.11.4.8.15 Energy Efficient Ethernet Support (802.3az)
          16. 24.11.4.8.16 CPSW_3G Network Statistics
            1. 24.11.4.8.16.1 3522
        9. 24.11.4.9  Static Packet Filter (SPF)
          1. 24.11.4.9.1 SPF Overview
          2. 24.11.4.9.2 SPF Functional Description
            1. 24.11.4.9.2.1 SPF Block Diagram
            2. 24.11.4.9.2.2 Interrupts
            3. 24.11.4.9.2.3 Protocol Header Extractor
            4. 24.11.4.9.2.4 Programmable Rule Engine
              1. 24.11.4.9.2.4.1 Internal Registers
              2. 24.11.4.9.2.4.2 Packet Buffer
            5. 24.11.4.9.2.5 Intrusion Event Logger
            6. 24.11.4.9.2.6 Rate Limiter
            7. 24.11.4.9.2.7 Rule Engine Instruction Set Architecture
              1. 24.11.4.9.2.7.1 Instruction Format
              2. 24.11.4.9.2.7.2 Operand Field
              3. 24.11.4.9.2.7.3 Arithmetic/Logical Function Field
              4. 24.11.4.9.2.7.4 Operation Field
          3. 24.11.4.9.3 Programming Guide
            1. 24.11.4.9.3.1 Initialization Routine
            2. 24.11.4.9.3.2 Interrupt Service Routine
            3. 24.11.4.9.3.3 Rule Engine Example Program
        10. 24.11.4.10 Common Platform Time Sync (CPTS)
          1. 24.11.4.10.1 CPTS Architecture
          2. 24.11.4.10.2 CPTS Initialization
          3. 24.11.4.10.3 Time Stamp Value
          4. 24.11.4.10.4 Event FIFO
          5. 24.11.4.10.5 Time Sync Events
            1. 24.11.4.10.5.1 Time Stamp Push Event
            2. 24.11.4.10.5.2 Time Stamp Counter Rollover Event
            3. 24.11.4.10.5.3 Time Stamp Counter Half-rollover Event
            4. 24.11.4.10.5.4 Hardware Time Stamp Push Event
            5. 24.11.4.10.5.5 Ethernet Port Events
          6. 24.11.4.10.6 CPTS Interrupt Handling
        11. 24.11.4.11 CPPI Buffer Descriptors
          1. 24.11.4.11.1 TX Buffer Descriptors
            1. 24.11.4.11.1.1 CPPI TX Data Word 0
            2. 24.11.4.11.1.2 CPPI TX Data Word 1
            3. 24.11.4.11.1.3 CPPI TX Data Word 2
            4. 24.11.4.11.1.4 CPPI TX Data Word 3
          2. 24.11.4.11.2 RX Buffer Descriptors
            1. 24.11.4.11.2.1 CPPI RX Data Word 0
            2. 24.11.4.11.2.2 CPPI RX Data Word 1
            3. 24.11.4.11.2.3 CPPI RX Data Word 2
            4. 24.11.4.11.2.4 CPPI RX Data Word 3
        12. 24.11.4.12 MDIO
          1. 24.11.4.12.1 MDIO Frame Formats
          2. 24.11.4.12.2 MDIO Functional Description
      5. 24.11.5 GMAC_SW Programming Guide
        1. 24.11.5.1 Transmit Operation
        2. 24.11.5.2 Receive Operation
        3. 24.11.5.3 MDIO Software Interface
          1. 24.11.5.3.1 Initializing the MDIO Module
          2. 24.11.5.3.2 Writing Data To a PHY Register
          3. 24.11.5.3.3 Reading Data From a PHY Register
        4. 24.11.5.4 Initialization and Configuration of CPSW
      6. 24.11.6 GMAC_SW Register Manual
        1. 24.11.6.1  GMAC_SW Instance Summary
        2. 24.11.6.2  SS Registers
          1. 24.11.6.2.1 SS Register Summary
          2. 24.11.6.2.2 SS Register Description
        3. 24.11.6.3  PORT Registers
          1. 24.11.6.3.1 PORT Register Summary
          2. 24.11.6.3.2 PORT Register Description
        4. 24.11.6.4  CPDMA registers
          1. 24.11.6.4.1 CPDMA Register Summary
          2. 24.11.6.4.2 CPDMA Register Description
        5. 24.11.6.5  STATS Registers
          1. 24.11.6.5.1 STATS Register Summary
          2. 24.11.6.5.2 STATS Register Description
        6. 24.11.6.6  STATERAM Registers
          1. 24.11.6.6.1 STATERAM Register Summary
          2. 24.11.6.6.2 STATERAM Register Description
        7. 24.11.6.7  CPTS registers
          1. 24.11.6.7.1 CPTS Register Summary
          2. 24.11.6.7.2 CPTS Register Description
        8. 24.11.6.8  ALE registers
          1. 24.11.6.8.1 ALE Register Summary
          2. 24.11.6.8.2 ALE Register Description
        9. 24.11.6.9  SL registers
          1. 24.11.6.9.1 SL Register Summary
          2. 24.11.6.9.2 SL Register Description
        10. 24.11.6.10 MDIO registers
          1. 24.11.6.10.1 MDIO Register Summary
          2. 24.11.6.10.2 MDIO Register Description
        11. 24.11.6.11 WR registers
          1. 24.11.6.11.1 WR Register Summary
          2. 24.11.6.11.2 WR Register Description
        12. 24.11.6.12 SPF Registers
          1. 24.11.6.12.1 SPF Register Summary
          2. 24.11.6.12.2 SPF Register Description
    12. 24.12 Media Local Bus (MLB)
  27. 25eMMC/SD/SDIO
    1. 25.1 eMMC/SD/SDIO Overview
      1. 25.1.1 eMMC/SD/SDIO Features
    2. 25.2 eMMC/SD/SDIO Environment
      1. 25.2.1 eMMC/SD/SDIO Functional Modes
        1. 25.2.1.1 eMMC/SD/SDIO Connected to an eMMC, SD, or SDIO Card
      2. 25.2.2 Protocol and Data Format
        1. 25.2.2.1 Protocol
        2. 25.2.2.2 Data Format
    3. 25.3 eMMC/SD/SDIO Integration
    4. 25.4 eMMC/SD/SDIO Functional Description
      1. 25.4.1  Block Diagram
      2. 25.4.2  Resets
        1. 25.4.2.1 Hardware Reset
        2. 25.4.2.2 Software Reset
      3. 25.4.3  Power Management
      4. 25.4.4  Interrupt Requests
        1. 25.4.4.1 Interrupt-Driven Operation
        2. 25.4.4.2 Polling
        3. 25.4.4.3 Asynchronous Interrupt
      5. 25.4.5  DMA Modes
        1. 25.4.5.1 Master DMA Operations
          1. 25.4.5.1.1 Descriptor Table Description
          2. 25.4.5.1.2 Requirements for Descriptors
            1. 25.4.5.1.2.1 Data Length
            2. 25.4.5.1.2.2 Supported Features
            3. 25.4.5.1.2.3 Error Generation
          3. 25.4.5.1.3 Advanced DMA Description
        2. 25.4.5.2 Slave DMA Operations
          1. 25.4.5.2.1 DMA Receive Mode
          2. 25.4.5.2.2 DMA Transmit Mode
      6. 25.4.6  Mode Selection
      7. 25.4.7  Buffer Management
        1. 25.4.7.1 Data Buffer
          1. 25.4.7.1.1 Memory Size, Block Length, and Buffer-Management Relationship
          2. 25.4.7.1.2 Data Buffer Status
      8. 25.4.8  Transfer Process
        1. 25.4.8.1 Different Types of Commands
        2. 25.4.8.2 Different Types of Responses
      9. 25.4.9  Transfer or Command Status and Errors Reporting
        1. 25.4.9.1 Busy Time-Out for R1b, R5b Response Type
        2. 25.4.9.2 Busy Time-Out After Write CRC Status
        3. 25.4.9.3 Write CRC Status Time-Out
        4. 25.4.9.4 Read Data Time-Out
        5. 25.4.9.5 Boot Acknowledge Time-Out
      10. 25.4.10 Auto Command 12 Timings
        1. 25.4.10.1 Auto CMD12 Timings During Write Transfer
        2. 25.4.10.2 Auto CMD12 Timings During Read Transfer
      11. 25.4.11 Transfer Stop
      12. 25.4.12 Output Signals Generation
        1. 25.4.12.1 Generation on Falling Edge of MMC Clock
        2. 25.4.12.2 Generation on Rising Edge of MMC Clock
      13. 25.4.13 Sampling Clock Tuning
      14. 25.4.14 Card Boot Mode Management
        1. 25.4.14.1 Boot Mode Using CMD0
        2. 25.4.14.2 Boot Mode With CMD Line Tied to 0
      15. 25.4.15 MMC CE-ATA Command Completion Disable Management
      16. 25.4.16 Test Registers
      17. 25.4.17 eMMC/SD/SDIO Hardware Status Features
    5. 25.5 eMMC/SD/SDIO Programming Guide
      1. 25.5.1 Low-Level Programming Models
        1. 25.5.1.1 Global Initialization
          1. 25.5.1.1.1 Surrounding Modules Global Initialization
          2. 25.5.1.1.2 eMMC/SD/SDIO Host Controller Initialization Flow
            1. 25.5.1.1.2.1 Enable Interface and Functional Clock for MMC Controller
            2. 25.5.1.1.2.2 MMCHS Soft Reset Flow
            3. 25.5.1.1.2.3 Set MMCHS Default Capabilities
            4. 25.5.1.1.2.4 Wake-Up Configuration
            5. 25.5.1.1.2.5 MMC Host and Bus Configuration
        2. 25.5.1.2 Operational Modes Configuration
          1. 25.5.1.2.1 Basic Operations for eMMC/SD/SDIO Host Controller
            1. 25.5.1.2.1.1 Card Detection, Identification, and Selection
              1. 25.5.1.2.1.1.1 CMD Line Reset Procedure
            2. 25.5.1.2.1.2 Read/Write Transfer Flow in DMA Mode With Interrupt
              1. 25.5.1.2.1.2.1 DATA Lines Reset Procedure
            3. 25.5.1.2.1.3 Read/Write Transfer Flow in DMA Mode With Polling
            4. 25.5.1.2.1.4 Read/Write Transfer Flow Without DMA With Polling
            5. 25.5.1.2.1.5 Read/Write Transfer Flow in CE-ATA Mode
            6. 25.5.1.2.1.6 Suspend-Resume Flow
              1. 25.5.1.2.1.6.1 Suspend Flow
              2. 25.5.1.2.1.6.2 Resume Flow
            7. 25.5.1.2.1.7 Basic Operations – Steps Detailed
              1. 25.5.1.2.1.7.1 Command Transfer Flow
              2. 25.5.1.2.1.7.2 MMCHS Clock Frequency Change
              3. 25.5.1.2.1.7.3 Bus Width Selection
          2. 25.5.1.2.2 Bus Voltage Selection
          3. 25.5.1.2.3 Boot Mode Configuration
            1. 25.5.1.2.3.1 Boot Using CMD0
            2. 25.5.1.2.3.2 Boot With CMD Line Tied to 0
          4. 25.5.1.2.4 SDR104/HS200 DLL Tuning Procedure
    6. 25.6 eMMC/SD/SDIO Register Manual
      1. 25.6.1 eMMC/SD/SDIO Instance Summary
      2. 25.6.2 eMMC/SD/SDIO Registers
        1. 25.6.2.1 eMMC/SD/SDIO Register Summary
        2. 25.6.2.2 eMMC/SD/SDIO Register Description
  28. 26Shared PHY Component Subsystem
    1. 26.1 SATA PHY Subsystem
      1. 26.1.1 SATA PHY Subsystem Overview
      2. 26.1.2 SATA PHY Subsystem Environment
        1. 26.1.2.1 SATA PHY I/O Signals
      3. 26.1.3 SATA PHY Subsystem Integration
      4. 26.1.4 SATA PHY Subsystem Functional Description
        1. 26.1.4.1 SATA PLL Controller L4 Interface Adapter Functional Description
        2. 26.1.4.2 SATA PHY Serializer and Deserializer Functional Descriptions
          1. 26.1.4.2.1 SATA PHY Reset
          2. 26.1.4.2.2 SATA_PHY Clocking
            1. 26.1.4.2.2.1 SATA_PHY Input Clocks
            2. 26.1.4.2.2.2 SATA_PHY Output Clocks
          3. 26.1.4.2.3 SATA_PHY Power Management
            1. 26.1.4.2.3.1 SATA_PHY Power-Up/-Down Sequences
            2. 26.1.4.2.3.2 SATA_PHY Low-Power Modes
          4. 26.1.4.2.4 SATA_PHY Hardware Requests
        3. 26.1.4.3 SATA Clock Generator Subsystem Functional Description
          1. 26.1.4.3.1 SATA DPLL Clock Generator Overview
          2. 26.1.4.3.2 SATA DPLL Clock Generator Reset
          3. 26.1.4.3.3 SATA DPLL Low-Power Modes
          4. 26.1.4.3.4 SATA DPLL Clocks Configuration
            1. 26.1.4.3.4.1 SATA DPLL Input Clock Control
            2. 26.1.4.3.4.2 SATA DPLL Output Clock Configuration
              1. 26.1.4.3.4.2.1 SATA DPLL Output Clock Gating
          5. 26.1.4.3.5 SATA DPLL Subsystem Architecture
          6. 26.1.4.3.6 SATA DPLL Clock Generator Modes and State Transitions
            1. 26.1.4.3.6.1 SATA Clock Generator Power Up
            2. 26.1.4.3.6.2 SATA DPLL Sequences
            3. 26.1.4.3.6.3 SATA DPLL Locked Mode
            4. 26.1.4.3.6.4 SATA DPLL Idle-Bypass Mode
            5. 26.1.4.3.6.5 SATA DPLL MN-Bypass Mode
            6. 26.1.4.3.6.6 SATA DPLL Error Conditions
          7. 26.1.4.3.7 SATA PLL Controller Functions
            1. 26.1.4.3.7.1 SATA PLL Controller Register Access
            2. 26.1.4.3.7.2 SATA DPLL Clock Programming Sequence
            3. 26.1.4.3.7.3 SATA DPLL Recommended Values
      5. 26.1.5 SATA PHY Subsystem Low-Level Programming Model
    2. 26.2 USB3_PHY Subsystem
      1. 26.2.1 USB3_PHY Subsystem Overview
      2. 26.2.2 USB3_PHY Subsystem Environment
        1. 26.2.2.1 USB3_PHY I/O Signals
      3. 26.2.3 USB3_PHY Subsystem Integration
      4. 26.2.4 USB3_PHY Subsystem Functional Description
        1. 26.2.4.1 Super-Speed USB PLL Controller L4 Interface Adapter Functional Description
        2. 26.2.4.2 USB3_PHY Serializer and Deserializer Functional Descriptions
          1. 26.2.4.2.1 USB3_PHY Module Resets
            1. 26.2.4.2.1.1 Hardware Reset
            2. 26.2.4.2.1.2 Software Reset
          2. 26.2.4.2.2 USB3_PHY Subsystem Clocking
            1. 26.2.4.2.2.1 USB3_PHY Subsystem Input Clocks
            2. 26.2.4.2.2.2 USB3_PHY Subsystem Output Clocks
          3. 26.2.4.2.3 USB3_PHY Power Management
            1. 26.2.4.2.3.1 USB3_PHY Power-Up/-Down Sequences
            2. 26.2.4.2.3.2 USB3_PHY Low-Power Modes
            3. 26.2.4.2.3.3 Clock Gating
          4. 26.2.4.2.4 USB3_PHY Hardware Requests
        3. 26.2.4.3 USB3_PHY Clock Generator Subsystem Functional Description
          1. 26.2.4.3.1 USB3_PHY DPLL Clock Generator Overview
          2. 26.2.4.3.2 USB3_PHY DPLL Clock Generator Reset
          3. 26.2.4.3.3 USB3_PHY DPLL Low-Power Modes
          4. 26.2.4.3.4 USB3_PHY DPLL Clocks Configuration
            1. 26.2.4.3.4.1 USB3_PHY DPLL Input Clock Control
            2. 26.2.4.3.4.2 USB3_PHY DPLL Output Clock Configuration
              1. 26.2.4.3.4.2.1 USB3_PHY DPLL Output Clock Gating
          5. 26.2.4.3.5 USB3_PHY DPLL Subsystem Architecture
          6. 26.2.4.3.6 USB3_PHY DPLL Clock Generator Modes and State Transitions
            1. 26.2.4.3.6.1 USB3_PHY Clock Generator Power Up
            2. 26.2.4.3.6.2 USB3_PHY DPLL Sequences
            3. 26.2.4.3.6.3 USB3_PHY DPLL Locked Mode
            4. 26.2.4.3.6.4 USB3_PHY DPLL Idle-Bypass Mode
            5. 26.2.4.3.6.5 USB3_PHY DPLL MN-Bypass Mode
            6. 26.2.4.3.6.6 USB3_PHY DPLL Error Conditions
          7. 26.2.4.3.7 USB3_PHY PLL Controller Functions
            1. 26.2.4.3.7.1 USB3_PHY PLL Controller Register Access
            2. 26.2.4.3.7.2 3783
            3. 26.2.4.3.7.3 USB3_PHY DPLL Clock Programming Sequence
            4. 26.2.4.3.7.4 USB3_PHY DPLL Recommended Values
      5. 26.2.5 USB3_PHY Subsystem Low-Level Programming Model
    3. 26.3 USB3 PHY and SATA PHY Register Manual
      1. 26.3.1 USB3 PHY and SATA PHY Instance Summary
      2. 26.3.2 USB3_PHY_RX Registers
        1. 26.3.2.1 USB3_PHY_RX Register Summary
        2. 26.3.2.2 USB3_PHY_RX Register Description
      3. 26.3.3 USB3_PHY_TX Registers
        1. 26.3.3.1 USB3_PHY_TX Register Summary
        2. 26.3.3.2 USB3_PHY_TX Register Description
      4. 26.3.4 SATA_PHY_RX Registers
        1. 26.3.4.1 SATA_PHY_RX Register Summary
        2. 26.3.4.2 SATA_PHY_RX Register Description
      5. 26.3.5 SATA_PHY_TX Registers
        1. 26.3.5.1 SATA_PHY_TX Register Summary
        2. 26.3.5.2 SATA_PHY_TX Register Description
      6. 26.3.6 DPLLCTRL Registers
        1. 26.3.6.1 DPLLCTRL Register Summary
        2. 26.3.6.2 DPLLCTRL Register Description
    4. 26.4 PCIe PHY Subsystem
      1. 26.4.1 PCIe PHY Subsystem Overview
        1. 26.4.1.1 PCIe PHY Subsystem Key Features
      2. 26.4.2 PCIe PHY Subsystem Environment
        1. 26.4.2.1 PCIe PHY I/O Signals
      3. 26.4.3 PCIe Shared PHY Subsystem Integration
      4. 26.4.4 PCIe PHY Subsystem Functional Description
        1. 26.4.4.1 PCIe PHY Subsystem Block Diagram
        2. 26.4.4.2 OCP2SCP Functional Description
          1. 26.4.4.2.1 OCP2SCP Reset
            1. 26.4.4.2.1.1 Hardware Reset
            2. 26.4.4.2.1.2 Software Reset
          2. 26.4.4.2.2 OCP2SCP Power Management
            1. 26.4.4.2.2.1 Idle Mode
            2. 26.4.4.2.2.2 Clock Gating
          3. 26.4.4.2.3 OCP2SCP Timing Registers
        3. 26.4.4.3 PCIe PHY Serializer and Deserializer Functional Descriptions
          1. 26.4.4.3.1 PCIe PHY Module Resets
            1. 26.4.4.3.1.1 Hardware Reset
            2. 26.4.4.3.1.2 Software Reset
          2. 26.4.4.3.2 PCIe PHY Subsystem Clocking
            1. 26.4.4.3.2.1 PCIe PHY Subsystem Input Clocks
            2. 26.4.4.3.2.2 PCIe PHY Subsystem Output Clocks
          3. 26.4.4.3.3 PCIe PHY Power Management
            1. 26.4.4.3.3.1 PCIe PHY Power-Up/-Down Sequences
            2. 26.4.4.3.3.2 PCIe PHY Low-Power Modes
            3. 26.4.4.3.3.3 Clock Gating
          4. 26.4.4.3.4 PCIe PHY Hardware Requests
        4. 26.4.4.4 PCIe PHY Clock Generator Subsystem Functional Description
          1. 26.4.4.4.1 PCIe PHY DPLL Clock Generator
            1. 26.4.4.4.1.1 PCIe PHY DPLL Clock Generator Overview
            2. 26.4.4.4.1.2 PCIe PHY DPLL Clock Generator Reset
            3. 26.4.4.4.1.3 PCIe PHY DPLL Low-Power Modes
            4. 26.4.4.4.1.4 PCIe PHY DPLL Clocks Configuration
              1. 26.4.4.4.1.4.1 PCIe PHY DPLL Input Clock Control
              2. 26.4.4.4.1.4.2 PCIe PHY DPLL Output Clock Configuration
                1. 26.4.4.4.1.4.2.1 PCIe PHY DPLL Output Clock Gating
            5. 26.4.4.4.1.5 PCIe PHY DPLL Subsystem Architecture
            6. 26.4.4.4.1.6 PCIe PHY DPLL Clock Generator Modes and State Transitions
              1. 26.4.4.4.1.6.1 PCIe PHY Clock Generator Power Up
              2. 26.4.4.4.1.6.2 PCIe PHY DPLL Sequences
              3. 26.4.4.4.1.6.3 PCIe PHY DPLL Locked Mode
              4. 26.4.4.4.1.6.4 PCIe PHY DPLL Idle-Bypass Mode
              5. 26.4.4.4.1.6.5 PCIe PHY DPLL Low Power Stop Mode
              6. 26.4.4.4.1.6.6 PCIe PHY DPLL Clock Programming Sequence
              7. 26.4.4.4.1.6.7 PCIe PHY DPLL Recommended Values
          2. 26.4.4.4.2 PCIe PHY APLL Clock Generator
            1. 26.4.4.4.2.1 PCIe PHY APLL Clock Generator Overview
            2. 26.4.4.4.2.2 PCIe PHY APLL Clock Generator Reset
            3. 26.4.4.4.2.3 PCIe PHY APLL Low-Power Mode
            4. 26.4.4.4.2.4 PCIe PHY APLL Clocks Configuration
              1. 26.4.4.4.2.4.1 PCIe PHY APLL Input Clock Control
              2. 26.4.4.4.2.4.2 PCIe PHY APLL Output Clock Configuration
                1. 26.4.4.4.2.4.2.1 PCIe PHY APLL Output Clock Gating
            5. 26.4.4.4.2.5 PCIe PHY APLL Subsystem Architecture
            6. 26.4.4.4.2.6 PCIe PHY APLL Clock Generator Modes and State Transitions
              1. 26.4.4.4.2.6.1 PCIe PHY APLL Clock Generator Power Up
              2. 26.4.4.4.2.6.2 PCIe PHY APLL Sequences
              3. 26.4.4.4.2.6.3 PCIe PHY APLL Locked Mode
          3. 26.4.4.4.3 ACSPCIE reference clock buffer
      5. 26.4.5 PCIePHY Subsystem Low-Level Programming Model
      6. 26.4.6 PCIe PHY Subsystem Register Manual
        1. 26.4.6.1 PCIe PHY Instance Summary
          1. 26.4.6.1.1 PCIe_PHY_RX Registers
            1. 26.4.6.1.1.1 PCIe_PHY_RX Register Summary
            2. 26.4.6.1.1.2 PCIe_PHY_RX Register Description
          2. 26.4.6.1.2 PCIe_PHY_TX Registers
            1. 26.4.6.1.2.1 PCIe_PHY_TX Register Summary
            2. 26.4.6.1.2.2 PCIe_PHY_TX Register Description
          3. 26.4.6.1.3 OCP2SCP Registers
            1. 26.4.6.1.3.1 OCP2SCP Register Summary
            2. 26.4.6.1.3.2 OCP2SCP Register Description
  29. 27General-Purpose Interface
    1. 27.1 General-Purpose Interface Overview
    2. 27.2 General-Purpose Interface Environment
      1. 27.2.1 General-Purpose Interface as a Keyboard Interface
      2. 27.2.2 General-Purpose Interface Signals
    3. 27.3 General-Purpose Interface Integration
    4. 27.4 General-Purpose Interface Functional Description
      1. 27.4.1 General-Purpose Interface Block Diagram
      2. 27.4.2 General-Purpose Interface Interrupt and Wake-Up Features
        1. 27.4.2.1 Synchronous Path: Interrupt Request Generation
        2. 27.4.2.2 Asynchronous Path: Wake-Up Request Generation
        3. 27.4.2.3 Wake-Up Event Conditions During Transition To/From IDLE State
        4. 27.4.2.4 Interrupt (or Wake-Up) Line Release
      3. 27.4.3 General-Purpose Interface Clock Configuration
        1. 27.4.3.1 Clocking
      4. 27.4.4 General-Purpose Interface Hardware and Software Reset
      5. 27.4.5 General-Purpose Interface Power Management
        1. 27.4.5.1 Power Domain
        2. 27.4.5.2 Power Management
          1. 27.4.5.2.1 Idle Scheme
          2. 27.4.5.2.2 Operating Modes
          3. 27.4.5.2.3 System Power Management and Wakeup
          4. 27.4.5.2.4 Module Power Saving
      6. 27.4.6 General-Purpose Interface Interrupt and Wake-Up Requests
        1. 27.4.6.1 Interrupt Requests Generation
        2. 27.4.6.2 Wake-Up Requests Generation
      7. 27.4.7 General-Purpose Interface Channels Description
      8. 27.4.8 General-Purpose Interface Data Input/Output Capabilities
      9. 27.4.9 General-Purpose Interface Set-and-Clear Protocol
        1. 27.4.9.1 Description
        2. 27.4.9.2 Clear Instruction
          1. 27.4.9.2.1 Clear Register Addresses
          2. 27.4.9.2.2 Clear Instruction Example
        3. 27.4.9.3 Set Instruction
          1. 27.4.9.3.1 Set Register Addresses
          2. 27.4.9.3.2 Set Instruction Example
    5. 27.5 General-Purpose Interface Programming Guide
      1. 27.5.1 General-Purpose Interface Low-Level Programming Models
        1. 27.5.1.1 Global Initialization
          1. 27.5.1.1.1 Surrounding Modules Global Initialization
          2. 27.5.1.1.2 General-Purpose Interface Module Global Initialization
        2. 27.5.1.2 General-Purpose Interface Operational Modes Configuration
          1. 27.5.1.2.1 General-Purpose Interface Read Input Register
          2. 27.5.1.2.2 General-Purpose Interface Set Bit Function
          3. 27.5.1.2.3 General-Purpose Interface Clear Bit Function
    6. 27.6 General-Purpose Interface Register Manual
      1. 27.6.1 General-Purpose Interface Instance Summary
      2. 27.6.2 General-Purpose Interface Registers
        1. 27.6.2.1 General-Purpose Interface Register Summary
        2. 27.6.2.2 General-Purpose Interface Register Description
  30. 28Keyboard Controller
    1. 28.1 Keyboard Controller Overview
    2. 28.2 Keyboard Controller Environment
      1. 28.2.1 Keyboard Controller Functions/Modes
      2. 28.2.2 Keyboard Controller Signals
      3. 28.2.3 Protocols and Data Formats
    3. 28.3 Keyboard Controller Integration
    4. 28.4 Keyboard Controller Functional Description
      1. 28.4.1 Keyboard Controller Block Diagram
      2. 28.4.2 Keyboard Controller Software Reset
      3. 28.4.3 Keyboard Controller Power Management
      4. 28.4.4 Keyboard Controller Interrupt Requests
      5. 28.4.5 Keyboard Controller Software Mode
      6. 28.4.6 Keyboard Controller Hardware Decoding Modes
        1. 28.4.6.1 Functional Modes
        2. 28.4.6.2 Keyboard Controller Timer
        3. 28.4.6.3 State-Machine Status
        4. 28.4.6.4 Keyboard Controller Interrupt Generation
          1. 28.4.6.4.1 Interrupt-Generation Scheme
          2. 28.4.6.4.2 Keyboard Buffer and Missed Events (Overrun Feature)
      7. 28.4.7 Keyboard Controller Key Coding Registers
      8. 28.4.8 Keyboard Controller Register Access
        1. 28.4.8.1 Write Registers Access
        2. 28.4.8.2 Read Registers Access
    5. 28.5 Keyboard Controller Programming Guide
      1. 28.5.1 Keyboard Controller Low-Level Programming Models
        1. 28.5.1.1 Global Initialization
          1. 28.5.1.1.1 Surrounding Modules Global Initialization
          2. 28.5.1.1.2 Keyboard Controller Global Initialization
            1. 28.5.1.1.2.1 Main Sequence – Keyboard Controller Global Initialization
        2. 28.5.1.2 Operational Modes Configuration
          1. 28.5.1.2.1 Keyboard Controller in Hardware Decoding Mode (Default Mode)
            1. 28.5.1.2.1.1 Main Sequence – Keyboard Controller Hardware Mode
          2. 28.5.1.2.2 Keyboard Controller Software Scanning Mode
            1. 28.5.1.2.2.1 Main Sequence – Keyboard Controller Software Mode
          3. 28.5.1.2.3 Using the Timer
          4. 28.5.1.2.4 State-Machine Status Register
        3. 28.5.1.3 Keyboard Controller Events Servicing
    6. 28.6 Keyboard Controller Register Manual
      1. 28.6.1 Keyboard Controller Instance Summary
      2. 28.6.2 Keyboard Controller Registers
        1. 28.6.2.1 Keyboard Controller Register Summary
        2. 28.6.2.2 Keyboard Controller Register Description
  31. 29Pulse-Width Modulation Subsystem
    1. 29.1 PWM Subsystem Resources
      1. 29.1.1 PWMSS Overview
        1. 29.1.1.1 PWMSS Key Features
        2. 29.1.1.2 PWMSS Unsupported Fetaures
      2. 29.1.2 PWMSS Environment
        1. 29.1.2.1 PWMSS I/O Interface
      3. 29.1.3 PWMSS Integration
        1. 29.1.3.1 PWMSS Module Interfaces Implementation
          1. 29.1.3.1.1 Device Specific PWMSS Features
          2. 29.1.3.1.2 Daisy-Chain Connectivity between PWMSS Modules
          3. 29.1.3.1.3 eHRPWM Modules Time Base Clock Gating
      4. 29.1.4 PWMSS Subsystem Power, Reset and Clock Configuration
        1. 29.1.4.1 PWMSS Local Clock Management
        2. 29.1.4.2 PWMSS Modules Local Clock Gating
        3. 29.1.4.3 PWMSS Software Reset
      5. 29.1.5 PWMSS_CFG Register Manual
        1. 29.1.5.1 PWMSS_CFG Instance Summary
        2. 29.1.5.2 PWMSS_CFG Registers
          1. 29.1.5.2.1 PWMSS_CFG Register Summary
          2. 29.1.5.2.2 PWMSS_CFG Register Description
    2. 29.2 Enhanced PWM (ePWM) Module
    3. 29.3 Enhanced Capture (eCAP) Module
    4. 29.4 Enhanced Quadrature Encoder Pulse (eQEP) Module
  32. 30Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem
    1. 30.1  PRU-ICSS Overview
      1. 30.1.1 PRU-ICSS Key Features
    2. 30.2  PRU-ICSS Environment
      1. 30.2.1 PRU-ICSS I/O Interface
    3. 30.3  PRU-ICSS Integration
    4. 30.4  PRU-ICSS Level Resources Functional Description
      1. 30.4.1 PRU-ICSS Reset Management
      2. 30.4.2 PRU-ICSS Power and Clock Management
        1. 30.4.2.1 PRU-ICSS Idle and Standby States
        2. 30.4.2.2 Module Clock Configurations at PRU-ICSS Top Level
      3. 30.4.3 Other PRU-ICSS Module Functional Registers at Subsystem Level
      4. 30.4.4 PRU-ICSS Memory Maps
        1. 30.4.4.1 PRU-ICSS Local Memory Map
          1. 30.4.4.1.1 PRU-ICSS Local Instruction Memory Map
          2. 30.4.4.1.2 PRU-ICSS Local Data Memory Map
        2. 30.4.4.2 PRU-ICSS Global Memory Map
      5. 30.4.5 PRUSS_CFG Register Manual
        1. 30.4.5.1 PRUSS_CFG Instance Summary
        2. 30.4.5.2 PRUSS_CFG Registers
          1. 30.4.5.2.1 PRUSS_CFG Register Summary
          2. 30.4.5.2.2 PRUSS_CFG Register Description
    5. 30.5  PRU-ICSS PRU Cores
    6. 30.6  PRU-ICSS Local Interrupt Controller
      1. 30.6.1 PRU-ICSS Interrupt Controller Overview
      2. 30.6.2 PRU-ICSS Interrupt Controller Functional Description
        1. 30.6.2.1 PRU-ICSS Interrupt Controller System Events
        2. 30.6.2.2 PRU-ICSS Interrupt Controller System Events Flow
          1. 30.6.2.2.1 PRU-ICSS Interrupt Processing
            1. 30.6.2.2.1.1 PRU-ICSS Interrupt Enabling
          2. 30.6.2.2.2 PRU-ICSS Interrupt Status Checking
          3. 30.6.2.2.3 PRU-ICSS Interrupt Channel Mapping
            1. 30.6.2.2.3.1 PRU-ICSS Host Interrupt Mapping
            2. 30.6.2.2.3.2 PRU-ICSS Interrupt Prioritization
          4. 30.6.2.2.4 PRU-ICSS Interrupt Nesting
          5. 30.6.2.2.5 PRU-ICSS Interrupt Status Clearing
        3. 30.6.2.3 PRU-ICSS Interrupt Disabling
      3. 30.6.3 PRU-ICSS Interrupt Controller Basic Programming Model
      4. 30.6.4 PRU-ICSS Interrupt Requests Mapping
      5. 30.6.5 PRU-ICSS Interrupt Controller Register Manual
        1. 30.6.5.1 PRUSS_INTC Instance Summary
        2. 30.6.5.2 PRUSS_INTC Registers
          1. 30.6.5.2.1 PRUSS_INTC Register Summary
          2. 30.6.5.2.2 PRUSS_INTC Register Description
    7. 30.7  PRU-ICSS UART Module
      1. 30.7.1 PRU-ICSS UART Module Overview
        1. 30.7.1.1 Purpose of the PRU-ICSS integrated UART Peripheral
        2. 30.7.1.2 PRU-ICSS UART Key Features
          1. 30.7.1.2.1 PRU-ICSS UART Module Industry Standard Compliance Statement
      2. 30.7.2 PRU-ICSS UART Environment
        1. 30.7.2.1 PRU-ICSS UART Pin Multiplexing
        2. 30.7.2.2 PRU-ICSS UART Signal Descriptions
        3. 30.7.2.3 PRU-ICSS UART Data Format and Protocol Description
          1. 30.7.2.3.1 PRU-ICSS UART Transmission Protocol
          2. 30.7.2.3.2 PRU-ICSS UART Reception Protocol
          3. 30.7.2.3.3 PRU-ICSS UART Data Format
            1. 30.7.2.3.3.1 Frame Formatting
        4. 30.7.2.4 PRU-ICSS UART Clock Generation and Control
      3. 30.7.3 PRU-ICSS UART Module Functional Description
        1. 30.7.3.1 PRU-ICSS UART Functional Block Diagram
        2. 30.7.3.2 PRU-ICSS UART Reset Considerations
          1. 30.7.3.2.1 PRU-ICSS UART Software Reset Considerations
          2. 30.7.3.2.2 PRU-ICSS UART Hardware Reset Considerations
        3. 30.7.3.3 PRU-ICSS UART Power Management
        4. 30.7.3.4 PRU-ICSS UART Interrupt Support
          1. 30.7.3.4.1 PRU-ICSS UART Interrupt Events and Requests
          2. 30.7.3.4.2 PRU-ICSS UART Interrupt Multiplexing
          3. 30.7.3.4.3 4060
        5. 30.7.3.5 4061
        6. 30.7.3.6 PRU-ICSS UART DMA Event Support
        7. 30.7.3.7 PRU-ICSS UART Operations
          1. 30.7.3.7.1 PRU-ICSS UART Transmission
          2. 30.7.3.7.2 PRU-ICSS UART Reception
          3. 30.7.3.7.3 PRU-ICSS UART FIFO Modes
            1. 30.7.3.7.3.1 PRU-ICSS UART FIFO Interrupt Mode
            2. 30.7.3.7.3.2 PRU-ICSS UART FIFO Poll Mode
          4. 30.7.3.7.4 PRU-ICSS UART Autoflow Control
            1. 30.7.3.7.4.1 PRU-ICSS UART Signal UART0_RTS Behavior
            2. 30.7.3.7.4.2 PRU-ICSS UART Signal PRUSS_UART0_CTS Behavior
          5. 30.7.3.7.5 PRU-ICSS UART Loopback Control
        8. 30.7.3.8 PRU-ICSS UART Initialization
        9. 30.7.3.9 PRU-ICSS UART Exception Processing
          1. 30.7.3.9.1 PRU-ICSS UART Divisor Latch Not Programmed
          2. 30.7.3.9.2 Changing Operating Mode During Busy Serial Communication of PRU-ICSS UART
      4. 30.7.4 PRUSS_UART Register Manual
        1. 30.7.4.1 PRUSS_UART Instance Summary
        2. 30.7.4.2 PRUSS_UART Registers
          1. 30.7.4.2.1 PRUSS_UART Register Summary
          2. 30.7.4.2.2 PRUSS_UART Register Description
    8. 30.8  PRU-ICSS eCAP Module
      1. 30.8.1 4083
      2. 30.8.2 PRU-ICSS eCAP Functional Description
      3. 30.8.3 PRUSS_ECAP Register Manual
        1. 30.8.3.1 PRUSS_ECAP Instance Summary
        2. 30.8.3.2 PRUSS_ECAP Registers
          1. 30.8.3.2.1 PRUSS_ECAP Register Summary
          2. 30.8.3.2.2 PRUSS_ECAP Register Description
    9. 30.9  PRU-ICSS MII RT Module
      1. 30.9.1 Introduction
        1. 30.9.1.1 Features
        2. 30.9.1.2 Unsupported Features
        3. 30.9.1.3 Block Diagram
      2. 30.9.2 Functional Description
        1. 30.9.2.1 Data Path Configuration
          1. 30.9.2.1.1 Auto-forward with Optional PRU Snoop
          2. 30.9.2.1.2 8- or 16-bit Processing with On-the-Fly Modifications
          3. 30.9.2.1.3 32-byte Double Buffer or Ping-Pong Processing
        2. 30.9.2.2 Definition and Terms
          1. 30.9.2.2.1 Data Frame Structure
          2. 30.9.2.2.2 PRU R30 and R31
          3. 30.9.2.2.3 RX and TX L1 FIFO Data Movement
          4. 30.9.2.2.4 CRC Computation
            1. 30.9.2.2.4.1 Receive CRC Computation
            2. 30.9.2.2.4.2 Transmit CRC Computation
        3. 30.9.2.3 RX MII Interface
          1. 30.9.2.3.1 RX MII Submodule Overview
            1. 30.9.2.3.1.1 Receive Data Latch
              1. 30.9.2.3.1.1.1 Start of Frame Detection
              2. 30.9.2.3.1.1.2 CRC Error Detection
              3. 30.9.2.3.1.1.3 RX Error Detection and Action
            2. 30.9.2.3.1.2 RX Data Path Options to PRU
              1. 30.9.2.3.1.2.1 RX MII Port → RX L1 FIFO → PRU
              2. 30.9.2.3.1.2.2 RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU
        4. 30.9.2.4 TX MII Interface
          1. 30.9.2.4.1 TX Data Path Options to TX L1 FIFO
            1. 30.9.2.4.1.1 PRU → TX L1 FIFO → TX MII Port
            2. 30.9.2.4.1.2 RX L1 FIFO → TX L1 FIFO → TX MII Port
        5. 30.9.2.5 PRU R31 Command Interface
        6. 30.9.2.6 Other Configuration Options
          1. 30.9.2.6.1 Nibble and Byte Order
          2. 30.9.2.6.2 Preamble Source
          3. 30.9.2.6.3 PRU and MII Port Multiplexer
            1. 30.9.2.6.3.1 Receive Multiplexer
            2. 30.9.2.6.3.2 Transmit Multiplexer
          4. 30.9.2.6.4 RX L2 Scratch Pad
      3. 30.9.3 PRU-ICSS MII RT Module Register Manual
        1. 30.9.3.1 PRUSS_MII_RT Instance Summary
        2. 30.9.3.2 PRUSS_MII_RT Registers
          1. 30.9.3.2.1 PRUSS_MII_RT Register Summary
          2. 30.9.3.2.2 PRUSS_MII_RT Register Description
    10. 30.10 PRU-ICSS MII MDIO Module
      1. 30.10.1 PRU-ICSS MII MDIO Overview
      2. 30.10.2 PRU-ICSS MII MDIO Functional Description
        1. 30.10.2.1 MII MDIO Management Interface Frame Formats
        2. 30.10.2.2 PRU-ICSS MII MDIO Interractions
        3. 30.10.2.3 PRU-ICSS MII MDIO Interrupts
      3. 30.10.3 PRU-ICSS MII MDIO Receive/Transmit Frame Host Software Interface
      4. 30.10.4 PRU-ICSS MII MDIO Module Register Manual
        1. 30.10.4.1 PRUSS_MII_MDIO Instance Summary
        2. 30.10.4.2 PRUSS_MII_MDIO Registers
          1. 30.10.4.2.1 PRUSS_MII_MDIO Register Summary
          2. 30.10.4.2.2 PRUSS_MII_MDIO Register Description
    11. 30.11 PRU-ICSS Industrial Ethernet Peripheral (IEP)
      1. 30.11.1 PRU-ICSS IEP Overview
      2. 30.11.2 PRU-ICSS IEP Functional Description
        1. 30.11.2.1 PRU-ICSS IEP Clock Generation
        2. 30.11.2.2 PRU-ICSS Industrial Ethernet Timer
          1. 30.11.2.2.1 PRU-ICSS Industrial Ethernet Timer Features
          2. 30.11.2.2.2 Industrial Ethernet Mapping
          3. 30.11.2.2.3 PRU-ICSS Industrial Ethernet Timer Basic Programming Sequence
        3. 30.11.2.3 PRU-ICSS IEP Sync0/Sync1 Signals Generation
          1. 30.11.2.3.1 PRU-ICSS IEP Sync0/Sync1 Features
          2. 30.11.2.3.2 PRU-ICSS IEP Sync0/Sync1 Generation Modes
        4. 30.11.2.4 PRU-ICSS Industrial Ethernet WatchDog
          1. 30.11.2.4.1 Features
        5. 30.11.2.5 PRU-ICSS Industrial Ethernet Digital IOs
          1. 30.11.2.5.1 Features
          2. 30.11.2.5.2 4160
          3. 30.11.2.5.3 DIGIO Block Diagrams
          4. 30.11.2.5.4 Basic Programming Model
      3. 30.11.3 PRUSS_IEP Register Manual
        1. 30.11.3.1 PRUSS_IEP Instance Summary
        2. 30.11.3.2 PRUSS_IEP Registers
          1. 30.11.3.2.1 PRUSS_IEP Register Summary
          2. 30.11.3.2.2 PRUSS_IEP Register Description
  33. 31Viterbi-Decoder Coprocessor
  34. 32Audio Tracking Logic
  35. 33Initialization
    1. 33.1 Initialization Overview
      1. 33.1.1 Terminology
      2. 33.1.2 Initialization Process
    2. 33.2 Preinitialization
      1. 33.2.1 Power Requirements
      2. 33.2.2 Boot Device Conditions
      3. 33.2.3 Clock, Reset, and Control
        1. 33.2.3.1 Overview
        2. 33.2.3.2 Clocking Scheme
        3. 33.2.3.3 Reset Configuration
          1. 33.2.3.3.1 ON/OFF Interconnect and Power-On-Reset
          2. 33.2.3.3.2 Warm Reset
          3. 33.2.3.3.3 Peripheral Reset by GPIO
          4. 33.2.3.3.4 Warm Reset Impact on GPIOs
        4. 33.2.3.4 PMIC Control
        5. 33.2.3.5 PMIC Request Signals
      4. 33.2.4 Sysboot Configuration
        1. 33.2.4.1 GPMC Configuration for XIP/NAND
        2. 33.2.4.2 System Clock Speed Selection
        3. 33.2.4.3 QSPI Redundant SBL Images Offset
        4. 33.2.4.4 Booting Device Order Selection
        5. 33.2.4.5 4192
        6. 33.2.4.6 Boot Peripheral Pin Multiplexing
    3. 33.3 Device Initialization by ROM Code
      1. 33.3.1 Booting Overview
        1. 33.3.1.1 Booting Types
        2. 33.3.1.2 ROM Code Architecture
      2. 33.3.2 Memory Maps
        1. 33.3.2.1 ROM Memory Map
        2. 33.3.2.2 RAM Memory Map
      3. 33.3.3 Overall Booting Sequence
      4. 33.3.4 Startup and Configuration
        1. 33.3.4.1 Startup
        2. 33.3.4.2 Control Module Configuration
        3. 33.3.4.3 PRCM Module Mode Configuration
        4. 33.3.4.4 Clocking Configuration
        5. 33.3.4.5 Booting Device List Setup
      5. 33.3.5 Peripheral Booting
        1. 33.3.5.1 Description
        2. 33.3.5.2 Initialization Phase for UART Boot
        3. 33.3.5.3 Initialization Phase for USB Boot
          1. 33.3.5.3.1 Initialization Procedure
          2. 33.3.5.3.2 SATA Peripheral Device Flashing over USB Interface
          3. 33.3.5.3.3 USB Driver Descriptors
          4. 33.3.5.3.4 4215
          5. 33.3.5.3.5 USB Customized Vendor and Product IDs
          6. 33.3.5.3.6 USB Driver Functionality
      6. 33.3.6 Fast External Booting
        1. 33.3.6.1 Overview
        2. 33.3.6.2 Fast External Booting Procedure
      7. 33.3.7 Memory Booting
        1. 33.3.7.1 Overview
        2. 33.3.7.2 Non-XIP Memory
        3. 33.3.7.3 XIP Memory
          1. 33.3.7.3.1 GPMC Initialization
        4. 33.3.7.4 NAND
          1. 33.3.7.4.1 Initialization and NAND Detection
          2. 33.3.7.4.2 NAND Read Sector Procedure
        5. 33.3.7.5 SPI/QSPI Flash Devices
        6. 33.3.7.6 eMMC Memories and SD Cards
          1. 33.3.7.6.1 eMMC Memories
            1. 33.3.7.6.1.1 System Conditions and Limitations
            2. 33.3.7.6.1.2 eMMC Memory Connection
          2. 33.3.7.6.2 SD Cards
            1. 33.3.7.6.2.1 System Conditions and Limitations
            2. 33.3.7.6.2.2 SD Card Connection
            3. 33.3.7.6.2.3 Booting Procedure
            4. 33.3.7.6.2.4 eMMC Partitions Handling in Alternative Boot Operation Mode
              1. 33.3.7.6.2.4.1 eMMC Devices Preflashing
              2. 33.3.7.6.2.4.2 eMMC Device State After ROM Code Execution
              3. 33.3.7.6.2.4.3 Consideration on device Global Warm Reset
              4. 33.3.7.6.2.4.4 Booting Image Size
              5. 33.3.7.6.2.4.5 Booting Image Layout
          3. 33.3.7.6.3 Initialization and Detection
          4. 33.3.7.6.4 Read Sector Procedure
          5. 33.3.7.6.5 File System Handling
            1. 33.3.7.6.5.1 MBR and FAT File System
        7. 33.3.7.7 SATA Device Boot Operation
          1. 33.3.7.7.1 SATA Booting Overview
          2. 33.3.7.7.2 SATA Power-Up Initialization Sequence
          3. 33.3.7.7.3 System Conditions and Limitations for SATA Boot
          4. 33.3.7.7.4 SATA Read Sector Procedure in FAT Mode
      8. 33.3.8 Image Format
        1. 33.3.8.1 Overview
        2. 33.3.8.2 Configuration Header
          1. 33.3.8.2.1 CHSETTINGS Item
          2. 33.3.8.2.2 CHFLASH Item
          3. 33.3.8.2.3 CHMMCSD Item
          4. 33.3.8.2.4 CHQSPI Item
        3. 33.3.8.3 GP Header
        4. 33.3.8.4 Image Execution
      9. 33.3.9 Tracing
    4. 33.4 Services for HLOS Support
      1. 33.4.1 Hypervisor
      2. 33.4.2 Caches Maintenance
      3. 33.4.3 CP15 Registers
      4. 33.4.4 Wakeup Generator
      5. 33.4.5 Arm Timer
      6. 33.4.6 MReq Domain
  36. 34On-Chip Debug Support
    1. 34.1  Introduction
      1. 34.1.1 Key Features
    2. 34.2  Debug Interfaces
      1. 34.2.1 IEEE1149.1
      2. 34.2.2 Debug (Trace) Port
      3. 34.2.3 Trace Connector and Board Layout Considerations
    3. 34.3  Debugger Connection
      1. 34.3.1 ICEPick Module
      2. 34.3.2 ICEPick Boot Modes
        1. 34.3.2.1 Default Boot Mode
        2. 34.3.2.2 Wait-In-Reset
      3. 34.3.3 Dynamic TAP Insertion
        1. 34.3.3.1 ICEPick Secondary TAPs
    4. 34.4  Primary Debug Support
      1. 34.4.1 Processor Native Debug Support
        1. 34.4.1.1 Cortex-A15 Processor
        2. 34.4.1.2 Cortex-M4 Processor
        3. 34.4.1.3 DSP C66x
        4. 34.4.1.4 IVA Arm968
        5. 34.4.1.5 PRU
      2. 34.4.2 Cross-Triggering
        1. 34.4.2.1 SoC-Level Cross-Triggering
        2. 34.4.2.2 Cross-Triggering With External Device
      3. 34.4.3 Suspend
        1. 34.4.3.1 Debug Aware Peripherals and Host Processors
    5. 34.5  Real-Time Debug
      1. 34.5.1 Real-Time Debug Events
        1. 34.5.1.1 Emulation Interrupts
    6. 34.6  Power, Reset, and Clock Management Debug Support
      1. 34.6.1 Power and Clock Management
        1. 34.6.1.1 Power and Clock Control Override From Debugger
          1. 34.6.1.1.1 Debugger Directives
            1. 34.6.1.1.1.1 FORCEACTIVE Debugger Directive
            2. 34.6.1.1.1.2 INHIBITSLEEP Debugger Directive
          2. 34.6.1.1.2 Intrusive Debug Model
        2. 34.6.1.2 Debug Across Power Transition
          1. 34.6.1.2.1 Nonintrusive Debug Model
          2. 34.6.1.2.2 Debug Context Save and Restore
            1. 34.6.1.2.2.1 Debug Context Save
            2. 34.6.1.2.2.2 Debug Context Restore
      2. 34.6.2 Reset Management
        1. 34.6.2.1 Debugger Directives
          1. 34.6.2.1.1 Assert Reset
          2. 34.6.2.1.2 Block Reset
          3. 34.6.2.1.3 Wait-In-Reset
    7. 34.7  Performance Monitoring
      1. 34.7.1 MPU Subsystem Performance Monitoring
        1. 34.7.1.1 Performance Monitoring Unit
        2. 34.7.1.2 L2 Cache Controller
      2. 34.7.2 IPU Subsystem Performance Monitoring
        1. 34.7.2.1 Subsystem Counter Timer Module
        2. 34.7.2.2 Cache Events
      3. 34.7.3 DSP Subsystem Performance Monitoring
        1. 34.7.3.1 Advanced Event Triggering
    8. 34.8  MPU Memory Adaptor (MPU_MA) Watchpoint
    9. 34.9  Processor Trace
      1. 34.9.1 Cortex-A15 Processor Trace
      2. 34.9.2 DSP Processor Trace
      3. 34.9.3 Trace Export
        1. 34.9.3.1 Trace Exported to External Trace Receiver
        2. 34.9.3.2 Trace Captured Into On-Chip Trace Buffer
        3. 34.9.3.3 Trace Exported Through USB
    10. 34.10 System Instrumentation
      1. 34.10.1 MIPI STM (CT_STM)
      2. 34.10.2 System Trace Export
        1. 34.10.2.1 CT_STM ATB Export
        2. 34.10.2.2 Trace Streams Interleaving
      3. 34.10.3 Software Instrumentation
        1. 34.10.3.1 MPU Software Instrumentation
        2. 34.10.3.2 SoC Software Instrumentation
      4. 34.10.4 OCP Watchpoint
        1. 34.10.4.1 OCP Target Traffic Monitoring
        2. 34.10.4.2 Messages Triggered from System Events
        3. 34.10.4.3 DMA Transfer Profiling
      5. 34.10.5 IVA Pipeline
      6. 34.10.6 L3 NOC Statistics Collector
        1. 34.10.6.1 L3 Target Load Monitoring
        2. 34.10.6.2 L3 Master Latency Monitoring
          1. 34.10.6.2.1  SC_LAT0 Configuration
          2. 34.10.6.2.2  SC_LAT1 Configuration
          3. 34.10.6.2.3  SC_LAT2 Configuration
          4. 34.10.6.2.4  SC_LAT3 Configuration
          5. 34.10.6.2.5  SC_LAT4 Configuration
          6. 34.10.6.2.6  SC_LAT5 Configuration
          7. 34.10.6.2.7  SC_LAT6 Configuration
          8. 34.10.6.2.8  SC_LAT7 Configuration
          9. 34.10.6.2.9  SC_LAT8 Configuration
          10. 34.10.6.2.10 Statistics Collector Alarm Mode
          11. 34.10.6.2.11 Statistics Collector Suspend Mode
      7. 34.10.7 PM Instrumentation
      8. 34.10.8 CM Instrumentation
      9. 34.10.9 Master-ID Encoding
        1. 34.10.9.1 Software Masters
        2. 34.10.9.2 Hardware Masters
    11. 34.11 Concurrent Debug Modes
    12. 34.12 DRM Register Manual
      1. 34.12.1 DRM Instance Summary
      2. 34.12.2 DRM Registers
        1. 34.12.2.1 DRM Register Summary
        2. 34.12.2.2 DRM Register Description
  37. 35Glossary
  38. 36Revision History
15.3.6.2.2 EMIF Register Description
Table 15-97 EMIF_REVISION
Address Offset0x0000 0000
Physical Address0x4C00 0000InstanceEMIF1
DescriptionRevision number register
TypeR
313029282726252423222120191817161514131211109876543210
REVISION
BitsField NameDescriptionTypeReset
31:0REVISIONModule revisionR0x- (1)
(1) TI internal data
Table 15-98 EMIF_STATUS
Address Offset0x0000 0004
Physical Address0x4C00 0004InstanceEMIF1
DescriptionSDRAM Status Register (STATUS)
TypeR
313029282726252423222120191817161514131211109876543210
BEDUAL_CLK_MODEFAST_INITRESERVEDRDLVLGATETORDLVLTOWRLVLTORESERVEDPHY_DLL_READYRESERVED
BitsField NameDescriptionTypeReset
31BEBig endian mode select for 8 and 16-bit devices, set to 1 for big endian or 0 for little endian operation. In current implementation, only 32-bit devices are supported - this bit is don't care.R0
30DUAL_CLK_MODEDual Clock mode. Defines whether the EMIFi_L3_ICLK and EMIF_FICLK clock are asynchronous. EMIFi_L3_ICLK and EMIF_FICLK clock are asynchronous, if set to 1.R0
29FAST_INITFast Init. Defines whether the EMIF fast initialization mode has been enabled. Fast initialization is enabled if set to 1.R0
28:7RESERVEDReservedR0x00 0000
6RDLVLGATETORead DQS Gate Training Timeout. Value of 1 indicates read DQS gate training has timed out because read DQS gate training done was not received from the PHY.R0
5RDLVLTORead Data Eye Training Timeout. Value of 1 indicates read data eye training has timed out because read data eye training done was not received from the PHY.R0
4WRLVLTOWrite Leveling Timeout. Value of 1 indicates write leveling has timed out because write leveling done was not received from the PHY.R0
3RESERVEDR0
2PHY_DLL_READYDDR PHY Ready. The DDR PHY is ready for normal operation, if set to 1.R0
1:0RESERVEDReservedR0x0
Table 15-99 EMIF_SDRAM_CONFIG
Address Offset0x0000 0008
Physical Address0x4C00 0008InstanceEMIF1
DescriptionSDRAM Config Register.
A write to this register will cause the EMIF to start the SDRAM initialization sequence.
CAUTION: This register is loaded with values by control module at device reset.
TypeRW
313029282726252423222120191817161514131211109876543210
SDRAM_TYPEIBANK_POSDDR_TERMDDR2_DDQSDYN_ODTDDR_DISABLE_DLLSDRAM_DRIVECWLNARROW_MODECLROWSIZEIBANKEBANKPAGESIZE
BitsField NameDescriptionTypeReset
31:29SDRAM_TYPESDRAM Type selection. This field is loaded from e-fuse.
Set to 3 for DDR3
All other values are reserved.		RW0x0
28:27IBANK_POSInternal bank position.
See SDRAM Address Mapping.		RW0x0
26:24DDR_TERMDDR3 termination resistor value. Set to 0 to disable termination. For DDR3,
set to 1 for RZQ/4,
set to 2 for RZQ/2,
set to 3 for RZQ/6,
set to 4 for RZQ/12, and
set to 5 for RZQ/8. All other values are reserved.		RW0x0
23DDR2_DDQSDifferential DQS enable. Set to 0 for single ended DQS (Not supported). Set to 1 for differential DQS.RW0
22:21DYN_ODTDDR3 Dynamic ODT. NOT SUPPORTED. Set to 0 to turn off dynamic ODT.RW0x0
20DDR_DISABLE_DLLDisable DLL select. Set to 1 to disable DLL inside SDRAM.RW0
19:18SDRAM_DRIVESDRAM drive strength.For DDR3, set to 0 for RZQ/6 and set to 1 for RZQ/7. All other values are reserved.RW0x0
17:16CWLDDR3 CAS Write latency. Value of 0, 1, 2, and 3 (CAS write latency of 5, 6, 7, and 8) are supported. Use the lowest value supported for best performance. All other values are reserved.RW0x0
15:14NARROW_MODE

SDRAM data bus width.

Set to 0 for 32-bit data bus width.

Set to 1 for 16-bit data bus width.

All other values are reserved.

RW0x0
13:10CLCAS Latency (referred to as read latency (RL) in some SDRAM specs). The value of this field defines the CAS latency to be used when accessing connected SDRAM devices.
Values of 2, 4, 6, 8, 10, 12 and 14 (CAS latency of 5, 6, 7, 8, 9, 10 and 11) are supported for DDR3.
All other values are reserved.
RW0x0
9:7ROWSIZERow Size. Defines the number of row address bits of connected SDRAM devices.
Set to 0 for 9 row bits,
Set to 1 for 10 row bits,
Set to 2 for 11 row bits,
Set to 3 for 12 row bits,
Set to 4 for 13 row bits,
Set to 5 for 14 row bits,
Set to 6 for 15 row bits,
Set to 7 for 16 row bits.
This field is only used when EMIF_SDRAM_CONFIG[28:27] IBANK_POS field is set to 1, 2, or 3 or EBANK_POS field in EMIF_SDRAM_CONFIG_2 register is set to 1.		RW0x0
6:4IBANKInternal Bank setup. Defines number of banks inside connected SDRAM devices.
Set to 0 for 1 bank,
Set to 1 for 2 banks,
Set to 2 for 4 banks,
Set to 3 for 8 banks.
All other values are reserved.		RW0x0
3EBANKExternal chip select setup. Defines whether SDRAM accesses will use 1 or 2 chip select lines.
Set to 0 to use CSN0 only.
Set to 1 to use CSN[1:0].
NOTE: Chip select 1 is not supported on this device.		RW0
2:0PAGESIZEPage Size. Defines the internal page size of connected SDRAM devices.
Set to 0 for 256-word page (8 column bits),
Set to 1 for 512-word page (9 column bits),
Set to 2 for 1024-word page (10 column bits),
Set to 3 for 2048-word page (11 column bits).
All other values are reserved.		RW0x0
Table 15-100 EMIF_SDRAM_CONFIG_2
Address Offset0x0000 000C
Physical Address0x4C00 000CInstanceEMIF1
DescriptionSDRAM Config Register 2
CAUTION: This register is loaded with values by control module at device reset.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEBANK_POSRESERVED
BitsField NameDescriptionTypeReset
31:28RESERVEDR0x0
27EBANK_POSExternal bank position. Set to 0 to assign external bank address bits from lower OCP address. Set to 1 to assign external bank address bits from higher OCP address bits. See SDRAM Address Mapping.RW0
26:0RESERVEDR0x00 0000
Table 15-101 EMIF_SDRAM_REFRESH_CONTROL
Address Offset0x0000 0010
Physical Address0x4C00 0010InstanceEMIF1
DescriptionSDRAM Refresh Control Register
TypeRW
313029282726252423222120191817161514131211109876543210
INITREF_DISRESERVEDSRTASRRESERVEDPASRRESERVEDREFRESH_RATE
BitsField NameDescriptionTypeReset
31INITREF_DISInitialization and Refresh disable.
When set to 1, EMIF will disable SDRAM initialization and refreshes, but will carry out SDRAM write/read transactions.		RW1
30RESERVEDR0
29SRTDDR3 Self Refresh temperature range. Set to 0 for normal operating temperature range and set to 1 for extended operating temperature range when the ASR field is set to 0. This bit must be set to 0 if the ASR field is set to 1. A write to this field will cause the EMIF to start the SDRAM initialization sequence.RW0
28ASRDDR3 Auto Self Refresh enable. Set to 1 for auto Self Refresh enable. Set to 0 for manual Self Refresh reference indicated by the SRT field. A write to this field will cause the EMIF to start the SDRAM initialization sequence.RW0
27RESERVEDR0
26:24PASRPartial Array Self Refresh. These bits get loaded into the Extended Mode Register of DDR3 during initialization. For DDR3,
set to 0 for full array,
set to 1 or 5 for 1/2 array,
set to 2 or 6 for 1/4 array,
set to 3 or 7 for 1/8 array, and
set to 4 for 3/4 array to be refreshed. All other values are reserved. A write to this field will cause the EMIF to start the SDRAM initialization sequence.		RW0x0
23:16RESERVEDR0x00
15:0REFRESH_RATERefresh Rate. Value in this field is used to define the rate at which connected SDRAM devices will be refreshed. SDRAM refresh rate = REFRESH_RATE / EMIF_PHY_FCLK.
A 533-MHz DDR clock rate system that requires a 7.8 µs refresh rate would need 7.8 × 533 = 4157 or 0x103D value to be written.
To avoid lock-up situations, the programmer must not program REFRESH_RATE < (6 × EMIF_SDRAM_TIMING_3[12:4] T_RFC).
Note: NOTE: The SDRAM refresh rate can be changed on-the-fly by writing to this field.
When changing the SDRAM refresh rate all timing parameters that use the refresh rate value have to be recalculated. For example, tRASmax specified in the EMIF_SDRAM_TIMING_3[3:0] T_RAS_MAX field must be recalculated.
RW0x0000
Table 15-102 EMIF_SDRAM_REFRESH_CONTROL_SHADOW
Address Offset0x0000 0014
Physical Address0x4C00 0014InstanceEMIF1
DescriptionSDRAM Refresh Control Shadow Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREFRESH_RATE_SHDW
BitsField NameDescriptionTypeReset
31:16RESERVEDReservedR0x0000
15:0REFRESH_RATE_SHDWShadow field for REFRESH_RATE. This field is loaded into EMIF_SDRAM_REFRESH_CONTROL[15:0] REFRESH_RATE field when SIdleAck is asserted.RW0x0000
Table 15-103 EMIF_SDRAM_TIMING_1
Address Offset0x0000 0018
Physical Address0x4C00 0018InstanceEMIF1
DescriptionSDRAM Timing 1 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM.
TypeRW
313029282726252423222120191817161514131211109876543210
T_RTWT_RPT_RCDT_WRT_RAST_RCT_RRDT_WTR
BitsField NameDescriptionTypeReset
31:29T_RTWMinimum number of DDR clock cycles between Read to Write data phases, minus one.RW0x0
28:25T_RPMinimum number of DDR clock cycles from Precharge to Activate or Refresh, minus one.RW0x0
24:21T_RCDMinimum number of DDR clock cycles from Activate to Read or Write, minus one.RW0x0
20:17T_WRMinimum number of DDR clock cycles from last Write transfer to Precharge, minus one.RW0x0
16:12T_RASMinimum number of DDR clock cycles from Activate to Precharge, minus one. T_RAS value needs to be bigger than or equal to T_RDC value.RW0x00
11:6T_RCMinimum number of DDR clock cycles from Activate to Activate, minus one.RW0x00
5:3T_RRDMinimum number of DDR clock cycles from Activate to Activate for a different bank, minus one.
For an 8-bank, this field must be equal to ((tFAW / (4 × tCK)) - 1).		RW0x0
2:0T_WTRMinimum number of DDR clock cycles from last Write to Read, minus one.RW0x0
Table 15-104 EMIF_SDRAM_TIMING_1_SHADOW
Address Offset0x0000 001C
Physical Address0x4C00 001CInstanceEMIF1
DescriptionSDRAM Timing 1 Shadow Register
TypeRW
313029282726252423222120191817161514131211109876543210
T_RTW_SHDWT_RP_SHDWT_RCD_SHDWT_WR_SHDWT_RAS_SHDWT_RC_SHDWT_RRD_SHDWT_WTR_SHDW
BitsField NameDescriptionTypeReset
31:29T_RTW_SHDWShadow field for T_RTW. This field is loaded into EMIF_SDRAM_TIMING_1[31:29] T_RTW field when SIdleAck is asserted.RW0x0
28:25T_RP_SHDWShadow field for T_RP. This field is loaded into EMIF_SDRAM_TIMING_1[28:25] T_RP field when SIdleAck is asserted.RW0x0
24:21T_RCD_SHDWShadow field for T_RCD. This field is loaded into EMIF_SDRAM_TIMING_1[24:21] T_RCD field when SIdleAck is asserted.RW0x0
20:17T_WR_SHDWShadow field for T_WR. This field is loaded into EMIF_SDRAM_TIMING_1[20:17] T_WR field when SIdleAck is asserted.RW0x0
16:12T_RAS_SHDWShadow field for T_RAS. This field is loaded into EMIF_SDRAM_TIMING_1[16:12] T_RAS field when SIdleAck is asserted.RW0x00
11:6T_RC_SHDWShadow field for T_RC. This field is loaded into EMIF_SDRAM_TIMING_1[11:6] T_RC field when SIdleAck is asserted.RW0x00
5:3T_RRD_SHDWShadow field for T_RRD. This field is loaded into EMIF_SDRAM_TIMING_1[5:3] T_RRD field when SIdleAck is asserted.RW0x0
2:0T_WTR_SHDWShadow field for T_WTR. This field is loaded into EMIF_SDRAM_TIMING_1[2:0] T_WTR field when SIdleAck is asserted.RW0x0
Table 15-105 EMIF_SDRAM_TIMING_2
Address Offset0x0000 0020
Physical Address0x4C00 0020InstanceEMIF1
DescriptionSDRAM Timing 2 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDT_XPRESERVEDT_XSNRT_XSRDT_RTPT_CKE
BitsField NameDescriptionTypeReset
31RESERVEDReservedR0
30:28T_XPMinimum number of DDR clock cycles from power-down exit to any command other than a read command, minus one.RW0x0
27:25RESERVEDReservedRW0x0
24:16T_XSNRMinimum number of DDR clock cycles from Self-Refresh exit to any command other than a Read command, minus one.RW0x000
15:6T_XSRDMinimum number of DDR clock cycles from Self-Refresh exit to a Read command, minus one.RW0x000
5:3T_RTPMinimum number of DDR clock cycles for the last read command to a Precharge command, minus one.RW0x0
2:0T_CKEMinimum number of DDR clock cycles between CKE pin changes, minus one.RW0x0
Table 15-106 EMIF_SDRAM_TIMING_2_SHADOW
Address Offset0x0000 0024
Physical Address0x4C00 0024InstanceEMIF1
DescriptionSDRAM Timing 2 Shadow Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDT_XP_SHDWRESERVEDT_XSNR_SHDWT_XSRD_SHDWT_RTP_SHDWT_CKE_SHDW
BitsField NameDescriptionTypeReset
31RESERVEDReservedR0
30:28T_XP_SHDWShadow field for T_XP. This field is loaded into EMIF_SDRAM_TIMING_2[30:28] T_XP field when SIdleAck is asserted.RW0x0
27:25RESERVEDReservedRW0x0
24:16T_XSNR_SHDWShadow field for T_XSNR. This field is loaded into EMIF_SDRAM_TIMING_2[24:16] T_XSNR field when SIdleAck is asserted.RW0x000
15:6T_XSRD_SHDWShadow field for T_XSRD. This field is loaded into EMIF_SDRAM_TIMING_2[15:6] T_XSRD field when SIdleAck is asserted.RW0x000
5:3T_RTP_SHDWShadow field for T_RTP. This field is loaded into EMIF_SDRAM_TIMING_2[5:3] T_RTP field when SIdleAck is asserted.RW0x0
2:0T_CKE_SHDWShadow field for T_CKE. This field is loaded into EMIF_SDRAM_TIMING_2[2:0] T_CKE field when SIdleAck is asserted.RW0x0
Table 15-107 EMIF_SDRAM_TIMING_3
Address Offset0x0000 0028
Physical Address0x4C00 0028InstanceEMIF1
DescriptionSDRAM Timing 3 Register. If this register is byte written, care must be taken that all the fields are written before performing any accesses to the SDRAM.
TypeRW
313029282726252423222120191817161514131211109876543210
T_PDLL_ULRESERVEDT_CKESRZQ_ZQCSRESERVEDT_RFCT_RAS_MAX
BitsField NameDescriptionTypeReset
31:28T_PDLL_ULMinimum number of DDR clock cycles for PHY DLL to unlock. A value of N will be equal to N x 128 clocks.RW0x0
27:24RESERVEDR0x0
23:21T_CKESRMinimum number of DDR clock cycles for which SDRAM must remain in Self Refresh, minus one.RW0x0
20:15ZQ_ZQCSNumber of DDR clock cycles for a ZQCS command, minus one.RW0x00
14:13RESERVEDR0x0
12:4T_RFCMinimum number of DDR clock cycles from Refresh or Load Mode to Refresh or Activate, minus one.RW0x000
3:0T_RAS_MAXMaximum number of REFRESH_RATE intervals from Activate to Precharge command. This field must be equal to ((tRASmax / tREFI)-1) rounded down to the next lower integer.
Value for T_RAS_MAX can be calculated as follows:
If tRASmax = 120 us and tREFI = 15.7 us, then T_RAS_MAX = ((120/15.7)-1) = 6.64.
Round down to the next lower integer. Therefore, the programmed value must be 6.		RW0x0
Table 15-108 EMIF_SDRAM_TIMING_3_SHADOW
Address Offset0x0000 002C
Physical Address0x4C00 002CInstanceEMIF1
DescriptionSDRAM Timing 3 Shadow Register
TypeRW
313029282726252423222120191817161514131211109876543210
T_PDLL_UL_SHDWRESERVEDT_CKESR_SHDWZQ_ZQCS_SHDWRESERVEDT_RFC_SHDWT_RAS_MAX_SHDW
BitsField NameDescriptionTypeReset
31:28T_PDLL_UL_SHDWShadow field for T_PDLL_UL. This field is loaded into T_PDLL_UL field in EMIF_SDRAM_TIMING_3 register when SIdleAck is asserted.RW0x0
27:24RESERVEDR0x0
23:21T_CKESR_SHDWShadow field for T_CKESR. This field is loaded into T_CKESR field in EMIF_SDRAM_TIMING_3 register when SIdleAck is asserted.RW0x0
20:15ZQ_ZQCS_SHDWShadow field for ZQ_ZQCS. This field is loaded into ZQ_ZQCS field in EMIF_SDRAM_TIMING_3 register when SIdleAck is asserted.RW0x00
14:13RESERVEDR0x0
12:4T_RFC_SHDWShadow field for T_RFC. This field is loaded into EMIF_SDRAM_TIMING_3[12:4] T_RFC when SIdleAck is asserted.RW0x000
3:0T_RAS_MAX_SHDWShadow field for T_RAS_MAX. This field is loaded into EMIF_SDRAM_TIMING_3[3:0] T_RAS_MAX field when SIdleAck is asserted.RW0x0
Table 15-109 EMIF_LPDDR2_NVM_TIMING
Address Offset0x0000 0030
Physical Address0x4C00 0030InstanceEMIF1
DescriptionNOTE: This register is not supported. It is kept only for code compatibility.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVED
BitsField NameDescriptionTypeReset
31:0RESERVEDReservedRW0x0
Table 15-110 EMIF_LPDDR2_NVM_TIMING_SHADOW
Address Offset0x0000 0034
Physical Address0x4C00 0034InstanceEMIF1
DescriptionNOTE: This register is not supported. It is kept only for code compatibility.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVED
BitsField NameDescriptionTypeReset
31:0RESERVEDReservedRW0x0
Table 15-111 EMIF_POWER_MANAGEMENT_CONTROL
Address Offset0x0000 0038
Physical Address0x4C00 0038InstanceEMIF1
DescriptionPower Management Control Register. Updating the *_TIM fields must be followed by at least one access to SDRAM for the new value to take an effect.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPD_TIMRESERVEDLP_MODESR_TIMRESERVED
BitsField NameDescriptionTypeReset
31:16RESERVEDR0x0000
15:12PD_TIMPower Management timer for Power-Down. The EMIF will put the external SDRAM in Power-Down mode after the EMIF is idle for these number of DDR clock cycles and if LP_MODE field is set to 4. Set to 0 to immediately enter Power-Down mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks.RW0x0
11RESERVEDR0
10:8LP_MODE

Automatic Power Management enable.

0x0: Disable automatic power management

0x1: Reserved

0x2: Self Refresh mode

0x3: Disable automatic power management

0x4: Power-Down mode

All other values disable automatic power management.

RW0x0
7:4SR_TIMPower Management timer for Self Refresh. The EMIF will put the external SDRAM in Self Refresh mode after the EMIF is idle for these number of DDR clock cycles and if LP_MODE field is set to 2. Set to 0 to immediately enter Self Refresh mode. Set to 1 for 16 clocks, set to 2 for 32 clocks, set to 3 for 64 clocks, set to 4 for 128 clocks, set to 5 for 256 clocks, set to 6 for 512 clocks, set to 7 for 1024 clocks, set to 8 for 2048 clocks, set to 9 for 4096 clocks, set to 10 for 8192 clocks, set to 11 for 16384 clocks, set to 12 for 32768 clocks, set to 13 for 65536 clocks, set to 14 for 131072 clocks, and set to 15 for 262144 clocks.RW0x0
3:0RESERVEDRW0x0
Table 15-112 EMIF_POWER_MANAGEMENT_CONTROL_SHADOW
Address Offset0x0000 003C
Physical Address0x4C00 003CInstanceEMIF1
DescriptionPower Management Control Shadow Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPD_TIM_SHDWRESERVEDSR_TIM_SHDWRESERVED
BitsField NameDescriptionTypeReset
31:16RESERVEDR0x0000
15:12PD_TIM_SHDWShadow field for PD_TIM. This field is loaded into PD_TIM field in EMIF_POWER_MANAGEMENT_CONTROL register when SIdleAck is asserted.RW0x0
11:8RESERVEDR0x0
7:4SR_TIM_SHDWShadow field for SR_TIM. This field is loaded into SR_TIM field in EMIF_POWER_MANAGEMENT_CONTROL register when SIdleAck is asserted.RW0x0
3:0RESERVEDRW0x0
Table 15-113 EMIF_OCP_CONFIG
Address Offset0x0000 0054
Physical Address0x4C00 0054InstanceEMIF1
DescriptionOCP Config Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDSYS_THRESH_MAXMPU_THRESH_MAXRESERVED
BitsField NameDescriptionTypeReset
31:28RESERVEDR0x0
27:24SYS_THRESH_MAXSystem OCP Threshold Maximum. The number of commands the system interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for the associated interface. In the event the value is set to zero and a request is seen for that interface, the command FIFO will assume a value of 1. RW0x7
23:20MPU_THRESH_MAXMPU Threshold Maximum. The number of commands the MPU interface can consume in the command FIFO. The value is used to determine when to stop future request, writing a zero will reserve no space for the associated interface. In the event the value is set to zero and a request is seen for that interface, the command FIFO will assume a value of 1. RW0x7
19:0RESERVEDR0x70000
Table 15-114 EMIF_OCP_CONFIG_VALUE_1
Address Offset0x0000 0058
Physical Address0x4C00 0058InstanceEMIF1
DescriptionOCP Config Value 1 Register
TypeR
313029282726252423222120191817161514131211109876543210
SYS_BUS_WIDTHRESERVEDWR_FIFO_DEPTHCMD_FIFO_DEPTH
BitsField NameDescriptionTypeReset
31:30SYS_BUS_WIDTHSystem OCP data bus width
0 = 32-bit wide,
1 = 64-bit wide,
2 = 128-bit wide,
3 = Reserved		R0x2
29:16RESERVEDR0x1000
15:8WR_FIFO_DEPTHWrite Data FIFO depthR0x19
7:0CMD_FIFO_DEPTHCommand FIFO depthR0x0A
Table 15-115 EMIF_OCP_CONFIG_VALUE_2
Address Offset0x0000 005C
Physical Address0x4C00 005CInstanceEMIF1
DescriptionOCP Config Value 2 Register
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDRREG_FIFO_DEPTHRSD_FIFO_DEPTHRCMD_FIFO_DEPTH
BitsField NameDescriptionTypeReset
31:24RESERVEDReservedR0x00
23:16RREG_FIFO_DEPTHRegister Read Data FIFO depthR0x04
15:8RSD_FIFO_DEPTHSDRAM Read Data FIFO depthR0x27
7:0RCMD_FIFO_DEPTHRead Command FIFO depthR0x27
Table 15-116 EMIF_IODFT_TLGC
Address Offset0x0000 0060
Physical Address0x4C00 0060InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESET_PHYRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
BitsField NameDescriptionTypeReset
31:16RESERVEDReserved. This field must not be modified.RW0x0
15RESERVEDReservedR0x0
14RESERVEDReserved. This bit must not be modified.RW0x0
13RESERVEDReserved. This bit must not be modified.RW0x1
12RESERVEDReserved. This bit must not be modified.RW0x0
11RESERVEDReservedR0x0
10RESET_PHYReset the DDR PHY. Writing 1 to this bit resets the DDR PHY. This bit will self clear to 0.RW0x0
9RESERVEDReservedR0x0
8RESERVEDReserved. This bit must not be modified.RW0x0
7:6RESERVEDReservedR0x0
5:4RESERVEDReserved. This field must not be modified.RW0x1
3:1RESERVEDReserved. This field must not be modified.RW0x0
0RESERVEDReserved. This bit must not be modified.RW0x1
Table 15-117 EMIF_PERFORMANCE_COUNTER_1
Address Offset0x0000 0080
Physical Address0x4C00 0080InstanceEMIF1
DescriptionPerformance Counter 1 Register
TypeR
313029282726252423222120191817161514131211109876543210
COUNTER1
BitsField NameDescriptionTypeReset
31:0COUNTER132-bit counter that can be configured as specified in the EMIF_PERFORMANCE_COUNTER_CONFIG register and EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT register.R0x0000 0000
Table 15-118 EMIF_PERFORMANCE_COUNTER_2
Address Offset0x0000 0084
Physical Address0x4C00 0084InstanceEMIF1
DescriptionPerformance Counter 2 Register
TypeR
313029282726252423222120191817161514131211109876543210
COUNTER2
BitsField NameDescriptionTypeReset
31:0COUNTER232-bit counter that can be configured as specified in the EMIF_PERFORMANCE_COUNTER_CONFIG register and EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT register.R0x0000 0000
Table 15-119 EMIF_PERFORMANCE_COUNTER_CONFIG
Address Offset0x0000 0088
Physical Address0x4C00 0088InstanceEMIF1
DescriptionPerformance Counter Config Register
TypeRW
313029282726252423222120191817161514131211109876543210
CNTR2_MCONNID_ENCNTR2_REGION_ENRESERVEDCNTR2_CFGCNTR1_MCONNID_ENCNTR1_REGION_ENRESERVEDCNTR1_CFG
BitsField NameDescriptionTypeReset
31CNTR2_MCONNID_ENMConnID filter enable for EMIF_PERFORMANCE_COUNTER_2 register.RW0
30CNTR2_REGION_ENChip Select filter enable for EMIF_PERFORMANCE_COUNTER_2 register.RW0
29:20RESERVEDReserved for future useR0x000
19:16CNTR2_CFGFilter configuration for EMIF_PERFORMANCE_COUNTER_2. Refer to Table 15-86 for details.RW0x1
15CNTR1_MCONNID_ENMConnID filter enable for EMIF_PERFORMANCE_COUNTER_1 register.RW0
14CNTR1_REGION_ENChip Select filter enable for EMIF_PERFORMANCE_COUNTER_1 register.RW0
13:4RESERVEDReserved for future useR0x000
3:0CNTR1_CFGFilter configuration for EMIF_PERFORMANCE_COUNTER_1. Refer to Table 15-86 for details.RW0x0
Table 15-120 EMIF_PERFORMANCE_COUNTER_MASTER_REGION_SELECT
Address Offset0x0000 008C
Physical Address0x4C00 008CInstanceEMIF1
DescriptionPerformance Counter Master Region Select Register
The values programmed into the MCONNIDx fields are those in the ConnID Values table in Interconnect.
TypeRW
313029282726252423222120191817161514131211109876543210
MCONNID2RESERVEDREGION_SEL2MCONNID1RESERVEDREGION_SEL1
BitsField NameDescriptionTypeReset
31:24MCONNID2MConnID for EMIF_PERFORMANCE_COUNTER_2 register.RW0x00
23:18RESERVEDReservedR0x00
17:16REGION_SEL2MAddrSpace for EMIF_PERFORMANCE_COUNTER_2 register.RW0x0
15:8MCONNID1MConnID for EMIF_PERFORMANCE_COUNTER_1 register.RW0x00
7:2RESERVEDReservedR0x00
1:0REGION_SEL1MAddrSpace for EMIF_PERFORMANCE_COUNTER_1 register.RW0x0
Table 15-121 EMIF_PERFORMANCE_COUNTER_TIME
Address Offset0x0000 0090
Physical Address0x4C00 0090InstanceEMIF1
DescriptionPerformance Counter Time Register. This is a free running counter.
TypeR
313029282726252423222120191817161514131211109876543210
TOTAL_TIME
BitsField NameDescriptionTypeReset
31:0TOTAL_TIME32-bit counter that continuously counts number for EMIF_FICLK clock cycles elapsed after EMIF is brought out of reset.R0x0000 0000
Table 15-122 EMIF_MISC_REG
Address Offset0x0000 0094
Physical Address0x4C00 0094InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDDLL_CALIB_OS
BitsField NameDescriptionTypeReset
31:1RESERVEDReservedR0x0
0DLL_CALIB_OSPhy_dll_calib one shot : Setting bit to 1 generates a phy_pll_calib pulse. Bit is self cleared when pll_calib gets generated and ack_wait has been satisfied. Software can poll to confirm completion.
Uses the EMIF_DLL_CALIB_CTRL[19:16] ACK_WAIT bit field for time to wait after firing off the phy_dll_calib.		RW0x0
Table 15-123 EMIF_DLL_CALIB_CTRL
Address Offset0x0000 0098
Physical Address0x4C00 0098InstanceEMIF1
DescriptionControl register to force idle window time to generate a phy_dll_calib that can be used for updating PHY DLLs during voltage ramps. NOTE: Should always be loaded via the shadow register.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDACK_WAITRESERVEDDLL_CALIB_INTERVAL
BitsField NameDescriptionTypeReset
31:20RESERVEDR0x000
19:16ACK_WAITThe ack_wait determines the required wait time after a phy_dll_calib is generated before another command can be sent. Value program is in terms of EMIF_FICLK cycle count.
CAUTION: 5 must be the minimum value ever programmed.		RW0x9
15:9RESERVEDR0x00
8:0DLL_CALIB_INTERVALThis field determines the interval between phy_dll_calib generation. This value is multiplied by a precounter of 16 EMIF_FICLK cycles. Program this field one less the value you are targeting; program 1 to achieve interval of 2 (minimum interval supported). Programming zero turns off function. Note the final intervals between dll_calib generation is also a function of ACK_WAIT. Final periodic interval is calculated by: ((DLL_CALIB_INTERVAL + 1) × 16) + ACK_WAITRW0x000
Table 15-124 EMIF_DLL_CALIB_CTRL_SHADOW
Address Offset0x0000 009C
Physical Address0x4C00 009CInstanceEMIF1
DescriptionRead Idle Control Shadow Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDACK_WAIT_SHDWRESERVEDDLL_CALIB_INTERVAL_SHDW
BitsField NameDescriptionTypeReset
31:20RESERVEDR0x000
19:16ACK_WAIT_SHDWShadow field for ACK_WAIT. This field is loaded into ACK_WAIT field in EMIF_DLL_CALIB_CTRL register when SIdleAck is assertedRW0x9
15:9RESERVEDR0x00
8:0DLL_CALIB_INTERVAL_SHDWShadow field for DLL_CALIB_INTERVAL. This field is loaded into DLL_CALIB_INTERVAL field in the EMIF_DLL_CALIB_CTRL register when SIdleAck is assertedRW0x000
Table 15-125 EMIF_END_OF_INTERRUPT
Address Offset0x0000 00A0
Physical Address0x4C00 00A0InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDEOI
BitsField NameDescriptionTypeReset
31:1RESERVEDR0x0
0EOISoftware End Of Interrupt (EOI) control. Write 0x0 for system OCP interrupt. This field always reads 0 (no EOI memory).RW0x0
Table 15-126 EMIF_SYSTEM_OCP_INTERRUPT_RAW_STATUS
Address Offset0x0000 00A4
Physical Address0x4C00 00A4InstanceEMIF1
DescriptionSystem OCP Interrupt Raw Status Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDONEBIT_ECC_ERR_SYSTWOBIT_ECC_ERR_SYSWR_ECC_ERR_SYSRESERVEDERR_SYS
BitsField NameDescriptionTypeReset
31:6RESERVEDR0x000 0000
5ONEBIT_ECC_ERR_SYSRaw status of system ECC one bit error correction interrupt.RW0x0
4TWOBIT_ECC_ERR_SYSRaw status of system ECC two bit error detection interrupt.RW0x0
3WR_ECC_ERR_SYSRaw status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location.RW0x0
2:1RESERVEDR0x0
0ERR_SYSRaw status of system OCP interrupt for command or address error.
Write 1 to set the (raw) status, mostly for debug.
Writing a 0 has no effect.		RW0
Table 15-127 EMIF_SYSTEM_OCP_INTERRUPT_STATUS
Address Offset0x0000 00AC
Physical Address0x4C00 00ACInstanceEMIF1
DescriptionSystem OCP Interrupt Status Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDONEBIT_ECC_ERR_SYSTWOBIT_ECC_ERR_SYSWR_ECC_ERR_SYSRESERVEDERR_SYS
BitsField NameDescriptionTypeReset
31:6RESERVEDR0x000 0000
5ONEBIT_ECC_ERR_SYSEnabled status of system ECC one bit error correction interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effectRW0x0
4TWOBIT_ECC_ERR_SYSEnabled status of system ECC two bit error detection interrupt. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect.RW0x0
3WR_ECC_ERR_SYSEnabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is even if not enabled). Writing a 0 has no effect.RW0x0
2:1RESERVEDR0x0
0ERR_SYSEnabled status of system OCP interrupt interrupt for command or address error.
Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled).
Writing a 0 has no effect.		RW0
Table 15-128 EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET
Address Offset0x0000 00B4
Physical Address0x4C00 00B4InstanceEMIF1
DescriptionSystem OCP Interrupt Enable Set Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDONEBIT_ECC_ERR_SYSTWOBIT_ECC_ERR_SYSWR_ECC_ERR_SYSRESERVEDEN_ERR_SYS
BitsField NameDescriptionTypeReset
31:6RESERVEDR0x000 0000
5ONEBIT_ECC_ERR_SYSEnabled status of sysem ECC one bit error correction interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.RW W1toSet0x0
4TWOBIT_ECC_ERR_SYSEnabled status of system ECC two bit error detection interrupt. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.RW W1toSet0x0
3WR_ECC_ERR_SYSEnabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register. Writing a 0 has no effect.RW W1toSet0x0
2:1RESERVEDR0x0
0EN_ERR_SYSEnable set for system OCP interrupt for command or address error.
Writing a 1 will enable the interrupt, and set this bit as well as the corresponding Interrupt Enable Clear Register.
Writing a 0 has no effect.		RW W1toSet0
Table 15-129 EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR
Address Offset0x0000 00BC
Physical Address0x4C00 00BCInstanceEMIF1
DescriptionSystem OCP Interrupt Enable Clear Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDONEBIT_ECC_ERR_SYSTWOBIT_ECC_ERR_SYSWR_ECC_ERR_SYSRESERVEDEN_ERR_SYS
BitsField NameDescriptionTypeReset
31:6RESERVEDR0x000 0000
5ONEBIT_ECC_ERR_SYSEnabled status of system ECC one bit error correction interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.RW W1toClr0x0
4TWOBIT_ECC_ERR_SYSEnabled status of system ECC two bit error detection interrupt. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.RW W1toClr0x0
3WR_ECC_ERR_SYSEnabled status of system ECC Error interrupt when a memory access is made to a non-quanta aligned location. Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register. Writing a 0 has no effect.RW W1toClr0x0
2:1RESERVEDR0x0
0EN_ERR_SYSEnable clear for system OCP interrupt for command or address error.
Writing a 1 will disable the interrupt, and clear this bit as well as the corresponding Interrupt Enable Set Register.
Writing a 0 has no effect.		RW W1toClr0
Table 15-130 EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG
Address Offset0x0000 00C8
Physical Address0x4C00 00C8InstanceEMIF1
DescriptionSDRAM Output Impedance Calibration Config Register
TypeRW
313029282726252423222120191817161514131211109876543210
ZQ_CS1ENZQ_CS0ENZQ_DUALCALENZQ_SFEXITENRESERVEDZQ_ZQINIT_MULTZQ_ZQCL_MULTZQ_REFINTERVAL
BitsField NameDescriptionTypeReset
31ZQ_CS1ENWriting a 1 enables ZQ calibration for CS1.RW0x0
30ZQ_CS0ENWriting a 1 enables ZQ calibration for CS0.RW0x0
29ZQ_DUALCALENZQ Dual Calibration enable. Allows both ranks to be ZQ calibrated simultaneously. Setting this bit requires both chip selects to have a separate calibration resistor per device.
NOTE: Chip select 1 is not supported on this device.		RW0x0
28ZQ_SFEXITENWriting a 1 enables the issuing of ZQCL on Self-Refresh, Active Power-Down, and Precharge Power-Down exit.RW0x0
27:20RESERVEDR0x00
19:18ZQ_ZQINIT_MULTIndicates the number of ZQCL durations that make up a ZQINIT duration, minus one.RW0x0
17:16ZQ_ZQCL_MULTIndicates the number of ZQCS intervals that make up a ZQCL duration, minus one. ZQCS interval is defined by ZQ_ZQCS in EMIF_SDRAM_TIMING_3.RW0x0
15:0ZQ_REFINTERVALNumber of refresh periods between ZQCS commands. This field supports between one refresh period to 256 ms between ZQCS calibration commands. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register.RW0x0000
Table 15-131 EMIF_TEMP_ALERT_CONFIG
Address Offset0x0000 00CC
Physical Address0x4C00 00CCInstanceEMIF1
DescriptionTemperature Alert Configuration Register. NOTE: This register is only applicable to LPDDR2 memories and cannot be used in this device.
TypeRW
313029282726252423222120191817161514131211109876543210
TA_CS1ENTA_CS0ENRESERVEDTA_SFEXITENTA_DEVWDTTA_DEVCNTRESERVEDTA_REFINTERVAL
BitsField NameDescriptionTypeReset
31TA_CS1ENWriting 1 enables temperature alert polling for CS1.RW0x0
30TA_CS0ENWriting 1 enables temperature alert polling for CS0.RW0x0
29RESERVEDReservedR0x0
28TA_SFEXITENTemperature Alert Poll on Self-Refresh, Active Power-Down, and Precharge Power-Down exit enable. Writing 1 enables the issuing of a temperature alert poll on Self-Refresh exit.RW0x0
27:26TA_DEVWDTThis field indicates how wide a physical device is. It is used in conjunction with the TA_DEVCNT field to determine which byte lanes contain the temperature alert info. A value of
0: 8-bit wide,
1: 16-bit wide,
2: 32-bit wide.
All others are reserved. If this field is set to 1 and the TA_DEVCNT field is set to 1 the byte mask for checking is 4'b0101.		RW0x0
25:24TA_DEVCNTThis field indicates which external byte lanes contain a device for temperature monitoring. A value of
0: one device,
1: two devices,
2: four devices.
All other reserved.		RW0x0
23:22RESERVEDReservedR0x0
21:0TA_REFINTERVALNumber of refresh periods between temperature alert polls. This field supports between one refresh period to 10 seconds between temperature alert polls. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register.RW0x0
Table 15-132 EMIF_OCP_ERROR_LOG
Address Offset0x0000 00D0
Physical Address0x4C00 00D0InstanceEMIF1
DescriptionOCP Error Log Register. This register is overwritten by any first error transaction once after the interrupt is serviced and cleared by writing 0x1 to the EMIF_SYSTEM_OCP_INTERRUPT_STATUS[0] ERR_SYS bit.
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDMADDRSPACEMBURSTSEQMCMDMCONNID
BitsField NameDescriptionTypeReset
31:16RESERVEDReserved for future use.R0x0000
15:14MADDRSPACEAddress space of the first errored transaction.
0x0: SDRAM
0x1: reserved
0x2: reserved
0x3: internal registers		R0x0
13:11MBURSTSEQAddressing mode of the first errored transaction. (see L3_MAIN Interconnect for more information)R0x0
10:8MCMDCommand type of the first errored transaction. (see L3_MAIN Interconnect for more information)R0x0
7:0MCONNIDConnection ID of the first errored transaction.R0x00
Table 15-133 EMIF_READ_WRITE_LEVELING_RAMP_WINDOW
Address Offset0x0000 00D4
Physical Address0x4C00 00D4InstanceEMIF1
DescriptionRead/write leveling ramp window register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRDWRLVLINC_RMP_WIN
BitsField NameDescriptionTypeReset
31:13RESERVEDR0x0 0000
12:0RDWRLVLINC_RMP_WINIncremental leveling ramp window in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device.RW0x0000
Table 15-134 EMIF_READ_WRITE_LEVELING_RAMP_CONTROL
Address Offset0x0000 00D8
Physical Address0x4C00 00D8InstanceEMIF1
DescriptionRead/write leveling ramp control register
TypeRW
313029282726252423222120191817161514131211109876543210
RDWRLVL_ENRDWRLVLINC_RMP_PRERDLVLINC_RMP_INTRDLVLGATEINC_RMP_INTWRLVLINC_RMP_INT
BitsField NameDescriptionTypeReset
31RDWRLVL_ENRead-Write Leveling enable. Set 1 to enable leveling. Set 0 to disable leveling.RW0
30:24RDWRLVLINC_RMP_PREIncremental leveling pre-scalar in number of refresh periods during ramp window. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device.RW0x00
23:16RDLVLINC_RMP_INTIncremental read data eye training interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental read data eye training during ramp window. A value of 0 will disable incremental read data eye training.NOTE: Incremental leveling is not supported on this device.RW0x00
15:8RDLVLGATEINC_RMP_INTIncremental read DQS gate training interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental read DQS gate training during ramp window. A value of 0 will disable incremental read DQS gate training.NOTE: Incremental leveling is not supported on this device.RW0x00
7:0WRLVLINC_RMP_INTIncremental write leveling interval during ramp window. Number of RDWRLVLINC_RMP_PRE intervals between incremental write leveling during ramp window. A value of 0 will disable incremental write leveling.NOTE: Incremental leveling is not supported on this device.RW0x00
Table 15-135 EMIF_READ_WRITE_LEVELING_CONTROL
Address Offset0x0000 00DC
Physical Address0x4C00 00DCInstanceEMIF1
DescriptionRead/write leveling control register
TypeRW
313029282726252423222120191817161514131211109876543210
RDWRLVLFULL_STARTRDWRLVLINC_PRERDLVLINC_INTRDLVLGATEINC_INTWRLVLINC_INT
BitsField NameDescriptionTypeReset
31RDWRLVLFULL_STARTFull leveling trigger. Writing a 1 to this field triggers full read and write leveling. This bit will self clear to 0.RW0
30:24RDWRLVLINC_PREIncremental leveling pre-scalar in number of refresh periods. The value programmed is minus one the required value. Refresh period is defined by REFRESH_RATE in EMIF_SDRAM_REFRESH_CONTROL register. NOTE: Incremental leveling is not supported on this device.RW0x00
23:16RDLVLINC_INTIncremental read data eye training interval. Number of RDWRLVLINC_PRE intervals between incremental read data eye training. A value of 0 will disable incremental read data eye training. NOTE: Incremental leveling is not supported on this device.RW0x00
15:8RDLVLGATEINC_INTIncremental read DQS gate training interval. Number of RDWRLVLINC_PRE intervals between incremental read DQS gate training. A value of 0 will disable incremental read DQS gate training. NOTE: Incremental leveling is not supported on this device.RW0x00
7:0WRLVLINC_INTIncremental write leveling interval. Number of RDWRLVLINC_PRE intervals between incremental write leveling. A value of 0 will disable incremental write leveling. NOTE: Incremental leveling is not supported on this device.RW0x00
Table 15-136 EMIF_DDR_PHY_CONTROL_1
Address Offset0x0000 00E4
Physical Address0x4C00 00E4InstanceEMIF1
DescriptionPHY control register 1
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRDLVL_MASKRDLVLGATE_MASKWRLVL_MASKRESERVEDPHY_HALF_DELAYSPHY_CLK_STALL_LEVELPHY_DIS_CALIB_RSTPHY_INVERT_CLKOUTPHY_DLL_LOCK_DIFFPHY_FAST_DLL_LOCKRESERVEDREAD_LATENCY
BitsField NameDescriptionTypeReset
31:28RESERVEDReservedRW0x0
27RDLVL_MASKWriting a 1 to this field will mask read data eye training during full leveling command, plus drives reg_phy_use_rd_data_eye_level control low to allow user to use programmed ratio values. RW0
26RDLVLGATE_MASKWriting a 1 to this field will mask dqs gate training during full leveling command, plus drives reg_phy_use_rd_dqs_level control low to allow user to use programmed ratio values. RW0
25WRLVL_MASKWriting a 1 to this field will mask write leveling training during full leveling command, plus drives reg_phy_use_wr_level control low to allow user to use programmed ratio values. RW0
24:22RESERVEDReservedRW0x0
21PHY_HALF_DELAYSAdjust slave delay line delays to support 2× mode
1: 2× mode (MDLL clock is half the rate of PHY)
0: 1× mode (MDLL clock rate is same as PHY)		RW0
20PHY_CLK_STALL_LEVELEnable variable idle value for delay lines. Enable during normal operations to avoid differential aging in the delay lines.RW0
19PHY_DIS_CALIB_RSTDisable the dll_calib (internally generated) signal from resetting the Read Capture FIFO pointers and portions of data PHYs. Debug only.
Note: dll_calib is generated by
1. EMIF_MISC_REG[0] DLL_CALIB_OS set to 1,or
2. by the PHY when it detects that the clock frequency variation has exceeded the bounds set by PHY_DLL_LOCK_DIFF or
3. periodically throughout the leveling process.		RW0
18PHY_INVERT_CLKOUTInverts the polarity of DRAM clock.
0: core clock is passed on to DRAM
1: inverted core clock is passed on to DRAM		RW0
17:10PHY_DLL_LOCK_DIFFThe maximum number of delay line taps variation while maintaining the master DLL lock. When the PHY is in locked state and the variation on the clock exceeds the variation indicated by this field, the lock signal is de-asserted and a dll_calib signal is generated. To prevent the dll_calib signal from being asserted in the middle of traffic when the clock jitter exceeds the variation, this register needs to be set to a value which will ensure that the lock will not be lost. Recommended value is 16.RW0x02
9PHY_FAST_DLL_LOCKControls master DLL to lock fast or average logic must be part of locking process. Set to 1 before OPP transition commences, and set back to 0 after OPP transition completes.
1: MDLL lock is asserted based on single sample
0: MDLL lock is asserted based on average of 16 samples.		RW0
8:5RESERVEDReservedRW0x00
4:0READ_LATENCYThis field defines the read latency for the read data from SDRAM in number of DDR clock cycles. This field is used by the EMIF as well as the PHY. READ_LATENCY = RL + reg_phy_rdc_we_to_re -1. EMIF uses above equation to calculate reg_phy_rdc_we_to_re and forward it to the PHY. For DDR3, the true RL is used, not the decoded value. See JEDEC spec.RW0x01E
Table 15-137 EMIF_DDR_PHY_CONTROL_1_SHADOW
Address Offset0x0000 00E8
Physical Address0x4C00 00E8InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDRDLVL_MASK_SHDWRDLVLGATE_MASK_SHDWWRLVL_MASK_SHDWRESERVEDPHY_HALF_DELAYS_SHDWPHY_CLK_STALL_LEVEL_SHDWPHY_DIS_CALIB_RST_SHDWPHY_INVERT_CLKOUT_SHDWPHY_DLL_LOCK_DIFF_SHDWPHY_FAST_DLL_SHDWRESERVEDREAD_LATENCY_SHDW
BitsField NameDescriptionTypeReset
31:28RESERVEDReservedRW0x0
27RDLVL_MASK_SHDWShadow field for RDLVL_MASKRW0
26RDLVLGATE_MASK_SHDWShadow field for RDLVLGATE_MASKRW0
25WRLVL_MASK_SHDWShadow field for WRLVL_MASKRW0
24:22RESERVEDReservedRW0x0
21PHY_HALF_DELAYS_SHDWShadow field for PHY_HALF_DELAYSRW0
20PHY_CLK_STALL_LEVEL_SHDWShadow field for PHY_CLK_STALL_LEVELRW0
19PHY_DIS_CALIB_RST_SHDWShadow field for PHY_DIS_CALIB_RSTRW0
18PHY_INVERT_CLKOUT_SHDWShadow field for PHY_INVERT_CLKOUTRW0
17:10PHY_DLL_LOCK_DIFF_SHDWShadow field for PHY_DLL_LOCK_DIFFRW0x00
9PHY_FAST_DLL_SHDWShadow field for PHY_FAST_DLLRW0
8:5RESERVEDReservedRW0x00
4:0READ_LATENCY_SHDWShadow field for READ_LATENCYRW0x000
Table 15-138 EMIF_DDR_PHY_CONTROL_2
Address Offset0x0000 00EC
Physical Address0x4C00 00ECInstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVED
BitsField NameDescriptionTypeReset
31:0RESERVEDReservedRW0x0
Table 15-139 EMIF_PRIORITY_TO_CLASS_OF_SERVICE_MAPPING
Address offset0x0000 0100
Physical Address0x4C00 0100InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
PRI_COS_MAP_ENRESERVEDPRI_7_COSPRI_6_COSPRI_5_COSPRI_4_COSPRI_3_COSPRI_2_COSPRI_1_COSPRI_0_COS
BitsField NameDescriptionTypeReset
31PRI_COS_MAP_EN

Set 1 to enable priority to class of service mapping. Set 0 to disable mapping.

RW0x0
30:16RESERVEDR0x0
15:14PRI_7_COS

Class of service for commands with priority of 7. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3.

RW0x0
13:12PRI_6_COS

Class of service for commands with priority of 6. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3.

RW0x0
11:10PRI_5_COS

Class of service for commands with priority of 5. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3.

RW0x0
9:8PRI_4_COS

Class of service for commands with priority of 4. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3.

RW0x0
7:6PRI_3_COS

Class of service for commands with priority of 3. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3.

RW0x0
5:4PRI_2_COS

Class of service for commands with priority of 2. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3.

RW0x0
3:2PRI_1_COS

Class of service for commands with priority of 1. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3.

RW0x0
1:0PRI_0_COS

Class of service for commands with priority of 0. Value can be 1, 2, or 3. Setting a value of 0 will have similar effects as a value of 3.

RW0x0
Table 15-140 EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_1_MAPPING
Address offset0x0000 0104
Physical Address0x4C00 0104InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
CONNID_COS_1_MAP_ENCONNID_1_COS_1MSK_1_COS_1CONNID_2_COS_1MSK_2_COS_1CONNID_3_COS_1MSK_3_COS_1
BitsField NameDescriptionTypeReset
31CONNID_COS_1_MAP_EN

Set 1 to enable Connection ID to class of service 1 mapping. Set 0 to disable mapping.

RW0x0
30:23CONNID_1_COS_1

Connection ID value 1 for class of service 1.

RW0x0
22:20MSK_1_COS_1

Mask for Connection ID value 1 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0. Value of 4 will mask Connection ID bits 3:0. Value of 5 will mask Connection ID bits 4:0. Value of 6 will mask Connection ID bits 5:0. Value of 7 will mask Connection ID bits 6:0.

RW0x0
19:12CONNID_2_COS_1

Connection ID value 2 for class of service 1.

RW0x0
11:10MSK_2_COS_1

Mask for Connection ID value 2 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0.

RW0x0
9:2CONNID_3_COS_1

Connection ID value 3 for class of service 1.

RW0x0
1:0MSK_3_COS_1

Mask for Connection ID value 3 for class of service 1. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0.

RW0x0
Table 15-141 EMIF_CONNECTION_ID_TO_CLASS_OF_SERVICE_2_MAPPING
Address offset0x0000 0108
Physical Address0x4C00 0108InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
CONNID_COS_2_MAP_ENCONNID_1_COS_2MSK_1_COS_2CONNID_2_COS_2MSK_2_COS_2CONNID_3_COS_2MSK_3_COS_2
BitsField NameDescriptionTypeReset
31CONNID_COS_2_MAP_EN

Set 1 to enable Connection ID to class of service 2 mapping. Set 0 to disable mapping.

RW0x0
30:23CONNID_1_COS_2

Connection ID value 1 for class of service 2.

RW0x0
22:20MSK_1_COS_2

Mask for Connection ID value 1 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0. Value of 4 will mask Connection ID bits 3:0. Value of 5 will mask Connection ID bits 4:0. Value of 6 will mask Connection ID bits 5:0. Value of 7 will mask Connection ID bits 6:0.

RW0x0
19:12CONNID_2_COS_2

Connection ID value 2 for class of service 2.

RW0x0
11:10MSK_2_COS_2

Mask for Connection ID value 2 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0.

RW0x0
9:2CONNID_3_COS_2

Connection ID value 3 for class of service 2.

RW0x0
1:0MSK_3_COS_2

Mask for Connection ID value 3 for class of service 2. Value of 0 will disable masking. Value of 1 will mask Connection ID bit 0. Value of 2 will mask Connection ID bits 1:0. Value of 3 will mask Connection ID bits 2:0.

RW0x0
Table 15-142 EMIF_ECC_CTRL_REG
Address offset0x4C00 0110
Physical Address0x4C00 0110InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
REG_ECC_ENREG_ECC_ADDR_RGN_PROTRESERVEDREG_ECC_ADDR_RGN_2_ENREG_ECC_ADDR_RGN_1_EN
BitsField NameDescriptionTypeReset
31REG_ECC_EN

Set 1 to enable ECC. Set 0 to disable ECC.

RW0x0
30REG_ECC_ADDR_RGN_PROT

Setting this field to 1 and reg_ecc_en to a 1 will enable ECC calculation for accesses within the address ranges and disable ECC calculation for accesses outside the address ranges. Setting this field to 0 and reg_ecc_en to a 1 will disable ECC calculation for accesses within the address ranges and enable ECC calculation for accesses outside the address ranges. The address ranges can be specified using the ECC Address Range 1 and 2 registers.

RW0x0
29:2RESERVEDR0x0
1REG_ECC_ADDR_RGN_2_EN

Set 1 to enable ECC address range 2. Set 0 to disable ECC address range 2.

RW0x0
0REG_ECC_ADDR_RGN_1_EN

Set 1 to enable ECC address range 1. Set 0 to disable ECC address range 1.

RW0x0
Table 15-143 EMIF_ECC_ADDRESS_RANGE_1
Address offset0x4C00 0114
Physical Address0x4C00 0114InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
REG_ECC_END_ADDR_1REG_ECC_STRT_ADDR_1
BitsField NameDescriptionTypeReset
31:16REG_ECC_END_ADDR_1

End address[32:17] for ECC address range 1. If this bit field is set to 0x1000, this indicates that the SDRAM physical end address on which the ECC applies is 0x1000 FFFF. If this bit field is set to 0x0FFF the physical end address on which the ECC applies is 0x0FFF FFFF. This bit field controls only the 16 MSbs of the physical end address of the ECC protected range. The other 16 LSbs are always 0xFFFF.

RW0x0
15:0REG_ECC_STRT_ADDR_1

Start address[32:17] for ECC address range 1. If this bit field is set to 0x0000, this indicates that the SDRAM physical start address on which the ECC applies is 0x0000 0000. This bit field controls only the 16 MSbs of the physical start address of the ECC protected range. The other 16 LSbs are always 0x0000.

RW0x0
Table 15-144 EMIF_ECC_ADDRESS_RANGE_2
Address offset0x4C00 0118
Physical Address0x4C00 0118InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
REG_ECC_END_ADDR_2REG_ECC_STRT_ADDR_2
BitsField NameDescriptionTypeReset
31:16REG_ECC_END_ADDR_2

End address[32:17] for ECC address range 2. If this bit field is set to 0x1000, this indicates that the SDRAM physical end address on which the ECC applies is 0x1000 FFFF. If this bit field is set to 0x0FFF the physical end address on which the ECC applies is 0x0FFF FFFF. This bit field controls only the 16 MSbs of the physical end address of the ECC protected range. The other 16 LSbs are always 0xFFFF.

RW0x0
15:0REG_ECC_STRT_ADDR_2

Start address[32:17] for ECC address range 2. If this bit field is set to 0x0000, this indicates that the SDRAM physical start address on which the ECC applies is 0x0000 0000. This bit field controls only the 16 MSbs of the physical start address of the ECC protected range. The other 16 LSbs are always 0x0000.

RW0x0
Table 15-145 EMIF_READ_WRITE_EXECUTION_THRESHOLD
Address Offset0x0000 0120
Physical Address0x4C00 0120InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
MFLAG_OVERRIDERESERVEDWR_THRSHRESERVEDRD_THRSH
BitsField NameDescriptionTypeReset
31MFLAG_OVERRIDEMflag override.RW0
0x0: Use MFLAG
0x1: Use Priority Class of Service
30:13RESERVEDReservedR0x0000
12:8WR_THRSHWrite Threshold. Number of SDRAM write bursts after which the EMIF arbitration will switch to executing read commands. The value programmed is always minus one the required numberRW0x03
7:5RESERVEDReservedR0x0
4:0RD_THRSHRead threshold. Number of SDRAM read bursts after which the EMIF arbitration will switch to executing write commands. The value that is programmed is always minus one the required numberR0x05
Table 15-146 EMIF_COS_CONFIG
Address Offset0x0000 0124
Physical Address0x4C00 0124InstanceEMIF1
DescriptionPriority Raise Counter Register.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDCOS_COUNT_1COS_COUNT_2PR_OLD_COUNT
BitsField NameDescriptionTypeReset
31:24RESERVEDR0x00
23:16COS_COUNT_1Priority Raise Counter for class of service 1. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the class of service 1 commands in the Command FIFO. A value of N will be equal to N x 16 clocks.RW0xFF
15:8COS_COUNT_2Priority Raise Counter for class of service 2. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the class of service 2 commands in the Command FIFO. A value of N will be equal to N x 16 clocks.RW0xFF
7:0PR_OLD_COUNTPriority Raise Old Counter. Number of EMIF_FICLK cycles after which the EMIF momentarily raises the priority of the oldest command in the Command FIFO. A value of N will be equal to N x 16 clocks.RW0xFF
Table 15-147 EMIF_1B_ECC_ERR_CNT
Address offset0x130
Physical Address0x4C00 0130InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
REG_1B_ECC_ERR_CNT
BitsField NameDescriptionTypeReset
31:0REG_1B_ECC_ERR_CNT

32 bit counter that displays number of 1-bit ECC errors. Writing a value will decrement the count by that value. For example, if the count is 0x1234_ABF3, writing 0x1234_ABF3 to this register will clear it.

RW0x0
Table 15-148 EMIF_1B_ECC_ERR_THRSH
Address offset0x134
Physical Address0x4C00 0134InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
REG_1B_ECC_ERR_THRSHRESERVEDREG_1B_ECC_ERR_WIN
BitsField NameDescriptionTypeReset
31:24REG_1B_ECC_ERR_THRSH

1-bit ECC error threshold. The EMIF will generate an interrupt when the 1-bit ECC error count is greater than or equal to this threshold. A value of 0 will disable the generation of the interrupt.

RW0x0
23:16RESERVEDR0x0
15:0REG_1B_ECC_ERR_WIN

1-bit ECC error window in number of refresh periods. The EMIF will generate an interrupt when the 1-bit ECC error count is equal to or greater than the threshold within this window. A value of 0 will disable the window. Refresh period is defined by EMIF_SDRAM_REFRESH_CONTROL[15:0] REFRESH_RATE. The software can set this bitfield to 0x0 to reset the internal counter.

RW0x0
Table 15-149 EMIF_1B_ECC_ERR_DIST_1
Address offset0x138
Physical Address0x4C00 0138InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
REG_1B_ECC_ERR_DIST_1
BitsField NameDescriptionTypeReset
31:0REG_1B_ECC_ERR_DIST_1

1-bit ECC error distribution over data bus bit 31:0. A value of 1 on a bit indicates 1-bit error on the corresponding bit on the data bus. Writing a 1 to any bit will clear that bit. Writing a 0 has no effect.

RW0x0
Table 15-150 EMIF_1B_ECC_ERR_ADDR_LOG
Address offset0x13C
Physical Address0x4C00 013CInstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
REG_1B_ECC_ERR_ADDR
BitsField NameDescriptionTypeReset
31:0REG_1B_ECC_ERR_ADDR

1-bit ECC error address. Most significant bits of the starting address(es) related to the SDRAM reads that had a 1-bit ECC error. This field displays up to four addresses logged in the 4 deep address logging FIFO. Writing a 0x1 will pop one element of the FIFO. Writing a 0x2 will pop all elements of the FIFO. Writing any other alue will have no effect.

RW0x0
Table 15-151 EMIF_2B_ECC_ERR_ADDR_LOG
Address offset0x140
Physical Address0x4C00 0140InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
REG_2B_ECC_ERR_ADDR
BitsField NameDescriptionTypeReset
31:0REG_2B_ECC_ERR_ADDR

2-bit ECC error address. Most significant bits of the starting address of the first SDRAM burst that had the 2-bit ECC error. Writing a 1 will clear this field. Writing any other value has no effect.

RW0x0
Table 15-152 EMIF_PHY_STATUS_1
Address Offset0x0000 0144
Physical Address0x4C00 0144InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_PHY_CTRL_DLL_SLAVE_VALUERESERVEDPHY_REG_STATUS_DLL_LOCKRESERVEDPHY_REG_PHY_CTRL_DLL_LOCK
BitsField NameDescriptionTypeReset
31:30RESERVEDR0x0
29:12PHY_REG_PHY_CTRL_DLL_SLAVE_VALUEDLL Slave ValueR0x0
11:9RESERVEDR0x0
8:4PHY_REG_STATUS_DLL_LOCKLock Status for Data DLLsR0x0
3:2RESERVEDR0x0
1:0PHY_REG_PHY_CTRL_DLL_LOCKLock Status for Command DLLsR0x0
Table 15-153 EMIF_PHY_STATUS_2
Address Offset0x0000 0148
Physical Address0x4C00 0148InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
PHY_REG_STATUS_DLL_SLAVE_VALUE_LO
BitsField NameDescriptionTypeReset
31:0PHY_REG_STATUS_DLL_SLAVE_VALUE_LOBits 31:0 of Phy_reg_status_dll_slave_valueR0x0
Table 15-154 EMIF_PHY_STATUS_3
Address Offset0x0000 014C
Physical Address0x4C00 014CInstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDFIFO_RDPTRRESERVEDPHY_REG_STATUS_DLL_SLAVE_VALUE_HI
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:16PHY_REG_RDFIFO_RDPTRRead FIFO Read PointerR0x0
15:13RESERVEDR0x0
12:0PHY_REG_STATUS_DLL_SLAVE_VALUE_HIBits 44:32 of Phy_reg_status_dll_slave_valueR0x0
Table 15-155 EMIF_PHY_STATUS_4
Address Offset0x0000 0150
Physical Address0x4C00 0150InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_GATELVL_FSMRESERVEDPHY_REG_RDFIFO_WRPTR
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:16PHY_REG_GATELVL_FSMGate Levelling FSMR0x0
15RESERVEDR0x0
14:0PHY_REG_RDFIFO_WRPTRRead FIFO Write PointerR0x0
Table 15-156 EMIF_PHY_STATUS_5
Address Offset0x0000 0154
Physical Address0x4C00 0154InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_LEVEL_FSM
BitsField NameDescriptionTypeReset
31:20RESERVEDR0x0
19:0PHY_REG_RD_LEVEL_FSMRead Levelling FSMR0x0
Table 15-157 EMIF_PHY_STATUS_6
Address Offset0x0000 0158
Physical Address0x4C00 0158InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_LEVEL_FSM
BitsField NameDescriptionTypeReset
31:15RESERVEDR0x0
14:0PHY_REG_WR_LEVEL_FSMWritel Levelling FSMR0x0
Table 15-158 EMIF_PHY_STATUS_7
Address Offset0x0000 015C
Physical Address0x4C00 015CInstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_DQS_RATIO1RESERVEDPHY_REG_RDLVL_DQS_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RDLVL_DQS_RATIO1Read levelling DQS ratio1R0x0
15:10RESERVEDR0x0
9:0PHY_REG_RDLVL_DQS_RATIO0Read levelling DQS ratio0R0x0
Table 15-159 EMIF_PHY_STATUS_8
Address Offset0x0000 0160
Physical Address0x4C00 0160InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_DQS_RATIO3RESERVEDPHY_REG_RDLVL_DQS_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RDLVL_DQS_RATIO3Read levelling DQS ratio3R0x0
15:10RESERVEDR0x0
9:0PHY_REG_RDLVL_DQS_RATIO2Read levelling DQS ratio2R0x0
Table 15-160 EMIF_PHY_STATUS_9
Address Offset0x0000 0164
Physical Address0x4C00 0164InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_DQS_RATIO5RESERVEDPHY_REG_RDLVL_DQS_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RDLVL_DQS_RATIO5Read Levelling DQS ratio5R0x0
15:10RESERVEDR0x0
9:0PHY_REG_RDLVL_DQS_RATIO4Read Levelling DQS ratio4R0x0
Table 15-161 EMIF_PHY_STATUS_10
Address Offset0x0000 0168
Physical Address0x4C00 0168InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_DQS_RATIO7RESERVEDPHY_REG_RDLVL_DQS_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RDLVL_DQS_RATIO7Read levelling DQS ratio7R0x0
15:10RESERVEDR0x0
9:0PHY_REG_RDLVL_DQS_RATIO6Read levelling DQS ratio6R0x0
Table 15-162 EMIF_PHY_STATUS_11
Address Offset0x0000 016C
Physical Address0x4C00 016CInstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_DQS_RATIO9RESERVEDPHY_REG_RDLVL_DQS_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RDLVL_DQS_RATIO9Read levelling DQS ratio9R0x0
15:10RESERVEDR0x0
9:0PHY_REG_RDLVL_DQS_RATIO8Read levelling DQS ratio8R0x0
Table 15-163 EMIF_PHY_STATUS_12
Address Offset0x0000 0170
Physical Address0x4C00 0170InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO1RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO0
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_RDLVL_FIFOWEIN_RATIO1Read levelling FIFO Write Enable Ratio1R0x0
15:11RESERVEDR0x0
10:0PHY_REG_RDLVL_FIFOWEIN_RATIO0Read levelling FIFO Write Enable Ratio0R0x0
Table 15-164 EMIF_PHY_STATUS_13
Address Offset0x0000 0174
Physical Address0x4C00 0174InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO3RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO2
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_RDLVL_FIFOWEIN_RATIO3Read levelling FIFO Write Enable Ratio3R0x0
15:11RESERVEDR0x0
10:0PHY_REG_RDLVL_FIFOWEIN_RATIO2Read levelling FIFO Write Enable Ratio2R0x0
Table 15-165 EMIF_PHY_STATUS_14
Address Offset0x0000 0178
Physical Address0x4C00 0178InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO5RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO4
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_RDLVL_FIFOWEIN_RATIO5Read levelling FIFO Write Enable Ratio5R0x0
15:11RESERVEDR0x0
10:0PHY_REG_RDLVL_FIFOWEIN_RATIO4Read levelling FIFO Write Enable Ratio4R0x0
Table 15-166 EMIF_PHY_STATUS_15
Address Offset0x0000 017C
Physical Address0x4C00 017CInstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO7RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO6
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_RDLVL_FIFOWEIN_RATIO7Read levelling FIFO Wrie Enable Ratio7R0x0
15:11RESERVEDR0x0
10:0PHY_REG_RDLVL_FIFOWEIN_RATIO6Read levelling FIFO Wrie Enable Ratio6R0x0
Table 15-167 EMIF_PHY_STATUS_16
Address Offset0x0000 0180
Physical Address0x4C00 0180InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO9RESERVEDPHY_REG_RDLVL_FIFOWEIN_RATIO8
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_RDLVL_FIFOWEIN_RATIO9Read levelling FIFO Write Enable Ratio9R0x0
15:11RESERVEDR0x0
10:0PHY_REG_RDLVL_FIFOWEIN_RATIO8Read levelling FIFO Write Enable Ratio8R0x0
Table 15-168 EMIF_PHY_STATUS_17
Address Offset0x0000 0184
Physical Address0x4C00 0184InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQ_RATIO1RESERVEDPHY_REG_WRLVL_DQ_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQ_RATIO1Write levelling DQ ratio1R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQ_RATIO0Write levelling DQ ratio0R0x0
Table 15-169 EMIF_PHY_STATUS_18
Address Offset0x0000 0188
Physical Address0x4C00 0188InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQ_RATIO3RESERVEDPHY_REG_WRLVL_DQ_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQ_RATIO3Write levelling DQ ratio3R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQ_RATIO2Write levelling DQ ratio2R0x0
Table 15-170 EMIF_PHY_STATUS_19
Address Offset0x0000 018C
Physical Address0x4C00 018CInstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQ_RATIO5RESERVEDPHY_REG_WRLVL_DQ_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQ_RATIO5Write levelling DQ ratio5R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQ_RATIO4Write levelling DQ ratio4R0x0
Table 15-171 EMIF_PHY_STATUS_20
Address Offset0x0000 0190
Physical Address0x4C00 0190InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQ_RATIO7RESERVEDPHY_REG_WRLVL_DQ_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQ_RATIO7Write levelling DQ ratio7R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQ_RATIO6Write levelling DQ ratio6R0x0
Table 15-172 EMIF_PHY_STATUS_21
Address Offset0x0000 0194
Physical Address0x4C00 0194InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQ_RATIO9RESERVEDPHY_REG_WRLVL_DQ_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQ_RATIO9Write levelling DQ ratio9R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQ_RATIO8Write levelling DQ ratio8R0x0
Table 15-173 EMIF_PHY_STATUS_22
Address Offset0x0000 0198
Physical Address0x4C00 0198InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQS_RATIO1RESERVEDPHY_REG_WRLVL_DQS_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQS_RATIO1Write levelling DQS ratio 1R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQS_RATIO0Write levelling DQS ratio 0R0x0
Table 15-174 EMIF_PHY_STATUS_23
Address Offset0x0000 019C
Physical Address0x4C00 019CInstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQS_RATIO3RESERVEDPHY_REG_WRLVL_DQS_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQS_RATIO3Write levelling DQS ratio3R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQS_RATIO2Write levelling DQS ratio2R0x0
Table 15-175 EMIF_PHY_STATUS_24
Address Offset0x0000 01A0
Physical Address0x4C00 01A0InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQS_RATIO5RESERVEDPHY_REG_WRLVL_DQS_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQS_RATIO5Write levelling DQS ratio5R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQS_RATIO4Write levelling DQS ratio4R0x0
Table 15-176 EMIF_PHY_STATUS_25
Address Offset0x0000 01A4
Physical Address0x4C00 01A4InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQS_RATIO7RESERVEDPHY_REG_WRLVL_DQS_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQS_RATIO7Write levelling DQS ratio7R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQS_RATIO6Write levelling DQS ratio6R0x0
Table 15-177 EMIF_PHY_STATUS_26
Address Offset0x0000 01A8
Physical Address0x4C00 01A8InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WRLVL_DQS_RATIO9RESERVEDPHY_REG_WRLVL_DQS_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WRLVL_DQS_RATIO9Write levelling DQS ratio9R0x0
15:10RESERVEDR0x0
9:0PHY_REG_WRLVL_DQS_RATIO8Write levelling DQS ratio8R0x0
Table 15-178 EMIF_PHY_STATUS_27
Address Offset0x0000 01AC
Physical Address0x4C00 01ACInstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_PHY_CONTROL_MDLL_UNLOCK_STICKYRESERVEDPHY_REG_STATUS_MDLL_UNLOCK_STICKYPHY_REG_RDC_FIFO_RST_ERR_CNT
BitsField NameDescriptionTypeReset
31:30RESERVEDR0x0
29:28PHY_REG_PHY_CONTROL_MDLL_UNLOCK_STICKYPhy control MDLL unlock stickyR0x0
27:25RESERVEDR0x0
24:20PHY_REG_STATUS_MDLL_UNLOCK_STICKYPhy data MDLL unlock stickyR0x0
19:0PHY_REG_RDC_FIFO_RST_ERR_CNTRDC FIFO reset error countR0x0
Table 15-179 EMIF_PHY_STATUS_28
Address Offset0x0000 01B0
Physical Address0x4C00 01B0InstanceEMIF1
Description
TypeR
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_GATELVL_INC_FAILRESERVEDPHY_REG_WRLVL_INC_FAILRESERVEDPHY_REG_RDLVL_INC_FAILRESERVEDPHY_REG_FIFO_WE_IN_MIASALIGNED_STICKY
BitsField NameDescriptionTypeReset
31:29RESERVEDR0x0
28:24PHY_REG_GATELVL_INC_FAILGate levelling failure. NOTE: Incremental leveling is not supported on this device.R0x0
23:21RESERVEDR0x0
20:16PHY_REG_WRLVL_INC_FAILWrite levelling failure. NOTE: Incremental leveling is not supported on this device.R0x0
15:13RESERVEDR0x0
12:8PHY_REG_RDLVL_INC_FAILRead levelling failure. NOTE: Incremental leveling is not supported on this device.R0x0
7:5RESERVEDR0x0
4:0PHY_REG_FIFO_WE_IN_MIASALIGNED_STICKYFIFO write enable in misaligned stickyR0x0
Table 15-180 EMIF_EXT_PHY_CONTROL_1
Address Offset0x0000 0200
Physical Address0x4C00 0200InstanceEMIF1
DescriptionControl DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_CTRL_SLAVE_RATIO2PHY_REG_CTRL_SLAVE_RATIO1PHY_REG_CTRL_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:30RESERVEDR0x0
29:20PHY_REG_CTRL_SLAVE_RATIO2

The user programmable ratio value for address/command launch timing in PHY control macro 2. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.

Required for LPDDR2 only. Please check the device datasheet for supported DDR memory types.

RW0x40
19:10PHY_REG_CTRL_SLAVE_RATIO1

The user programmable ratio value for address/command launch timing in PHY control macro 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.

Set to:

  • 0x080 for PHY_INVERT_CLKOUT = 0
  • 0x100 for PHY_INVERT_CLKOUT = 1

Required for DDR2/DDR3 only. Please check the device datasheet for supported DDR memory types.

RW0x80
9:0PHY_REG_CTRL_SLAVE_RATIO0

The user programmable ratio value for address/command launch timing in PHY control macro 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.

Set to:

  • 0x080 for PHY_INVERT_CLKOUT = 0
  • 0x100 for PHY_INVERT_CLKOUT = 1

Required for DDR2/DDR3 only. Please check the device datasheet for supported DDR memory types.

RW0x80
Table 15-181 EMIF_EXT_PHY_CONTROL_1_SHADOW
Address Offset0x0000 0204
Physical Address0x4C00 0204InstanceEMIF1
DescriptionControl DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_1 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_CTRL_SLAVE_RATIO2PHY_REG_CTRL_SLAVE_RATIO1PHY_REG_CTRL_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:30RESERVEDR0x0
29:20PHY_REG_CTRL_SLAVE_RATIO2

The user programmable ratio value for address/command launch timing in PHY control macro 2. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.

Required for LPDDR2 only. Please check the device datasheet for supported DDR memory types.

RW0x40
19:10PHY_REG_CTRL_SLAVE_RATIO1

The user programmable ratio value for address/command launch timing in PHY control macro 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.

Set to:

  • 0x080 for PHY_INVERT_CLKOUT = 0
  • 0x100 for PHY_INVERT_CLKOUT = 1

Required for DDR2/DDR3 only. Please check the device datasheet for supported DDR memory types.

RW0x80
9:0PHY_REG_CTRL_SLAVE_RATIO0

The user programmable ratio value for address/command launch timing in PHY control macro 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.

Set to:

  • 0x080 for PHY_INVERT_CLKOUT = 0
  • 0x100 for PHY_INVERT_CLKOUT = 1

Required for DDR2/DDR3 only. Please check the device datasheet for supported DDR memory types.

RW0x80
Table 15-182 EMIF_EXT_PHY_CONTROL_2
Address Offset0x0000 0208
Physical Address0x4C00 0208InstanceEMIF1
DescriptionData macro 0, FIFO write enable (read DQS gate) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO1RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO1The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO0The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-183 EMIF_EXT_PHY_CONTROL_2_SHADOW
Address Offset0x0000 020C
Physical Address0x4C00 020CInstanceEMIF1
DescriptionData macro 0, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_2 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO1RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO1The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO0The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-184 EMIF_EXT_PHY_CONTROL_3
Address Offset0x0000 0210
Physical Address0x4C00 0210InstanceEMIF1
DescriptionData macro 1, FIFO write enable (read DQS gate) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO3RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO2
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO3The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO2The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-185 EMIF_EXT_PHY_CONTROL_3_SHADOW
Address Offset0x0000 0214
Physical Address0x4C00 0214InstanceEMIF1
DescriptionData macro 1, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_3 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO3RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO2
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO3The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO2The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-186 EMIF_EXT_PHY_CONTROL_4
Address Offset0x0000 0218
Physical Address0x4C00 0218InstanceEMIF1
DescriptionData macro 2, FIFO write enable (read DQS gate) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO5RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO4
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO5The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO4The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-187 EMIF_EXT_PHY_CONTROL_4_SHADOW
Address Offset0x0000 021C
Physical Address0x4C00 021CInstanceEMIF1
DescriptionData macro 2, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_4 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO5RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO4
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO5The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO4The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-188 EMIF_EXT_PHY_CONTROL_5
Address Offset0x0000 0220
Physical Address0x4C00 0220InstanceEMIF1
DescriptionData macro 3, FIFO write enable (read DQS gate) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO7RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO6
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO7The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO6The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-189 EMIF_EXT_PHY_CONTROL_5_SHADOW
Address Offset0x0000 0224
Physical Address0x4C00 0224InstanceEMIF1
DescriptionData macro 3, FIFO write enable (read DQS gate) DLL Slave Ratio Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_5 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO7RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO6
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO7The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO6The user programmable ratio value for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-190 EMIF_EXT_PHY_CONTROL_6
Address Offset0x0000 0228
Physical Address0x4C00 0228InstanceEMIF1
DescriptionECC Data macro, FIFO write enable (read DQS gate) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO9RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO8
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO9The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO8The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-191 EMIF_EXT_PHY_CONTROL_6_SHADOW
Address Offset0x0000 022C
Physical Address0x4C00 022CInstanceEMIF1
DescriptionECC Data macro, FIFO write enable (read DQS gate) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_6 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO9RESERVEDPHY_REG_FIFO_WE_SLAVE_RATIO8
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16PHY_REG_FIFO_WE_SLAVE_RATIO9The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:11RESERVEDR0x0
10:0PHY_REG_FIFO_WE_SLAVE_RATIO8The user programmable ratio value for the FIFO write enable slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-192 EMIF_EXT_PHY_CONTROL_7
Address Offset0x0000 0230
Physical Address0x4C00 0230InstanceEMIF1
DescriptionData macro 0, read DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO1RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO1The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO0The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-193 EMIF_EXT_PHY_CONTROL_7_SHADOW
Address Offset0x0000 0234
Physical Address0x4C00 0234InstanceEMIF1
DescriptionData macro 0, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_7 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO1RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO1The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO0The user programmable ratio value for the read DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-194 EMIF_EXT_PHY_CONTROL_8
Address Offset0x0000 0238
Physical Address0x4C00 0238InstanceEMIF1
DescriptionData macro 1, read DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO3RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO3The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO2The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-195 EMIF_EXT_PHY_CONTROL_8_SHADOW
Address Offset0x0000 023C
Physical Address0x4C00 023CInstanceEMIF1
DescriptionData macro 1, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_8 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO3RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO3The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO2The user programmable ratio value for the read DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-196 EMIF_EXT_PHY_CONTROL_9
Address Offset0x0000 0240
Physical Address0x4C00 0240InstanceEMIF1
DescriptionData macro 2, read DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO5RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO5The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO4The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-197 EMIF_EXT_PHY_CONTROL_9_SHADOW
Address Offset0x0000 0244
Physical Address0x4C00 0244InstanceEMIF1
DescriptionData macro 2, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_9 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO5RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO5The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO4The user programmable ratio value for the read DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-198 EMIF_EXT_PHY_CONTROL_10
Address Offset0x0000 0248
Physical Address0x4C00 0248InstanceEMIF1
DescriptionData macro 3, read DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO7RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO7The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO6The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-199 EMIF_EXT_PHY_CONTROL_10_SHADOW
Address Offset0x0000 024C
Physical Address0x4C00 024CInstanceEMIF1
DescriptionData macro 3, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_10 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO7RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO7The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO6The user programmable ratio value for the read DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-200 EMIF_EXT_PHY_CONTROL_11
Address Offset0x0000 0250
Physical Address0x4C00 0250InstanceEMIF1
DescriptionECC Data macro, read DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO9RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO9The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO8The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-201 EMIF_EXT_PHY_CONTROL_11_SHADOW
Address Offset0x0000 0254
Physical Address0x4C00 0254InstanceEMIF1
DescriptionECC Data macro, read DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_11 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO9RESERVEDPHY_REG_RD_DQS_SLAVE_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_RD_DQS_SLAVE_RATIO9The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_RD_DQS_SLAVE_RATIO8The user programmable ratio value for the read DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-202 EMIF_EXT_PHY_CONTROL_12
Address Offset0x0000 0258
Physical Address0x4C00 0258InstanceEMIF1
DescriptionData macro 0, write DQ (data) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO1RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO1The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO0The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-203 EMIF_EXT_PHY_CONTROL_12_SHADOW
Address Offset0x0000 025C
Physical Address0x4C00 025CInstanceEMIF1
DescriptionData macro 0, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_12 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO1RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO1The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO0The user programmable ratio value for the write DQ slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-204 EMIF_EXT_PHY_CONTROL_13
Address Offset0x0000 0260
Physical Address0x4C00 0260InstanceEMIF1
DescriptionData macro 1, write DQ (data) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO3RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO3The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO2The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-205 EMIF_EXT_PHY_CONTROL_13_SHADOW
Address Offset0x0000 0264
Physical Address0x4C00 0264InstanceEMIF1
DescriptionData macro 1, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_13 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO3RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO3The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO2The user programmable ratio value for the write DQ slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-206 EMIF_EXT_PHY_CONTROL_14
Address Offset0x0000 0268
Physical Address0x4C00 0268InstanceEMIF1
DescriptionData macro 2, write DQ (data) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO5RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO5The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO4The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-207 EMIF_EXT_PHY_CONTROL_14_SHADOW
Address Offset0x0000 026C
Physical Address0x4C00 026CInstanceEMIF1
DescriptionData macro 2, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_14 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO5RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO5The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO4The user programmable ratio value for the write DQ slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-208 EMIF_EXT_PHY_CONTROL_15
Address Offset0x0000 0270
Physical Address0x4C00 0270InstanceEMIF1
DescriptionData macro 3, write DQ (data) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO7RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO7The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO6The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-209 EMIF_EXT_PHY_CONTROL_15_SHADOW
Address Offset0x0000 0274
Physical Address0x4C00 0274InstanceEMIF1
DescriptionData macro 3, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_15 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO7RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO7The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO6The user programmable ratio value for the write DQ slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-210 EMIF_EXT_PHY_CONTROL_16
Address Offset0x0000 0278
Physical Address0x4C00 0278InstanceEMIF1
DescriptionECC Data macro, write DQ (data) DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO9RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO9The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO8The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-211 EMIF_EXT_PHY_CONTROL_16_SHADOW
Address Offset0x0000 027C
Physical Address0x4C00 027CInstanceEMIF1
DescriptionECC Data macro, write DQ (data) DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_16 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO9RESERVEDPHY_REG_WR_DATA_SLAVE_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DATA_SLAVE_RATIO9The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x40
15:10RESERVEDR0x0
9:0PHY_REG_WR_DATA_SLAVE_RATIO8The user programmable ratio value for the write DQ slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x40
Table 15-212 EMIF_EXT_PHY_CONTROL_17
Address Offset0x0000 0280
Physical Address0x4C00 0280InstanceEMIF1
DescriptionData macro 0, write DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO1RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO1The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO0The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-213 EMIF_EXT_PHY_CONTROL_17_SHADOW
Address Offset0x0000 0284
Physical Address0x4C00 0284InstanceEMIF1
DescriptionData macro 0, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_17 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO1RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO1The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO0The user programmable ratio value for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-214 EMIF_EXT_PHY_CONTROL_18
Address Offset0x0000 0288
Physical Address0x4C00 0288InstanceEMIF1
DescriptionData macro 1, write DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO3RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO3The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO2The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-215 EMIF_EXT_PHY_CONTROL_18_SHADOW
Address Offset0x0000 028C
Physical Address0x4C00 028CInstanceEMIF1
DescriptionData macro 1, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_18 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO3RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO3The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO2The user programmable ratio value for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-216 EMIF_EXT_PHY_CONTROL_19
Address Offset0x0000 0290
Physical Address0x4C00 0290InstanceEMIF1
DescriptionData macro 2, write DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO5RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO5The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO4The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-217 EMIF_EXT_PHY_CONTROL_19_SHADOW
Address Offset0x0000 0294
Physical Address0x4C00 0294InstanceEMIF1
DescriptionData macro 2, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_19 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO5RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO5The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO4The user programmable ratio value for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-218 EMIF_EXT_PHY_CONTROL_20
Address Offset0x0000 0298
Physical Address0x4C00 0298InstanceEMIF1
DescriptionData macro 3, write DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO7RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO7The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO6The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-219 EMIF_EXT_PHY_CONTROL_20_SHADOW
Address Offset0x0000 029C
Physical Address0x4C00 029CInstanceEMIF1
DescriptionData macro 3, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_20 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO7RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO7The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO6The user programmable ratio value for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-220 EMIF_EXT_PHY_CONTROL_21
Address Offset0x0000 02A0
Physical Address0x4C00 02A0InstanceEMIF1
DescriptionECC Data macro, write DQS DLL Slave Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO9RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO9The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO8The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-221 EMIF_EXT_PHY_CONTROL_21_SHADOW
Address Offset0x0000 02A4
Physical Address0x4C00 02A4InstanceEMIF1
DescriptionECC Data macro, write DQS DLL Slave Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_21 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO9RESERVEDPHY_REG_WR_DQS_SLAVE_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16PHY_REG_WR_DQS_SLAVE_RATIO9The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0PHY_REG_WR_DQS_SLAVE_RATIO8The user programmable ratio value for the write DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-222 EMIF_EXT_PHY_CONTROL_22
Address Offset0x0000 02A8
Physical Address0x4C00 02A8InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_IN_DELAYRESERVEDPHY_REG_CTRL_SLAVE_DELAY
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16PHY_REG_FIFO_WE_IN_DELAYThe user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1.RW0x80
15:9RESERVEDR0x0
8:0PHY_REG_CTRL_SLAVE_DELAYThe user programmable command delay value used when DLL_OVERRIDE = 1.RW0x80
Table 15-223 EMIF_EXT_PHY_CONTROL_22_SHADOW
Address Offset0x0000 02AC
Physical Address0x4C00 02ACInstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_FIFO_WE_IN_DELAYRESERVEDPHY_REG_CTRL_SLAVE_DELAY
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16PHY_REG_FIFO_WE_IN_DELAYThe user programmable FIFO write enable delay value used when DLL_OVERRIDE = 1.RW0x80
15:9RESERVEDR0x0
8:0PHY_REG_CTRL_SLAVE_DELAYThe user programmable command delay value used when DLL_OVERRIDE = 1.RW0x80
Table 15-224 EMIF_EXT_PHY_CONTROL_23
Address Offset0x0000 02B0
Physical Address0x4C00 02B0InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_DELAYRESERVEDPHY_REG_RD_DQS_SLAVE_DELAY
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16PHY_REG_WR_DQS_SLAVE_DELAYThe user programmable write DQS delay value used when DLL_OVERRIDE = 1.RW0x80
15:9RESERVEDR0x0
8:0PHY_REG_RD_DQS_SLAVE_DELAYThe user programmable read DQS delay value used when DLL_OVERRIDE = 1.RW0x80
Table 15-225 EMIF_EXT_PHY_CONTROL_23_SHADOW
Address Offset0x0000 02B4
Physical Address0x4C00 02B4InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDPHY_REG_WR_DQS_SLAVE_DELAYRESERVEDPHY_REG_RD_DQS_SLAVE_DELAY
BitsField NameDescriptionTypeReset
31:25RESERVEDR0x0
24:16PHY_REG_WR_DQS_SLAVE_DELAYThe user programmable write DQS delay value used when DLL_OVERRIDE = 1.RW0x80
15:9RESERVEDR0x0
8:0PHY_REG_RD_DQS_SLAVE_DELAYThe user programmable read DQS delay value used when DLL_OVERRIDE = 1.RW0x80
Table 15-226 EMIF_EXT_PHY_CONTROL_24
Address Offset0x0000 02B8
Physical Address0x4C00 02B8InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_DQ_OFFSET_HIRESERVEDREG_PHY_GATELVL_INIT_MODERESERVEDREG_PHY_USE_RANK0_DELAYSRESERVEDREG_PHY_WR_DATA_SLAVE_DELAY
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:24REG_PHY_DQ_OFFSET_HIThe user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY ECC data macro. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
23:17RESERVEDR0x0
16REG_PHY_GATELVL_INIT_MODEThe user programmable init ratio selection mode. Recommended value is 0x1.RW0x1
15:13RESERVEDR0x0
12REG_PHY_USE_RANK0_DELAYSDelay selection. Chip select 0 delay line ratios are used for all chip selects when set to 1. Each chip select uses its own delays when set to 0.RW0x0
11:9RESERVEDR0x0
8:0REG_PHY_WR_DATA_SLAVE_DELAYThe user programmable write DQ delay value used when DLL_OVERRIDE = 1.RW0x80
Table 15-227 EMIF_EXT_PHY_CONTROL_24_SHADOW
Address Offset0x0000 02BC
Physical Address0x4C00 02BCInstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_DQ_OFFSET_HIRESERVEDREG_PHY_GATELVL_INIT_MODERESERVEDREG_PHY_USE_RANK0_DELAYSRESERVEDREG_PHY_WR_DATA_SLAVE_DELAY
BitsField NameDescriptionTypeReset
31RESERVEDR0x0
30:24REG_PHY_DQ_OFFSET_HIThe user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY ECC data macro. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
23:17RESERVEDR0x0
16REG_PHY_GATELVL_INIT_MODEThe user programmable init ratio selection mode. Recommended value is 0x1.RW0x1
15:13RESERVEDR0x0
12REG_PHY_USE_RANK0_DELAYSDelay selection. Chip select 0 delay line ratios are used for all chip selects when set to 1. Each chip select uses its own delays when set to 0.RW0x0
11:9RESERVEDR0x0
8:0REG_PHY_WR_DATA_SLAVE_DELAYThe user programmable write DQ delay value used when DLL_OVERRIDE = 1.RW0x80
Table 15-228 EMIF_EXT_PHY_CONTROL_25
Address Offset0x0000 02C0
Physical Address0x4C00 02C0InstanceEMIF1
DescriptionDQ DLL Slave Ratio Offset Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_DQ_OFFSET3REG_PHY_DQ_OFFSET2REG_PHY_DQ_OFFSET1REG_PHY_DQ_OFFSET0
BitsField NameDescriptionTypeReset
31:28RESERVEDR0x0
27:21REG_PHY_DQ_OFFSET3The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 3. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
20:14REG_PHY_DQ_OFFSET2The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 2. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
13:7REG_PHY_DQ_OFFSET1The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 1. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
6:0REG_PHY_DQ_OFFSET0The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 0. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
Table 15-229 EMIF_EXT_PHY_CONTROL_25_SHADOW
Address Offset0x0000 02C4
Physical Address0x4C00 02C4InstanceEMIF1
DescriptionDQ DLL Slave Ratio Offset Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_25 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_DQ_OFFSET3REG_PHY_DQ_OFFSET2REG_PHY_DQ_OFFSET1REG_PHY_DQ_OFFSET0
BitsField NameDescriptionTypeReset
31:28RESERVEDR0x0
27:21REG_PHY_DQ_OFFSET3The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 3. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
20:14REG_PHY_DQ_OFFSET2The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 2. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
13:7REG_PHY_DQ_OFFSET1The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 1. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
6:0REG_PHY_DQ_OFFSET0The user programmable offset ratio value from write DQS to write DQ. This value is used for the write DQ slave DLL in PHY data macro 0. The ratio represents the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 (in addition to the write DQS delay) to get the delay value for the slave delay line.RW0x0
Table 15-230 EMIF_EXT_PHY_CONTROL_26
Address Offset0x0000 02C8
Physical Address0x4C00 02C8InstanceEMIF1
DescriptionData macro 0, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO1RESERVEDREG_PHY_GATELVL_INIT_RATIO0
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO1The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO0The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-231 EMIF_EXT_PHY_CONTROL_26_SHADOW
Address Offset0x0000 02CC
Physical Address0x4C00 02CCInstanceEMIF1
DescriptionData macro 0, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_26 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO1RESERVEDREG_PHY_GATELVL_INIT_RATIO0
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO1The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO0The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-232 EMIF_EXT_PHY_CONTROL_27
Address Offset0x0000 02D0
Physical Address0x4C00 02D0InstanceEMIF1
DescriptionData macro 1, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO3RESERVEDREG_PHY_GATELVL_INIT_RATIO2
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO3The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO2The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-233 EMIF_EXT_PHY_CONTROL_27_SHADOW
Address Offset0x0000 02D4
Physical Address0x4C00 02D4InstanceEMIF1
DescriptionData macro 1, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_27 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO3RESERVEDREG_PHY_GATELVL_INIT_RATIO2
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO3The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO2The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-234 EMIF_EXT_PHY_CONTROL_28
Address Offset0x0000 02D8
Physical Address0x4C00 02D8InstanceEMIF1
DescriptionData macro 2, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO5RESERVEDREG_PHY_GATELVL_INIT_RATIO4
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO5The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO4The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-235 EMIF_EXT_PHY_CONTROL_28_SHADOW
Address Offset0x0000 02DC
Physical Address0x4C00 02DCInstanceEMIF1
DescriptionData macro 2, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_28 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO5RESERVEDREG_PHY_GATELVL_INIT_RATIO4
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO5The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO4The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-236 EMIF_EXT_PHY_CONTROL_29
Address Offset0x0000 02E0
Physical Address0x4C00 02E0InstanceEMIF1
DescriptionData macro 3, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO7RESERVEDREG_PHY_GATELVL_INIT_RATIO6
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO7The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO6The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-237 EMIF_EXT_PHY_CONTROL_29_SHADOW
Address Offset0x0000 02E4
Physical Address0x4C00 02E4InstanceEMIF1
DescriptionData macro 3, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_29 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO7RESERVEDREG_PHY_GATELVL_INIT_RATIO6
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO7The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO6The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-238 EMIF_EXT_PHY_CONTROL_30
Address Offset0x0000 02E8
Physical Address0x4C00 02E8InstanceEMIF1
DescriptionECC Data macro, FIFO write enable (read DQS gate) DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO9RESERVEDREG_PHY_GATELVL_INIT_RATIO8
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO9The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO8The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-239 EMIF_EXT_PHY_CONTROL_30_SHADOW
Address Offset0x0000 02EC
Physical Address0x4C00 02ECInstanceEMIF1
DescriptionECC Data macro, FIFO write enable (read DQS gate) DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_30 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_GATELVL_INIT_RATIO9RESERVEDREG_PHY_GATELVL_INIT_RATIO8
BitsField NameDescriptionTypeReset
31:27RESERVEDR0x0
26:16REG_PHY_GATELVL_INIT_RATIO9The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x150
15:11RESERVEDR0x0
10:0REG_PHY_GATELVL_INIT_RATIO8The user programmable initialization ratio value used by the gate training finite state machine (hardware leveling) for the FIFO write enable slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x150
Table 15-240 EMIF_EXT_PHY_CONTROL_31
Address Offset0x0000 02F0
Physical Address0x4C00 02F0InstanceEMIF1
DescriptionData macro 0, write DQS DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO1RESERVEDREG_PHY_WRLVL_INIT_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO1The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO0The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-241 EMIF_EXT_PHY_CONTROL_31_SHADOW
Address Offset0x0000 02F4
Physical Address0x4C00 02F4InstanceEMIF1
DescriptionData macro 0, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_31 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO1RESERVEDREG_PHY_WRLVL_INIT_RATIO0
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO1The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO0The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 0, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-242 EMIF_EXT_PHY_CONTROL_32
Address Offset0x0000 02F8
Physical Address0x4C00 02F8InstanceEMIF1
DescriptionData macro 1, write DQS DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO3RESERVEDREG_PHY_WRLVL_INIT_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO3The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO2The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-243 EMIF_EXT_PHY_CONTROL_32_SHADOW
Address Offset0x0000 02FC
Physical Address0x4C00 02FCInstanceEMIF1
DescriptionData macro 1, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_32 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO3RESERVEDREG_PHY_WRLVL_INIT_RATIO2
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO3The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO2The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 1, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-244 EMIF_EXT_PHY_CONTROL_33
Address Offset0x0000 0300
Physical Address0x4C00 0300InstanceEMIF1
DescriptionData macro 2, write DQS DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO5RESERVEDREG_PHY_WRLVL_INIT_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO5The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO4The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-245 EMIF_EXT_PHY_CONTROL_33_SHADOW
Address Offset0x0000 0304
Physical Address0x4C00 0304InstanceEMIF1
DescriptionData macro 2, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_33 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO5RESERVEDREG_PHY_WRLVL_INIT_RATIO4
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO5The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO4The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 2, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-246 EMIF_EXT_PHY_CONTROL_34
Address Offset0x0000 0308
Physical Address0x4C00 0308InstanceEMIF1
DescriptionData macro 3, write DQS DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO7RESERVEDREG_PHY_WRLVL_INIT_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO7The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO6The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-247 EMIF_EXT_PHY_CONTROL_34_SHADOW
Address Offset0x0000 030C
Physical Address0x4C00 030CInstanceEMIF1
DescriptionData macro 3, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_34 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO7RESERVEDREG_PHY_WRLVL_INIT_RATIO6
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO7The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO6The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY data macro 3, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-248 EMIF_EXT_PHY_CONTROL_35
Address Offset0x0000 0310
Physical Address0x4C00 0310InstanceEMIF1
DescriptionECC Data macro, write DQS DLL Slave Init Ratio Register
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO9RESERVEDREG_PHY_WRLVL_INIT_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO9The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO8The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-249 EMIF_EXT_PHY_CONTROL_35_SHADOW
Address Offset0x0000 0314
Physical Address0x4C00 0314InstanceEMIF1
DescriptionECC Data macro, write DQS DLL Slave Init Ratio Shadow Register. Its value is loaded in register EMIF_EXT_PHY_CONTROL_35 on any frequency change.
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_WRLVL_INIT_RATIO9RESERVEDREG_PHY_WRLVL_INIT_RATIO8
BitsField NameDescriptionTypeReset
31:26RESERVEDR0x0
25:16REG_PHY_WRLVL_INIT_RATIO9The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro, chip select 1. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.
NOTE: Chip select 1 is not supported on this device.		RW0x0
15:10RESERVEDR0x0
9:0REG_PHY_WRLVL_INIT_RATIO8The user programmable initialization ratio value used by the write leveling finite state machine (hardware leveling) for the write DQS slave DLL in PHY ECC data macro, chip select 0. This is the fraction of a clock cycle in units of 256ths. In other words, the full-cycle tap value from the master DLL will be scaled by this number over 256 to get the delay value for the slave delay line.RW0x0
Table 15-250 EMIF_EXT_PHY_CONTROL_36
Address Offset0x0000 0318
Physical Address0x4C00 0318InstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_RDC_FIFO_RST_ERR_CNT_CLRREG_PHY_MDLL_UNLOCK_CLRREG_PHY_FIFO_WE_IN_MISALIGNED_CLRREG_PHY_WRLVL_NUM_OF_DQ0REG_PHY_GATELVL_NUM_OF_DQ0
BitsField NameDescriptionTypeReset
31:11RESERVEDR0x0
10REG_PHY_RDC_FIFO_RST_ERR_CNT_CLRClear/reset the phy_reg_rdc_fifo_rst_err_cnt, phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags. A value of 0x1 clears the flag. A value of 0x0 has no effect.RW0x0
9REG_PHY_MDLL_UNLOCK_CLRClears the phy_reg_status_mdll_unlock_sticky flag. A value of 0x1 clears the flag. A value of 0x0 has no effect.RW0x0
8REG_PHY_FIFO_WE_IN_MISALIGNED_CLRClears the phy_reg_fifo_we_in_misaligned_sticky status flag. A value of 0x1 clears the flag. A value of 0x0 has no effect.RW0x0
7:4REG_PHY_WRLVL_NUM_OF_DQ0Determines the number of samples for dq0_in for each ratio increment by the write leveling finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended.
Note: NOTE: In this case dq0_in represents all 8 DQ bits OR-ed together.
RW0x7
3:0REG_PHY_GATELVL_NUM_OF_DQ0Determines the number of samples for dq0_in for each ratio increment by the gate training finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended.
Note: NOTE: In this case dq0_in represents the corresponding DQS signal.
RW0x7
Table 15-251 EMIF_EXT_PHY_CONTROL_36_SHADOW
Address Offset0x0000 031C
Physical Address0x4C00 031CInstanceEMIF1
Description
TypeRW
313029282726252423222120191817161514131211109876543210
RESERVEDREG_PHY_RDC_FIFO_RST_ERR_CNT_CLRREG_PHY_MDLL_UNLOCK_CLRREG_PHY_FIFO_WE_IN_MISALIGNED_CLRREG_PHY_WRLVL_NUM_OF_DQ0REG_PHY_GATELVL_NUM_OF_DQ0
BitsField NameDescriptionTypeReset
31:11RESERVEDR0x0
10REG_PHY_RDC_FIFO_RST_ERR_CNT_CLRClear/reset the phy_reg_rdc_fifo_rst_err_cnt, phy_reg_rdfifo_wrptr and phy_reg_rdfifo_rdptr status flags. A value of 0x1 clears the flag. A value of 0x0 has no effect.RW0x0
9REG_PHY_MDLL_UNLOCK_CLRClears the phy_reg_status_mdll_unlock_sticky flag. A value of 0x1 clears the flag. A value of 0x0 has no effect.RW0x0
8REG_PHY_FIFO_WE_IN_MISALIGNED_CLRClears the phy_reg_fifo_we_in_misaligned_sticky status flag. A value of 0x1 clears the flag. A value of 0x0 has no effect.RW0x0
7:4REG_PHY_WRLVL_NUM_OF_DQ0Determines the number of samples for dq0_in for each ratio increment by the write leveling finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended.
Note: NOTE: In this case dq0_in represents all 8 DQ bits OR-ed together.
RW0x7
3:0REG_PHY_GATELVL_NUM_OF_DQ0Determines the number of samples for dq0_in for each ratio increment by the gate training finite state machine (hardware leveling). The minimum value supported is 3; however, the default setting of 7 is recommended.
Note: NOTE: In this case dq0_in represents the corresponding DQS signal.
RW0x7