SPRUHZ7K
August 2015 – April 2024
AM5706
,
AM5708
,
AM5716
,
AM5718
,
AM5718-HIREL
1
Preface
Support Resources
About This Manual
Information About Cautions and Warnings
Register, Field, and Bit Calls
Coding Rules
Flow Chart Rules
Export Control Notice
AM571x, AM570x MIPI® Disclaimer
Trademarks
1
Introduction
1.1
AM571x, AM570x Overview
1.2
AM571x, AM570x Environment
1.3
AM571x, AM570x Description
1.3.1
MPU Subsystem
1.3.2
DSP Subsystem
1.3.3
PRU-ICSS
1.3.4
IPU Subsystems
1.3.5
IVA-HD Subsystem
1.3.6
Display Subsystem
1.3.7
Video Processing Subsystem
1.3.8
Video Capture
1.3.9
3D GPU Subsystem
1.3.10
BB2D Subsystem
1.3.11
Camera Interface Subsystem
1.3.12
On-Chip Debug Support
1.3.13
Power, Reset, and Clock Management
1.3.14
On-Chip Memory
1.3.15
Memory Management
1.3.16
External Memory Interfaces
1.3.17
System and Connectivity Peripherals
1.3.17.1
System Peripherals
1.3.17.2
Media Connectivity Peripherals
1.3.17.3
Connectivity Peripherals
1.3.17.4
Audio Connectivity Peripherals
1.3.17.5
Serial Control Peripherals
1.4
AM571x, AM570x Family
1.5
AM571x, AM570x Device Identification
1.6
AM571x, AM570x Package Characteristics Overview
2
Memory Mapping
2.1
Introduction
2.2
L3_MAIN Memory Map
2.2.1
L3_INSTR Memory Map
2.3
L4 Memory Map
2.3.1
L4_CFG Memory Map
2.3.2
L4_WKUP Memory Map
2.3.3
L4_PER Memory Map
2.3.3.1
L4_PER1 Memory Map
2.3.3.2
L4_PER2 Memory Map
2.3.3.3
L4_PER3 Memory Map
2.4
MPU Memory Map
2.5
IPU Memory Map
2.6
DSP Memory Map
2.7
PRU-ICSS Memory Map
2.8
TILER View Memory Map
3
Power, Reset, and Clock Management
3.1
Device Power Management Introduction
3.1.1
Device Power-Management Architecture Building Blocks
3.1.1.1
Clock Management
3.1.1.1.1
Module Interface and Functional Clocks
3.1.1.1.2
62
3.1.1.1.3
Module-Level Clock Management
3.1.1.1.4
Clock Domain
3.1.1.1.5
Clock Domain-Level Clock Management
3.1.1.1.6
Clock Domain HW_AUTO Mode Sequences
3.1.1.1.7
Clock Domain Sleep/Wake-up
3.1.1.1.8
Clock Domain Dependency
3.1.1.1.8.1
Static Dependency
3.1.1.1.8.2
Dynamic Dependency
3.1.1.1.8.3
Wake-Up Dependency
3.1.1.2
Power Management
3.1.1.2.1
Power Domain
3.1.1.2.2
Module Logic and Memory Context
3.1.1.2.3
Power Domain Management
3.1.1.3
Voltage Management
3.1.1.3.1
Voltage Domain
3.1.1.3.2
Voltage Domain Management
3.1.1.3.3
AVS Overview
3.1.1.3.3.1
AVS Class 0 (SmartReflex™) Voltage Control
3.1.2
Power-Management Techniques
3.1.2.1
Standby Leakage Management
3.1.2.2
Dynamic Voltage and Frequency Scaling
3.1.2.3
Dynamic Power Switching
3.1.2.4
Adaptive Voltage Scaling
3.1.2.5
Adaptive Body Bias
3.1.2.6
87
3.1.2.7
SR3-APG (Automatic Power Gating)
3.1.2.8
Combining Power-Management Techniques
3.1.2.8.1
DPS Versus SLM
3.2
PRCM Subsystem Overview
3.2.1
Introduction
3.2.2
Power-Management Framework Features
3.3
PRCM Subsystem Environment
3.3.1
External Clock Signals
3.3.2
External Boot Signals
3.3.3
External Reset Signals
3.3.4
External Voltage Inputs
3.4
PRCM Subsystem Integration
3.4.1
Device Power-Management Layout
3.4.2
Power-Management Scheme, Reset, and Interrupt Requests
3.4.2.1
Power Domain
3.4.2.2
Resets
3.4.2.3
PRCM Interrupt Requests
3.4.2.4
105
3.5
Reset Management Functional Description
3.5.1
Overview
3.5.1.1
PRCM Reset Management Functional Description
3.5.1.1.1
Power-On Reset
3.5.1.1.2
Warm Reset
3.5.1.2
PRM Reset Management Functional Description
3.5.2
General Characteristics of Reset Signals
3.5.2.1
Scope
3.5.2.2
Occurrence
3.5.2.3
Source Type
3.5.2.4
Retention Type
3.5.3
Reset Sources
3.5.3.1
Global Reset Sources
3.5.3.2
Local Reset Sources
3.5.4
Reset Logging
3.5.5
Reset Domains
3.5.6
Reset Sequences
3.5.6.1
MPU Subsystem Power-On Reset Sequence
3.5.6.2
MPU Subsystem Warm Reset Sequence
3.5.6.3
MPU Subsystem Reset Sequence on Sleep and Wake-Up Transitions From RETENTION State
3.5.6.4
IVA Subsystem Power-On Reset Sequence
3.5.6.5
IVA Subsystem Software Warm Reset Sequence
3.5.6.6
DSP1 Subsystem Power-On Reset Sequence
3.5.6.7
DSP1 Subsystem Software Warm Reset Sequence
3.5.6.8
IPU1 Subsystem Power-On Reset Sequence
3.5.6.9
IPU1 Subsystem Software Warm Reset Sequence
3.5.6.10
IPU2 Subsystem Power-On Reset Sequence
3.5.6.11
IPU2 Subsystem Software Warm Reset Sequence
3.5.6.12
Global Warm Reset Sequence
3.6
Clock Management Functional Description
3.6.1
Overview
3.6.2
External Clock Inputs
3.6.2.1
FUNC_32K_CLK Clock
3.6.2.2
High-Frequency System Clock Input
3.6.2.3
External Reference Clock Input
3.6.3
Internal Clock Sources and Generators
3.6.3.1
PRM Clock Source
3.6.3.2
CM Clock Source
3.6.3.2.1
CM_CORE_AON Clock Generator
3.6.3.2.2
CM_CORE_AON_CLKOUTMUX Overview
3.6.3.2.3
CM_CORE_AON_TIMER Overview
3.6.3.2.4
CM_CORE_AON_MCASP Overview
3.6.3.3
Generic DPLL Overview
3.6.3.3.1
Generic APLL Overview
3.6.3.3.2
DPLLs Output Clocks Parameters
3.6.3.3.3
Enable Control, Status, and Low-Power Operation Mode
3.6.3.3.4
DPLL Power Modes
3.6.3.3.5
DPLL Recalibration
3.6.3.3.6
DPLL Output Power Down
3.6.3.4
DPLL_PER Description
3.6.3.4.1
DPLL_PER Overview
3.6.3.4.2
DPLL_PER Synthesized Clock Parameters
3.6.3.4.3
DPLL_PER Power Modes
3.6.3.4.4
DPLL_PER Recalibration
3.6.3.5
DPLL_CORE Description
3.6.3.5.1
DPLL_CORE Overview
3.6.3.5.2
DPLL_CORE Synthesized Clock Parameters
3.6.3.5.3
DPLL_CORE Power Modes
3.6.3.5.4
DPLL_CORE Recalibration
3.6.3.6
DPLL_ABE Description
3.6.3.6.1
DPLL_ABE Overview
3.6.3.6.2
DPLL_ABE Synthesized Clock Parameters
3.6.3.6.3
DPLL_ABE Power Modes
3.6.3.6.4
DPLL_ABE Recalibration
3.6.3.7
DPLL_MPU Description
3.6.3.7.1
DPLL_MPU Overview
3.6.3.7.2
DPLL_MPU Tactical Clocking Adjustment
3.6.3.7.3
DPLL_MPU Synthesized Clock Parameters
3.6.3.7.4
DPLL_MPU Power Modes
3.6.3.7.5
DPLL_MPU Recalibration
3.6.3.8
DPLL_IVA Description
3.6.3.8.1
DPLL_IVA Overview
3.6.3.8.2
DPLL_IVA Synthesized Clock Parameters
3.6.3.8.3
DPLL_IVA Power Modes
3.6.3.8.4
DPLL_IVA Recalibration
3.6.3.9
DPLL_USB Description
3.6.3.9.1
DPLL_USB Overview
3.6.3.9.2
DPLL_USB Synthesized Clock Parameters
3.6.3.9.3
DPLL_USB Power Modes
3.6.3.9.4
DPLL_USB Recalibration
3.6.3.10
DPLL_DSP Description
3.6.3.10.1
DPLL_DSP Overview
3.6.3.10.2
DPLL_DSP Synthesized Clock Parameters
3.6.3.10.3
DPLL_DSP Power Modes
3.6.3.10.4
DPLL_DSP Recalibration
3.6.3.11
DPLL_GMAC Description
3.6.3.11.1
DPLL_GMAC Overview
3.6.3.11.2
DPLL_GMAC Synthesized Clock Parameters
3.6.3.11.3
DPLL_GMAC Power Modes
3.6.3.11.4
DPLL_GMAC Recalibration
3.6.3.12
DPLL_GPU Description
3.6.3.12.1
DPLL_GPU Overview
3.6.3.12.2
DPLL_GPU Synthesized Clock Parameters
3.6.3.12.3
DPLL_GPU Power Modes
3.6.3.12.4
DPLL_GPU Recalibration
3.6.3.13
DPLL_DDR Description
3.6.3.13.1
DPLL_DDR Overview
3.6.3.13.2
DPLL_DDR Synthesized Clock Parameters
3.6.3.13.3
DPLL_DDR Power Modes
3.6.3.13.4
DPLL_DDR Recalibration
3.6.3.14
DPLL_PCIE_REF Description
3.6.3.14.1
DPLL_PCIE_REF Overview
3.6.3.14.2
DPLL_PCIE_REF Synthesized Clock Parameters
3.6.3.14.3
DPLL_PCIE_REF Power Modes
3.6.3.15
APLL_PCIE Description
3.6.3.15.1
APLL_PCIE Overview
3.6.3.15.2
APLL_PCIE Synthesized Clock Parameters
3.6.3.15.3
APLL_PCIE Power Modes
3.6.4
Clock Domains
3.6.4.1
CD_WKUPAON Clock Domain
3.6.4.1.1
CD_WKUPAON Overview
3.6.4.1.2
CD_WKUPAON Clock Domain Modes
3.6.4.1.3
CD_WKUPAON Clock Domain Dependency
3.6.4.1.3.1
CD_WKUPAON Wake-Up Dependency
3.6.4.1.4
CD_WKUPAON Clock Domain Module Attributes
3.6.4.2
CD_DSP1 Clock Domain
3.6.4.2.1
CD_DSP1 Overview
3.6.4.2.2
CD_DSP1 Clock Domain Modes
3.6.4.2.3
CD_DSP1 Clock Domain Dependency
3.6.4.2.3.1
CD_DSP1 Static Dependency
3.6.4.2.3.2
CD_DSP1 Dynamic Dependency
3.6.4.2.4
CD_DSP1 Clock Domain Module Attributes
3.6.4.3
CD_CUSTEFUSE Clock Domain
3.6.4.3.1
CD_CUSTEFUSE Overview
3.6.4.3.2
CD_CUSTEFUSE Clock Domain Modes
3.6.4.3.3
CD_CUSTEFUSE Clock Domain Dependency
3.6.4.3.4
CD_CUSTEFUSE Clock Domain Module Attributes
3.6.4.4
CD_MPU Clock Domain
3.6.4.4.1
CD_MPU Overview
3.6.4.4.2
CD_MPU Clock Domain Modes
3.6.4.4.3
CD_MPU Clock Domain Dependency
3.6.4.4.3.1
CD_MPU Static Dependency
3.6.4.4.3.2
CD_MPU Dynamic Dependency
3.6.4.4.4
CD_MPU Clock Domain Module Attributes
3.6.4.5
CD_L4PER1 Clock Domain
3.6.4.5.1
CD_L4PER1 Overview
3.6.4.5.2
CD_L4PER1 Clock Domain Modes
3.6.4.5.3
CD_L4PER1 Clock Domain Dependency
3.6.4.5.3.1
CD_L4PER1 Dynamic Dependency
3.6.4.5.3.2
CD_L4PER1 Wake-Up Dependency
3.6.4.5.4
CD_L4PER1 Clock Domain Module Attributes
3.6.4.6
CD_L4PER2 Clock Domain
3.6.4.6.1
CD_L4PER2 Overview
3.6.4.6.2
CD_L4PER2 Clock Domain Modes
3.6.4.6.3
CD_L4PER2 Clock Domain Dependency
3.6.4.6.3.1
CD_L4PER2 Dynamic Dependency
3.6.4.6.3.2
CD_L4PER2 Wake-Up Dependency
3.6.4.6.4
CD_L4PER2 Clock Domain Module Attributes
3.6.4.7
CD_L4PER3 Clock Domain
3.6.4.7.1
CD_L4PER3 Overview
3.6.4.7.2
CD_L4PER3 Clock Domain Modes
3.6.4.7.3
CD_L4PER3 Clock Domain Dependency
3.6.4.7.3.1
CD_L4PER3 Dynamic Dependency
3.6.4.7.3.2
CD_L4PER3 Wake-Up Dependency
3.6.4.7.4
CD_L4PER3 Clock Domain Module Attributes
3.6.4.8
CD_L4SEC Clock Domain
3.6.4.8.1
CD_L4SEC Overview
3.6.4.8.2
CD_L4SEC Clock Domain Modes
3.6.4.8.3
CD_L4SEC Clock Domain Dependency
3.6.4.8.3.1
CD_L4SEC Static Dependency
3.6.4.8.3.2
CD_L4SEC Dynamic Dependency
3.6.4.8.4
CD_L4SEC Clock Domain Module Attributes
3.6.4.8.5
268
3.6.4.9
CD_L3INIT Clock Domain
3.6.4.9.1
CD_L3INIT Overview
3.6.4.9.2
CD_L3INIT Clock Domain Modes
3.6.4.9.3
CD_L3INIT Clock Domain Dependency
3.6.4.9.3.1
CD_L3INIT Static Dependency
3.6.4.9.3.2
CD_L3INIT Dynamic Dependency
3.6.4.9.3.3
CD_L3INIT Wake-Up Dependency
3.6.4.9.4
CD_L3INIT Clock Domain Module Attributes
3.6.4.10
CD_IVA Clock Domain
3.6.4.10.1
CD_IVA Overview
3.6.4.10.2
CD_IVA Clock Domain Modes
3.6.4.10.3
CD_IVA Clock Domain Dependency
3.6.4.10.3.1
CD_IVA Static Dependency
3.6.4.10.3.2
CD_IVA Dynamic Dependency
3.6.4.10.4
CD_IVA Clock Domain Module Attributes
3.6.4.11
CD_GPU Description
3.6.4.11.1
CD_GPU Overview
3.6.4.11.2
CD_GPU Clock Domain Modes
3.6.4.11.3
CD_GPU Clock Domain Dependency
3.6.4.11.3.1
CD_GPU Static Dependency
3.6.4.11.3.2
CD_GPU Dynamic Dependency
3.6.4.11.4
CD_GPU Clock Domain Module Attributes
3.6.4.12
CD_EMU Clock Domain
3.6.4.12.1
CD_EMU Overview
3.6.4.12.2
CD_EMU Clock Domain Modes
3.6.4.12.3
CD_EMU Clock Domain Dependency
3.6.4.12.3.1
CD_EMU Dynamic Dependency
3.6.4.12.4
CD_EMU Clock Domain Module Attributes
3.6.4.13
CD_DSS Clock Domain
3.6.4.13.1
CD_DSS Overview
3.6.4.13.2
CD_DSS Clock Domain Modes
3.6.4.13.3
CD_DSS Clock Domain Dependency
3.6.4.13.3.1
CD_DSS Static Dependency
3.6.4.13.3.2
CD_DSS Dynamic Dependency
3.6.4.13.3.3
CD_DSS Wake-Up Dependency
3.6.4.13.4
CD_DSS Clock Domain Module Attributes
3.6.4.14
CD_L4_CFG Clock Domain
3.6.4.14.1
CD_L4_CFG Overview
3.6.4.14.2
CD_L4_CFG Clock Domain Modes
3.6.4.14.3
CD_L4_CFG Clock Domain Dependency
3.6.4.14.3.1
CD_L4_CFG Dynamic Dependency
3.6.4.14.4
CD_L4_CFG Clock Domain Module Attributes
3.6.4.15
CD_L3_INSTR Clock Domain
3.6.4.15.1
CD_L3_INSTR Overview
3.6.4.15.2
CD_L3_INSTR Clock Domain Modes
3.6.4.15.3
CD_L3_INSTR Clock Domain Dependency
3.6.4.15.4
CD_L3_INSTR Clock Domain Module Attributes
3.6.4.16
CD_L3_MAIN1 Clock Domain
3.6.4.16.1
CD_L3_MAIN1 Overview
3.6.4.16.2
CD_L3_MAIN1 Clock Domain Modes
3.6.4.16.3
CD_L3_MAIN1 Clock Domain Dependency
3.6.4.16.3.1
CD_L3_MAIN1 Dynamic Dependency
3.6.4.16.4
CD_L3_MAIN1 Clock Domain Module Attributes
3.6.4.17
CD_EMIF Clock Domain
3.6.4.17.1
CD_EMIF Overview
3.6.4.17.2
CD_EMIF Clock Domain Modes
3.6.4.17.3
CD_EMIF Clock Domain Dependency
3.6.4.17.4
CD_EMIF Clock Domain Module Attributes
3.6.4.18
CD_IPU Clock Domain
3.6.4.18.1
CD_IPU Overview
3.6.4.18.2
CD_IPU Clock Domain Modes
3.6.4.18.3
CD_IPU Clock Domain Dependency
3.6.4.18.3.1
CD_IPU Static Dependency
3.6.4.18.3.2
CD_IPU Dynamic Dependency
3.6.4.18.4
CD_IPU Clock Domain Module Attributes
3.6.4.19
CD_IPU1 Clock Domain
3.6.4.19.1
CD_IPU1 Overview
3.6.4.19.2
CD_IPU1 Clock Domain Modes
3.6.4.19.3
CD_IPU1 Clock Domain Dependency
3.6.4.19.3.1
CD_IPU1 Static Dependency
3.6.4.19.3.2
CD_IPU1 Dynamic Dependency
3.6.4.19.4
CD_IPU1 Clock Domain Module Attributes
3.6.4.20
CD_IPU2 Clock Domain
3.6.4.20.1
CD_IPU2 Overview
3.6.4.20.2
CD_IPU2 Clock Domain Modes
3.6.4.20.3
CD_IPU2 Clock Domain Dependency
3.6.4.20.3.1
CD_IPU2 Static Dependency
3.6.4.20.3.2
CD_IPU2 Dynamic Dependency
3.6.4.20.4
CD_IPU2 Clock Domain Module Attributes
3.6.4.21
CD_DMA Clock Domain
3.6.4.21.1
CD_DMA Overview
3.6.4.21.2
CD_DMA Clock Domain Modes
3.6.4.21.3
CD_DMA Clock Domain Dependency
3.6.4.21.3.1
CD_DMA Static Dependency
3.6.4.21.3.2
CD_DMA Dynamic Dependency
3.6.4.21.4
CD_DMA Clock Domain Module Attributes
3.6.4.22
CD_ATL Clock Domain
3.6.4.22.1
CD_ATL Overview
3.6.4.22.2
CD_ATL Clock Domain Modes
3.6.4.22.3
CD_ATL Clock Domain Module Attributes
3.6.4.23
CD_CAM Clock Domain
3.6.4.23.1
CD_CAM Overview
3.6.4.23.2
CD_CAM Clock Domain Modes
3.6.4.23.3
CD_CAM Clock Domain Dependency
3.6.4.23.3.1
CD_CAM Static Dependency
3.6.4.23.3.2
CD_CAM Dynamic Dependency
3.6.4.23.4
CD_CAM Clock Domain Module Attributes
3.6.4.23.5
366
3.6.4.24
CD_GMAC Clock Domain
3.6.4.24.1
CD_GMAC Overview
3.6.4.24.2
CD_GMAC Clock Domain Modes
3.6.4.24.3
CD_GMAC Clock Domain Dependency
3.6.4.24.3.1
CD_GMAC Static Dependency
3.6.4.24.3.2
CD_GMAC Dynamic Dependency
3.6.4.24.4
CD_GMAC Clock Domain Module Attributes
3.6.4.25
CD_VPE Clock Domain
3.6.4.25.1
CD_VPE Overview
3.6.4.25.2
CD_VPE Clock Domain Modes
3.6.4.25.3
CD_VPE Clock Domain Dependency
3.6.4.25.3.1
CD_VPE Wake-Up Dependency
3.6.4.25.4
CD_VPE Clock Domain Module Attributes
3.6.4.26
CD_RTC Clock Domain
3.6.4.26.1
CD_RTC Overview
3.6.4.26.2
CD_RTC Clock Domain Modes
3.6.4.26.3
CD_RTC Clock Domain Dependency
3.6.4.26.3.1
CD_RTC Wake-Up Dependency
3.6.4.26.4
CD_RTC Clock Domain Module Attributes
3.6.4.27
CD_PCIE Clock Domain
3.6.4.27.1
CD_PCIE Overview
3.6.4.27.2
CD_PCIE Clock Domain Modes
3.6.4.27.3
CD_PCIE Clock Domain Dependency
3.6.4.27.3.1
CD_PCIE Wake-Up Dependency
3.6.4.27.4
CD_PCIE Clock Domain Module Attributes
3.7
Power Management Functional Description
3.7.1
PD_WKUPAON Description
3.7.1.1
PD_WKUPAON Power Domain Modes
3.7.1.1.1
PD_WKUPAON Logic and Memory Area Power Modes
3.7.2
PD_DSP1 Description
3.7.2.1
PD_DSP1 Power Domain Modes
3.7.2.1.1
PD_DSP1 Logic and Memory Area Power Modes
3.7.2.1.2
PD_DSP1 Logic and Memory Area Power Modes Control and Status
3.7.3
PD_CUSTEFUSE Description
3.7.3.1
PD_CUSTEFUSE Power Domain Modes
3.7.3.1.1
PD_CUSTEFUSE Logic and Memory Area Power Modes
3.7.3.1.2
PD_CUSTEFUSE Logic and Memory Area Power Modes Control and Status
3.7.4
PD_MPU Description
3.7.4.1
PD_MPU Power Domain Modes
3.7.4.1.1
PD_MPU Logic and Memory Area Power Modes
3.7.4.1.2
PD_MPU Logic and Memory Area Power Modes Control and Status
3.7.4.1.3
PD_MPU Power State Override
3.7.5
PD_IPU Description
3.7.5.1
PD_IPU Power Domain Modes
3.7.5.1.1
PD_IPU Logic and Memory Area Power Modes
3.7.5.1.2
PD_IPU Logic and Memory Area Power Modes Control and Status
3.7.6
PD_L3INIT Description
3.7.6.1
PD_L3INIT Power Domain Modes
3.7.6.1.1
PD_L3INIT Logic and Memory Area Power Modes
3.7.6.1.2
PD_L3INIT Logic and Memory Area Power Modes Control and Status
3.7.7
PD_L4PER Description
3.7.8
PD_IVA Description
3.7.8.1
PD_IVA Power Domain Modes
3.7.8.1.1
PD_IVA Logic and Memory Area Power Modes
3.7.8.1.2
PD_IVA Logic and Memory Area Power Modes Control and Status
3.7.9
PD_GPU Description
3.7.9.1
PD_GPU Power Domain Modes
3.7.9.1.1
PD_GPU Logic and Memory Area Power Modes
3.7.9.1.2
PD_GPU Logic and Memory Area Power Modes Control and Status
3.7.10
PD_EMU Description
3.7.11
PD_DSS Description
3.7.11.1
PD_DSS Power Domain Modes
3.7.11.1.1
PD_DSS Logic and Memory Area Power Modes
3.7.11.1.2
PD_DSS Logic and Memory Area Power Mode Control and Status
3.7.12
PD_CORE Description
3.7.12.1
PD_CORE Power Domain Modes
3.7.12.1.1
PD_CORE Logic and Memory Area Power Modes
3.7.12.1.2
PD_CORE Logic and Memory Area Power Mode Control and Status
3.7.13
PD_CAM Description
3.7.13.1
PD_CAM Power Domain Modes
3.7.13.1.1
PD_CAM Logic and Memory Area Power Modes
3.7.13.1.2
PD_CAM Logic and Memory Area Power Mode Control and Status
3.7.14
PD_MPUAON Description
3.7.14.1
PD_MPUAON Power Domain Modes
3.7.15
PD_MMAON Description
3.7.15.1
PD_MMAON Power Domain Modes
3.7.16
PD_COREAON Description
3.7.16.1
PD_COREAON Power Domain Modes
3.7.17
PD_VPE Description
3.7.17.1
PD_VPE Power Domain Modes
3.7.17.1.1
PD_VPE Logic and Memory Area Power Modes
3.7.17.1.2
PD_VPE Logic and Memory Area Power Modes Control and Status
3.7.18
PD_RTC Description
3.7.18.1
PD_RTC Power Domain Modes
3.7.18.1.1
PD_RTC Logic and Memory Area Power Modes
3.8
Voltage-Management Functional Description
3.8.1
Overview
3.8.2
Voltage-Control Architecture
3.8.3
Internal LDOs Control
3.8.3.1
VDD_MPU_L, VDD_CORE_L, and VDD_IVAHD_L, VDD_GPU_L, VDD_DSPEVE_L Control
3.8.3.1.1
Adaptive Voltage Scaling
3.8.3.1.1.1
SmartReflex in the Device
3.8.3.2
Memory LDOs
3.8.3.3
ABB LDOs Control
3.8.3.4
ABB LDO Programming Sequence
3.8.3.4.1
ABB LDO Enable Sequence
3.8.3.4.2
ABB LDO Disable Sequence (Entering in Bypass Mode)
3.8.3.5
BANDGAPs Control
3.8.4
DVFS
3.9
Device Low-Power States
3.9.1
Device Wake-Up Source Summary
3.9.2
Wakeup Upon Global Warm Reset
3.9.3
Global Warm Reset During a Device Wake-Up Sequence
3.9.4
I/O Management
3.9.4.1
Isolation / Wakeup Sequence
3.9.4.1.1
Software-Controlled I/O Isolation
3.10
PRCM Module Programming Guide
3.10.1
DPLLs Low-Level Programming Models
3.10.1.1
Global Initialization
3.10.1.1.1
Surrounding Module Global Initialization
3.10.1.1.2
DPLL Global Initialization
3.10.1.1.2.1
Main Sequence – DPLL Global Initialization
3.10.1.1.2.2
Subsequence – Recalibration Parameter Configuration
3.10.1.1.2.3
Subsequence – Synthesized Clock Parameter Configuration
3.10.1.1.2.4
Subsequence – Output Clock Parameter Configuration
3.10.1.2
DPLL Output Frequency Change
3.10.2
Clock Management Low-Level Programming Models
3.10.2.1
Global Initialization
3.10.2.1.1
Surrounding Module Global Initialization
3.10.2.1.2
Clock Management Global Initialization
3.10.2.1.2.1
Main Sequence – Clock Domain Global Initialization
3.10.2.2
Clock Domain Sleep Transition and Troubleshooting
3.10.2.3
Enable/Disable Software-Programmable Static Dependency
3.10.3
Power Management Low-Level Programming Models
3.10.3.1
Global Initialization
3.10.3.1.1
Surrounding Module Global Initialization
3.10.3.1.2
Power Management Global Initialization
3.10.3.1.2.1
Main Sequence – Power Domain Global Initialization and Setting
3.10.3.2
Forced Memory Area State Change With Power Domain ON
3.10.3.3
Forced Power Domain Low-Power State Transition
3.11
497
3.12
PRCM Software Configuration for OPP_PLUS
3.13
PRCM Register Manual
3.13.1
Not Supported Functionality (Registers and Bits)
3.13.2
PRCM Instance Summary
3.13.3
CM_CORE_AON__CKGEN Registers
3.13.3.1
CM_CORE_AON__CKGEN Register Summary
3.13.3.2
CM_CORE_AON__CKGEN Register Description
3.13.4
CM_CORE_AON__DSP1 Registers
3.13.4.1
CM_CORE_AON__DSP1 Register Summary
3.13.4.2
CM_CORE_AON__DSP1 Register Description
3.13.5
CM_CORE_AON__DSP2 Registers
3.13.5.1
CM_CORE_AON__DSP2 Register Summary
3.13.5.2
CM_CORE_AON__DSP2 Register Description
3.13.6
CM_CORE_AON__EVE1 Registers
3.13.6.1
CM_CORE_AON__EVE1 Register Summary
3.13.6.2
CM_CORE_AON__EVE1 Register Description
3.13.7
CM_CORE_AON__EVE2 Registers
3.13.7.1
CM_CORE_AON__EVE2 Register Summary
3.13.7.2
CM_CORE_AON__EVE2 Register Description
3.13.8
CM_CORE_AON__EVE3 Registers
3.13.8.1
CM_CORE_AON__EVE3 Register Summary
3.13.8.2
CM_CORE_AON__EVE3 Register Description
3.13.9
CM_CORE_AON__EVE4 Registers
3.13.9.1
CM_CORE_AON__EVE4 Register Summary
3.13.9.2
CM_CORE_AON__EVE4 Register Description
3.13.10
CM_CORE_AON__INSTR Registers
3.13.10.1
CM_CORE_AON__INSTR Register Summary
3.13.10.2
CM_CORE_AON__INSTR Register Description
3.13.11
CM_CORE_AON__IPU Registers
3.13.11.1
CM_CORE_AON__IPU Register Summary
3.13.11.2
CM_CORE_AON__IPU Register Description
3.13.12
CM_CORE_AON__MPU Registers
3.13.12.1
CM_CORE_AON__MPU Register Summary
3.13.12.2
CM_CORE_AON__MPU Register Description
3.13.13
CM_CORE_AON__OCP_SOCKET Registers
3.13.13.1
CM_CORE_AON__OCP_SOCKET Register Summary
3.13.13.2
CM_CORE_AON__OCP_SOCKET Register Description
3.13.14
CM_CORE_AON__RESTORE Registers
3.13.14.1
CM_CORE_AON__RESTORE Register Summary
3.13.14.2
CM_CORE_AON__RESTORE Register Description
3.13.15
CM_CORE_AON__RTC Registers
3.13.15.1
CM_CORE_AON__RTC Register Summary
3.13.15.2
CM_CORE_AON__RTC Register Description
3.13.16
CM_CORE_AON__VPE Registers
3.13.16.1
CM_CORE_AON__VPE Register Summary
3.13.16.2
CM_CORE_AON__VPE Register Description
3.13.17
CM_CORE__CAM Registers
3.13.17.1
CM_CORE__CAM Register Summary
3.13.17.2
CM_CORE__CAM Register Description
3.13.18
CM_CORE__CKGEN Registers
3.13.18.1
CM_CORE__CKGEN Register Summary
3.13.18.2
CM_CORE__CKGEN Register Description
3.13.19
CM_CORE__COREAON Registers
3.13.19.1
CM_CORE__COREAON Register Summary
3.13.19.2
CM_CORE__COREAON Register Description
3.13.20
CM_CORE__CORE Registers
3.13.20.1
CM_CORE__CORE Register Summary
3.13.20.2
CM_CORE__CORE Register Description
3.13.21
CM_CORE__CUSTEFUSE Registers
3.13.21.1
CM_CORE__CUSTEFUSE Register Summary
3.13.21.2
CM_CORE__CUSTEFUSE Register Description
3.13.22
CM_CORE__DSS Registers
3.13.22.1
CM_CORE__DSS Register Summary
3.13.22.2
CM_CORE__DSS Register Description
3.13.23
CM_CORE__GPU Registers
3.13.23.1
CM_CORE__GPU Register Summary
3.13.23.2
CM_CORE__GPU Register Description
3.13.24
CM_CORE__IVA Registers
3.13.24.1
CM_CORE__IVA Register Summary
3.13.24.2
CM_CORE__IVA Register Description
3.13.25
CM_CORE__L3INIT Registers
3.13.25.1
CM_CORE__L3INIT Register Summary
3.13.25.2
CM_CORE__L3INIT Register Description
3.13.26
CM_CORE__L4PER Registers
3.13.26.1
CM_CORE__L4PER Register Summary
3.13.26.2
CM_CORE__L4PER Register Description
3.13.27
CM_CORE__OCP_SOCKET Registers
3.13.27.1
CM_CORE__OCP_SOCKET Register Summary
3.13.27.2
CM_CORE__OCP_SOCKET Register Description
3.13.28
CM_CORE__RESTORE Registers
3.13.28.1
CM_CORE__RESTORE Register Summary
3.13.28.2
CM_CORE__RESTORE Register Description
3.13.29
SMARTREFLEX Registers
3.13.29.1
SMARTREFLEX Register Summary
3.13.29.2
SMARTREFLEX Register Description
3.13.30
CAM_PRM Registers
3.13.30.1
CAM_PRM Register Summary
3.13.30.2
CAM_PRM Register Description
3.13.31
CKGEN_PRM Registers
3.13.31.1
CKGEN_PRM Register Summary
3.13.31.2
CKGEN_PRM Register Description
3.13.32
COREAON_PRM Registers
3.13.32.1
COREAON_PRM Register Summary
3.13.32.2
COREAON_PRM Register Description
3.13.33
CORE_PRM Registers
3.13.33.1
CORE_PRM Register Summary
3.13.33.2
CORE_PRM Register Description
3.13.34
CUSTEFUSE_PRM Registers
3.13.34.1
CUSTEFUSE_PRM Register Summary
3.13.34.2
CUSTEFUSE_PRM Register Description
3.13.35
DEVICE_PRM Registers
3.13.35.1
DEVICE_PRM Register Summary
3.13.35.2
DEVICE_PRM Register Description
3.13.36
DSP1_PRM registers
3.13.36.1
DSP1_PRM Register Summary
3.13.36.2
DSP1_PRM Register Description
3.13.37
DSP2_PRM Registers
3.13.37.1
DSP2_PRM Register Summary
3.13.37.2
DSP2_PRM Register Description
3.13.38
DSS_PRM Registers
3.13.38.1
DSS_PRM Register Summary
3.13.38.2
DSS_PRM Register Description
3.13.39
EMU_CM Registers
3.13.39.1
EMU_CM Register Summary
3.13.39.2
EMU_CM Register Description
3.13.40
EMU_PRM Registers
3.13.40.1
EMU_PRM Register Summary
3.13.40.2
EMU_PRM Register Description
3.13.41
EVE1_PRM Registers
3.13.41.1
EVE1_PRM Register Summary
3.13.41.2
EVE1_PRM Register Description
3.13.42
EVE2_PRM Registers
3.13.42.1
EVE2_PRM Register Summary
3.13.42.2
EVE2_PRM Register Description
3.13.43
EVE3_PRM Registers
3.13.43.1
EVE3_PRM Register Summary
3.13.43.2
EVE3_PRM Register Description
3.13.44
EVE4_PRM Registers
3.13.44.1
EVE4_PRM Register Summary
3.13.44.2
EVE4_PRM Register Description
3.13.45
GPU_PRM Registers
3.13.45.1
GPU_PRM Register Summary
3.13.45.2
GPU_PRM Register Description
3.13.46
INSTR_PRM Registers
3.13.46.1
INSTR_PRM Register Summary
3.13.46.2
INSTR_PRM Register Description
3.13.47
IPU_PRM registers
3.13.47.1
IPU_PRM Register Summary
3.13.47.2
IPU_PRM Register Description
3.13.48
IVA_PRM Registers
3.13.48.1
IVA_PRM Register Summary
3.13.48.2
IVA_PRM Register Description
3.13.49
L3INIT_PRM Registers
3.13.49.1
L3INIT_PRM Register Summary
3.13.49.2
L3INIT_PRM Register Description
3.13.50
L4PER_PRM Registers
3.13.50.1
L4PER_PRM Register Summary
3.13.50.2
L4PER_PRM Register Description
3.13.51
MPU_PRM Registers
3.13.51.1
MPU_PRM Register Summary
3.13.51.2
MPU_PRM Register Description
3.13.52
OCP_SOCKET_PRM Registers
3.13.52.1
OCP_SOCKET_PRM Register Summary
3.13.52.2
OCP_SOCKET_PRM Register Description
3.13.53
RTC_PRM Registers
3.13.53.1
RTC_PRM Register Summary
3.13.53.2
RTC_PRM Register Description
3.13.54
VPE_PRM Registers
3.13.54.1
VPE_PRM Register Summary
3.13.54.2
VPE_PRM Register Description
3.13.55
WKUPAON_CM Registers
3.13.55.1
WKUPAON_CM Register Summary
3.13.55.2
WKUPAON_CM Register Description
3.13.56
WKUPAON_PRM registers
3.13.56.1
WKUPAON_PRM Register Summary
3.13.56.2
WKUPAON_PRM Register Description
4
Cortex-A15 MPU Subsystem
4.1
Cortex-A15 MPU Subsystem Overview
4.1.1
Introduction
4.1.2
Features
4.2
Cortex-A15 MPU Subsystem Integration
4.2.1
Clock Distribution
4.2.2
Reset Distribution
4.3
Cortex-A15 MPU Subsystem Functional Description
4.3.1
MPU Subsystem Block Diagram
4.3.2
Cortex-A15 MPCore (MPU_CLUSTER)
4.3.2.1
MPU L2 Cache Memory System
4.3.2.1.1
MPU L2 Cache Architecture
4.3.2.1.2
MPU L2 Cache Controller
4.3.2.1.3
677
4.3.3
MPU_AXI2OCP
4.3.4
Memory Adapter
4.3.4.1
MPU_MA Overview
4.3.4.2
AXI Input Interface
4.3.4.3
Interleaving
4.3.4.3.1
High-Order Fixed Interleaving Model
4.3.4.3.2
Lower 2-GiB Programmable Interleaving Model
4.3.4.3.3
Local Interconnect and Synchronization Agent (LISA) Section Manager
4.3.4.3.4
MA_LSM Registers
4.3.4.3.5
Posted and Nonposted Writes
4.3.4.3.6
Errors
4.3.4.4
Statistics Collector Probe Ports
4.3.4.5
MPU_MA Firewall
4.3.4.6
MPU_MA Power and Reset Management
4.3.4.7
MPU_MA Watchpoint
4.3.4.7.1
Watchpoint Types
4.3.4.7.2
Transaction Filtering Options
4.3.4.7.3
Transaction Match Effects
4.3.4.7.4
Trigger Generation
4.3.4.7.5
Programming Options Summary
4.3.5
Realtime Counter (Master Counter)
4.3.5.1
Counter Operation
4.3.5.2
Frequency Change Procedure
4.3.6
MPU Watchdog Timer
4.3.7
MPU Subsystem Power Management
4.3.7.1
Power Domains
4.3.7.2
Power States of MPU_C0
4.3.7.3
Power States of MPU Subsystem
4.3.7.4
MPU_WUGEN
4.3.7.5
Power Transition Sequence
4.3.7.6
SR3-APG Technology Fail-Safe Mode
4.3.8
MPU Subsystem AMBA Interface Configuration
4.4
Cortex-A15 MPU Subsystem Register Manual
4.4.1
Cortex-A15 MPU Subsystem Instance Summary
4.4.2
MPU_CS_STM Registers
4.4.3
MPU_INTC Registers
4.4.4
MPU_PRCM_OCP_SOCKET Registers
4.4.4.1
MPU_PRCM_OCP_SOCKET Register Summary
4.4.4.2
MPU_PRCM_OCP_SOCKET Register Description
4.4.5
MPU_PRCM_DEVICE Registers
4.4.5.1
MPU_PRCM_DEVICE Register Summary
4.4.5.2
MPU_PRCM_DEVICE Register Description
4.4.6
MPU_PRCM_PRM_C0 Registers
4.4.6.1
MPU_PRCM_PRM_C0 Register Summary
4.4.6.2
MPU_PRCM_PRM_C0 Register Description
4.4.7
MPU_PRCM_CM_C0 Registers
4.4.7.1
MPU_PRCM_CM_C0 Register Summary
4.4.7.2
MPU_PRCM_CM_C0 Register Description
4.4.8
MPU_WUGEN Registers
4.4.8.1
MPU_WUGEN Register Summary
4.4.8.2
MPU_WUGEN Register Description
4.4.9
MPU_WD_TIMER Registers
4.4.9.1
MPU_WD_TIMER Register Summary
4.4.9.2
MPU_WD_TIMER Register Description
4.4.10
MPU_AXI2OCP_MISC Registers
4.4.10.1
MPU_AXI2OCP_MISC Register Summary
4.4.10.2
MPU_AXI2OCP_MISC Register Description
4.4.11
MPU_MA_LSM Registers
4.4.11.1
MPU_MA_LSM Register Summary
4.4.11.2
MPU_MA_LSM Register Description
4.4.12
MPU_MA_WP Registers
4.4.12.1
MPU_MA_WP Register Summary
4.4.12.2
MPU_MA_WP Register Description
5
DSP Subsystem
5.1
DSP Subsystem Overview
5.1.1
DSP Subsystem Key Features
5.2
DSP Subsystem Integration
5.3
DSP Subsystem Functional Description
5.3.1
DSP Subsystem Block Diagram
5.3.2
DSP Subsystem Components
5.3.2.1
C66x DSP Subsystem Introduction
5.3.2.2
DSP TMS320C66x CorePac
5.3.2.2.1
DSP TMS320C66x CorePac CPU
5.3.2.2.2
DSP TMS320C66x CorePac Internal Memory Controllers and Memories
5.3.2.2.2.1
Level 1 Memories
5.3.2.2.2.2
Level 2 Memory
5.3.2.2.3
DSP C66x CorePac Internal Peripherals
5.3.2.2.3.1
DSP C66x CorePac Interrupt Controller (DSP INTC)
5.3.2.2.3.2
DSP C66x CorePac Power-Down Controller (DSP PDC)
5.3.2.2.3.3
DSP C66x CorePac Bandwidth Manager (BWM)
5.3.2.2.3.4
DSP C66x CorePac Memory Protection Hardware
5.3.2.2.3.5
DSP C66x CorePac Internal DMA (IDMA) Controller
5.3.2.2.3.6
DSP C66x CorePac External Memory Controller
5.3.2.2.3.7
DSP C66x CorePac Extended Memory Controller
5.3.2.2.3.7.1
XMC MDMA Accesses at DSP System Level
5.3.2.2.3.7.1.1
DSP System MPAX Logic
5.3.2.2.3.7.1.2
MDMA Non-Post Override Control
5.3.2.2.3.8
L1P Memory Error Detection Logic
5.3.2.2.3.9
L2 Memory Error Detection and Correction Logic
5.3.2.3
DSP Debug and Trace Support
5.3.2.3.1
DSP Advanced Event Triggering (AET)
5.3.2.3.2
DSP Trace Support
5.3.2.3.3
770
5.3.3
DSP System Control Logic
5.3.3.1
DSP System Clocks
5.3.3.2
DSP Hardware Resets
5.3.3.3
DSP Software Resets
5.3.3.4
DSP Power Management
5.3.3.4.1
DSP System Powerdown Protocols
5.3.3.4.2
DSP Software and Hardware Power Down Sequence Overview
5.3.3.4.3
DSP IDLE Wakeup
5.3.3.4.4
DSP SYSTEM IRQWAKEEN registers
5.3.3.4.5
DSP Automatic Power Transition
5.3.4
DSP Interrupt Requests
5.3.4.1
DSP Input Interrupts
5.3.4.1.1
DSP Non-maskable Interrupt Input
5.3.4.2
DSP Event and Interrupt Generation Outputs
5.3.4.2.1
DSP MDMA and DSP EDMA Mflag Event Outputs
5.3.4.2.2
DSP Aggregated Error Interrupt Output
5.3.4.2.3
Non-DSP C66x CorePac Generated Peripheral Interrupt Outputs
5.3.5
DSP DMA Requests
5.3.5.1
DSP EDMA Wakeup Interrupt
5.3.6
DSP Intergated Memory Management Units
5.3.6.1
DSP MMUs Overview
5.3.6.2
Routing MDMA Traffic through DSP MMU0
5.3.6.3
Routing EDMA Traffic thorugh DSP MMU1
5.3.7
DSP Integrated EDMA Subsystem
5.3.7.1
DSP EDMA Overview
5.3.7.2
DSP System and Device Level Settings of DSP EDMA
5.3.8
DSP L2 interconnect Network
5.3.8.1
DSP Public Firewall Settings
5.3.8.2
DSP NoC Flag Mux and Error Log Registers
5.3.8.3
DSP NoC Arbitration
5.3.9
DSP Boot Configuration
5.3.10
DSP Internal and External Memory Views
5.3.10.1
C66x CPU View of the Address Space
5.3.10.2
DSP_EDMA View of the Address Space
5.3.10.3
L3_MAIN View of the DSP Address Space
5.4
DSP Subsystem Register Manual
5.4.1
DSP Subsystem Instance Summary
5.4.2
DSP_ICFG Registers
5.4.2.1
DSP_ICFG Register Summary
5.4.2.2
DSP_ICFG Register Description
5.4.3
DSP_SYSTEM Registers
5.4.3.1
DSP_SYSTEM Register Summary
5.4.3.2
DSP_SYSTEM Register Description
5.4.4
DSP_FW_L2_NOC_CFG Registers
5.4.4.1
DSP_FW_L2_NOC_CFG Register Summary
5.4.4.2
DSP_FW_L2_NOC_CFG Register Description
6
IVA Subsystem
7
Dual Cortex-M4 IPU Subsystem
7.1
Dual Cortex-M4 IPU Subsystem Overview
7.1.1
Introduction
7.1.2
Features
7.2
Dual Cortex-M4 IPU Subsystem Integration
7.2.1
Dual Cortex-M4 IPU Subsystem Clock and Reset Distribution
7.2.1.1
Clock Distribution
7.2.1.2
Reset Distribution
7.3
Dual Cortex-M4 IPU Subsystem Functional Description
7.3.1
IPUx Subsystem Block Diagram
7.3.2
Power Management
7.3.2.1
Local Power Management
7.3.2.2
Power Domains
7.3.2.3
831
7.3.2.4
Voltage Domain
7.3.2.5
Power States and Modes
7.3.2.6
Wake-Up Generator (IPUx_WUGEN)
7.3.2.6.1
IPUx_WUGEN Main Features
7.3.3
IPUx_UNICACHE
7.3.4
IPUx_UNICACHE_MMU
7.3.5
IPUx_UNICACHE_SCTM
7.3.5.1
Counter Functions
7.3.5.1.1
Input Events
7.3.5.1.2
Counters
7.3.5.1.2.1
Counting Modes
7.3.5.1.2.2
Counter Overflow
7.3.5.1.2.3
Counters and Processor State
7.3.5.1.2.4
Chaining Counters
7.3.5.1.2.5
Enabling and Disabling Counters
7.3.5.1.2.6
Resetting Counters
7.3.5.2
Timer Functions
7.3.5.2.1
Periodic Intervals
7.3.5.2.2
Event Generation
7.3.6
IPUx_MMU
7.3.6.1
IPUx_MMU Behavior on Page-Fault in IPUx Subsystem
7.3.7
Interprocessor Communication (IPC)
7.3.7.1
Use of WFE and SEV
7.3.7.2
Use of Interrupt for IPC
7.3.7.3
Use of the Bit-Band Feature for Semaphore Operations
7.3.7.4
Private Memory Space
7.3.8
IPU Boot Options
7.4
Dual Cortex-M4 IPU Subsystem Register Manual
7.4.1
IPUx Subsystem Instance Summary
7.4.2
IPUx_UNICACHE_CFG Registers
7.4.2.1
IPUx_UNICACHE_CFG Register Summary
7.4.2.2
IPUx_UNICACHE_CFG Register Description
7.4.3
IPUx_UNICACHE_SCTM Registers
7.4.3.1
IPUx_UNICACHE_SCTM Register Summary
7.4.3.2
IPUx_UNICACHE_SCTM Register Description
7.4.4
IPUx_UNICACHE_MMU (AMMU) Registers
7.4.4.1
IPUx_UNICACHE_MMU (AMMU) Register Summary
7.4.4.2
IPUx_UNICACHE_MMU (AMMU) Register Description
7.4.5
IPUx_MMU Registers
7.4.6
IPUx_Cx_INTC Registers
7.4.7
IPUx_WUGEN Registers
7.4.7.1
IPUx_WUGEN Register Summary
7.4.7.2
IPUx_WUGEN Register Description
7.4.8
IPUx_Cx_RW_TABLE Registers
7.4.8.1
IPUx_Cx_RW_TABLE Register Summary
7.4.8.2
IPUx_Cx_RW_TABLE Register Description
8
Camera Interface Subsystem
8.1
CAMSS Overview
8.1.1
CAMSS Block Diagram
8.1.2
881
8.1.3
CAMSS Features
8.2
CAMSS Environment
8.2.1
CAMSS Interfaces Signal Descriptions
8.3
CAMSS Integration
8.3.1
CAMSS Main Integration Attributes
8.3.2
CAL Integration - Video Port
8.3.3
CAL Integration - PPI Interface
8.4
CAMSS Functional Description
8.4.1
CAMSS Hardware and Software Reset
8.4.2
CAMSS Clock Configuration
8.4.3
CAMSS Power Management
8.4.4
CAMSS Interrupt Events
8.4.5
CSI2 PHY Functional Description
8.4.5.1
CSI2 PHY Overview
8.4.5.2
CSI2 PHY Configuration
8.4.5.3
CSI2 PHY Link Initialization Sequence
8.4.5.4
CSI2 PHY Error Signals
8.4.6
CAL Functional Description
8.4.6.1
CAL Block Diagram
8.4.6.2
CSI2 Low Level Protocol
8.4.6.2.1
CSI2 Physical Layer
8.4.6.2.2
CSI2 Multi-lane Layer and Lane Merger
8.4.6.2.3
CSI2 Protocol Layer
8.4.6.2.3.1
CSI2 Short Packet
8.4.6.2.3.2
CSI2 Long Packet
8.4.6.2.3.3
CSI2 ECC and Checksum Generation
8.4.6.2.3.3.1
CSI2 ECC
8.4.6.2.3.3.2
CSI2 Checksum
8.4.6.2.3.4
CSI2 Alignment Constraints
8.4.6.2.3.5
CSI2 Data Identifier
8.4.6.2.3.6
CSI2 Virtual Channel ID
8.4.6.2.3.7
CSI2 Synchronization Codes
8.4.6.2.3.8
CSI2 Generic Short Packet Codes
8.4.6.2.3.9
CSI2 Frame Structure and Data
8.4.6.2.3.10
CSI2 Virtual Channel and Context
8.4.6.2.4
CSI2 TAG Generation FSM
8.4.6.3
CAL Data Stream Merger
8.4.6.4
CAL Pixel Extraction
8.4.6.5
CAL DPCM Decoding and Encoding
8.4.6.6
CAL Stream Interleaving
8.4.6.7
CAL Pixel Packing
8.4.6.8
CAL Write DMA
8.4.6.8.1
CAL Write DMA Overview
8.4.6.8.2
CAL Write DMA Data Cropping
8.4.6.8.3
CAL Write DMA Buffer Management
8.4.6.8.4
CAL Write DMA OCP Address Generation
8.4.6.8.4.1
Write DMA Buffer Base Address
8.4.6.8.4.2
Write DMA Line Start Address
8.4.6.8.4.3
Write DMA Data Address
8.4.6.8.5
CAL Write DMA OCP Transaction Generation
8.4.6.8.6
CAL Write DMA Real Time Traffic
8.4.6.9
CAL Video Port
8.4.6.9.1
CAL Video Port Overview
8.4.6.9.2
CAL Video Port Pixel Clock Generation
8.4.6.9.3
CAL Video Port Video Timing Generator
8.4.6.10
CAL Registers Shadowing
8.5
CAMSS Register Manual
8.5.1
CAMSS Instance Summary
8.5.2
CAL Registers
8.5.2.1
CAL Register Summary
8.5.2.2
CAL Register Description
8.5.3
CSI2 PHY Registers
8.5.3.1
CSI2 PHY Register Summary
8.5.3.2
CSI2 PHY Register Description
9
Video Input Port
9.1
VIP Overview
9.2
VIP Environment
9.3
VIP Integration
9.4
VIP Functional Description
9.4.1
VIP Block Diagram
9.4.2
VIP Software Reset
9.4.3
VIP Power and Clocks Management
9.4.3.1
VIP Clocks
9.4.3.2
VIP Idle Mode
9.4.3.3
VIP StandBy Mode
9.4.4
VIP Slice
9.4.4.1
VIP Slice Processing Path Overview
9.4.4.2
VIP Slice Processing Path Multiplexers
9.4.4.2.1
VIP_CSC Multiplexers
9.4.4.2.2
VIP_SC Multiplexer
9.4.4.2.3
Output to VPDMA Multiplexers
9.4.4.3
VIP Slice Processing Path Examples
9.4.4.3.1
Input: A=RGB, B=YUV422; Output: A=RGB, B=RGB
9.4.4.3.2
Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=RGB
9.4.4.3.3
Input: A=RGB, B=YUV422; Output: A=RGB, B=Scaled YUV420
9.4.4.3.4
Input: A=YUV444, B=YUV422; Output: A=YUV422, A=Scaled YUV422, B=YUV422
9.4.4.3.5
Input: A=YUV444; Output: A=Scaled YUV420, A=YUV420
9.4.4.3.6
Input: A=YUV444; Output: A=Scaled YUV420, A=YUV444
9.4.4.3.7
Input: A=YUV422 8/16; Output: A=Scaled YUV420, A=YUV444
9.4.4.3.8
Input: A=YUV422 8/16, B=YUV422; Output: A=Scaled YUV420, B=YUV420
9.4.4.3.9
Input: A=YUV422 8/16, B=YUV422; Output: A=YUV420, B=YUV420
9.4.5
VIP Parser
9.4.5.1
Features
9.4.5.2
Repacker
9.4.5.3
Analog Video
9.4.5.4
Digitized Video
9.4.5.5
Frame Buffers
9.4.5.6
Input Data Interface
9.4.5.6.1
8b Interface Mode
9.4.5.6.2
16b Interface Mode
9.4.5.6.3
24b Interface Mode
9.4.5.6.4
Signal Relationships
9.4.5.6.5
General 5 Pin Interfaces
9.4.5.6.6
Signal Subsets—4 Pin VSYNC, ACTVID, and FID
9.4.5.6.7
Signal Subsets—4 Pin VSYNC, HSYNC, and FID
9.4.5.6.8
Vertical Sync
9.4.5.6.9
Field ID Determination Using Dedicated Signal
9.4.5.6.10
Field ID Determination Using VSYNC Skew
9.4.5.6.11
Rationale for FID Determination By VSYNC Skew
9.4.5.6.12
ACTVID Framing
9.4.5.6.13
Ancillary Data Storage in Descrete Sync Mode
9.4.5.7
BT.656 Style Embedded Sync
9.4.5.7.1
Data Input
9.4.5.7.2
Sync Words
9.4.5.7.3
Error Correction
9.4.5.7.4
Embedded Sync Ancillary Data
9.4.5.7.5
Embedded Sync RGB 24-bit Data
9.4.5.8
Source Multiplexing
9.4.5.8.1
Multiplexing Scenarios
9.4.5.8.2
2-Way Multiplexing
9.4.5.8.3
4-Way Multiplexing
9.4.5.8.4
Line Multiplexing
9.4.5.8.5
Super Frame Concept in Line Multiplexing
9.4.5.8.6
8-bit Data Interface in Line Multiplexing
9.4.5.8.7
16-bit Data Interface in Line Multiplexing
9.4.5.8.8
Split Lines in Line Multiplex Mode
9.4.5.8.9
Meta Data
9.4.5.8.10
TI Line Mux Mode, Split Lines, and Channel ID Remapping
9.4.5.9
Channel ID Extraction for 2x/4x Multiplexed Source
9.4.5.9.1
Channel ID Extraction Overview
9.4.5.9.2
Channel ID Embedded in Protection Bits for 2- and 4-Way Multiplexing
9.4.5.9.3
Channel ID Embedded in Horizontal Blanking Pixel Data for 2- and 4-Way Multiplexing
9.4.5.10
Embedded Sync Mux Modes and Data Bus Widths
9.4.5.11
Ancillary and Active Video Cropping
9.4.5.12
Interrupts
9.4.5.13
VDET Interrupt
9.4.5.14
Source Video Size
9.4.5.15
Clipping
9.4.5.16
Current and Last FID Value
9.4.5.17
Disable Handling
9.4.5.18
Picture Size Interrupt
9.4.5.19
Discrete Sync Signals
9.4.5.19.1
VBLNK and HBLNK
9.4.5.19.2
BLNK and ACTVID (1)
9.4.5.19.3
VBLNK and ACTVID(2)
9.4.5.19.4
VBLNK and HSYNC
9.4.5.19.5
VSYNC and HBLNK
9.4.5.19.6
VSYNC and ACTIVID(1)
9.4.5.19.7
VSYNC and ACTIVID(2)
9.4.5.19.8
VSYNC and HSYNC
9.4.5.19.9
Line and Pixel Capture Examples
9.4.5.20
VIP Overflow Detection and Recovery
9.4.6
VIP Color Space Converter (CSC)
9.4.6.1
CSC Features
9.4.6.2
CSC Functional Description
9.4.6.2.1
HDTV Application
9.4.6.2.1.1
HDTV Application with Video Data Range
9.4.6.2.1.2
HDTV Application with Graphics Data Range
9.4.6.2.1.3
Quantized Coefficients for Color Space Converter in HDTV
9.4.6.2.2
SDTV Application
9.4.6.2.2.1
SDTV Application with Video Data Range
9.4.6.2.2.2
SDTV Application with Graphics Data Range
9.4.6.2.2.3
Quantized Coefficients for Color Space Converter in SDTV
9.4.6.3
CSC Bypass Mode
9.4.7
VIP Scaler (SC)
9.4.7.1
SC Features
9.4.7.2
SC Functional Description
9.4.7.2.1
Trimmer
9.4.7.2.2
1050
9.4.7.2.3
Peaking
9.4.7.2.4
Vertical Scaler
9.4.7.2.4.1
Running Average Filter
9.4.7.2.4.2
Vertical Scaler Configuration Parameters
9.4.7.2.5
Horizontal Scaler
9.4.7.2.5.1
Half Decimation Filter
9.4.7.2.5.2
Polyphase Filter
9.4.7.2.5.3
Nonlinear Horizontal Scaling
9.4.7.2.5.4
Horizontal Scaler Configuration Registers
9.4.7.2.6
Basic Configurations
9.4.7.2.7
Coefficient Memory
9.4.7.2.7.1
Overview
9.4.7.2.7.2
Physical Coefficient SRAM Layout
9.4.7.2.7.3
Scaler Coefficients Packing on 128-bit VPI Control I/F
9.4.7.2.7.4
VPI Control I/F Memory Map for Scaler Coefficients
9.4.7.2.7.5
VPI Control Interface
9.4.7.2.7.6
Coefficient Table Selection Guide
9.4.7.3
SC Code
9.4.7.3.1
Generate Coefficient Memory Image
9.4.7.3.2
Scaler Configuration Calculation
9.4.7.3.3
Typical Configuration Values
9.4.7.4
SC Coefficient Data Files
9.4.7.4.1
HS Polyphase Filter Coefficients
9.4.7.4.1.1
ppfcoef_scale_eq_1_32_phases_flip.dat
9.4.7.4.1.2
ppfcoef_scale_eq_8div16_32_phases_flip.dat
9.4.7.4.1.3
ppfcoef_scale_eq_9div16_32_phases_flip.dat
9.4.7.4.1.4
ppfcoef_scale_eq_10div16_32_phases_flip.dat
9.4.7.4.1.5
ppfcoef_scale_eq_11div16_32_phases_flip.dat
9.4.7.4.1.6
ppfcoef_scale_eq_12div16_32_phases_flip.dat
9.4.7.4.1.7
ppfcoef_scale_eq_13div16_32_phases_flip.dat
9.4.7.4.1.8
ppfcoef_scale_eq_14div16_32_phases_flip.dat
9.4.7.4.1.9
ppfcoef_scale_eq_15div16_32_phases_flip.dat
9.4.7.4.2
VS Polyphase Filter Coefficients
9.4.7.4.2.1
ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
9.4.7.4.2.2
ppfcoef_scale_eq_3_32_phases_flip.dat
9.4.7.4.2.3
ppfcoef_scale_eq_4_32_phases_flip.dat
9.4.7.4.2.4
ppfcoef_scale_eq_5_32_phases_flip.dat
9.4.7.4.2.5
ppfcoef_scale_eq_6_32_phases_flip.dat
9.4.7.4.2.6
ppfcoef_scale_eq_7_32_phases_flip.dat
9.4.7.4.2.6.1
ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
9.4.7.4.2.6.2
ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
9.4.7.4.2.6.3
ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
9.4.7.4.2.6.4
ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
9.4.7.4.2.6.5
ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
9.4.7.4.2.6.6
ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
9.4.7.4.2.6.7
ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
9.4.7.4.2.6.8
ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
9.4.7.4.3
VS (Bilinear Filter Coefficients)
9.4.7.4.3.1
ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
9.4.8
VIP Video Port Direct Memory Access (VPDMA)
9.4.8.1
VPDMA Introduction
9.4.8.2
VPDMA Basic Definitions
9.4.8.2.1
Client
9.4.8.2.2
Channel
9.4.8.2.3
List
9.4.8.2.4
Data Formats Supported
9.4.8.3
1107
9.4.8.4
VPDMA Client Buffering and Functionality
9.4.8.5
VPDMA Channels Assignment
9.4.8.6
VPDMA MFLAG Mechanism
9.4.8.7
VPDMA Interrupts
9.4.8.8
VPDMA Descriptors
9.4.8.8.1
Data Transfer Descriptors
9.4.8.8.1.1
Data Packet Descriptor Word 0 (Data)
9.4.8.8.1.1.1
Data Type
9.4.8.8.1.1.2
Notify
9.4.8.8.1.1.3
Field
9.4.8.8.1.1.4
Even Line Skip
9.4.8.8.1.1.5
Odd Line Skip
9.4.8.8.1.1.6
Line Stride
9.4.8.8.1.2
Data Packet Descriptor Word 1
9.4.8.8.1.2.1
Line Length
9.4.8.8.1.2.2
Transfer Height
9.4.8.8.1.3
Data Packet Descriptor Word 2
9.4.8.8.1.3.1
Start Address
9.4.8.8.1.4
Data Packet Descriptor Word 3
9.4.8.8.1.4.1
Packet Type
9.4.8.8.1.4.2
Mode
9.4.8.8.1.4.3
Direction
9.4.8.8.1.4.4
Channel
9.4.8.8.1.4.5
Priority
9.4.8.8.1.4.6
Next Channel
9.4.8.8.1.5
Data Packet Descriptor Word 4
9.4.8.8.1.5.1
Inbound data
9.4.8.8.1.5.1.1
Frame Width
9.4.8.8.1.5.1.2
Frame Height
9.4.8.8.1.5.2
Outbound data
9.4.8.8.1.5.2.1
Descriptor Write Address
9.4.8.8.1.5.2.2
Write Descriptor
9.4.8.8.1.5.2.3
Drop Data
9.4.8.8.1.6
Data Packet Descriptor Word 5
9.4.8.8.1.6.1
Outbound data
9.4.8.8.1.6.1.1
Max Width
9.4.8.8.1.6.1.2
Max Height
9.4.8.8.2
Configuration Descriptor
9.4.8.8.2.1
Configuration Descriptor Header Word0
9.4.8.8.2.2
Configuration Descriptor Header Word1
9.4.8.8.2.2.1
Number of Data Words
9.4.8.8.2.3
Configuration Descriptor Header Word2
9.4.8.8.2.3.1
Payload Location
9.4.8.8.2.4
Configuration Descriptor Header Word3
9.4.8.8.2.4.1
Packet Type
9.4.8.8.2.4.2
Direct
9.4.8.8.2.4.3
Class
9.4.8.8.2.4.3.1
Address Data Block Format
9.4.8.8.2.4.4
Destination
9.4.8.8.2.4.5
Descriptor Length
9.4.8.8.3
Control Descriptor
9.4.8.8.3.1
Generic Control Descriptor Format
9.4.8.8.3.2
Control Descriptor Header Description
9.4.8.8.3.2.1
Packet Type
9.4.8.8.3.2.2
Source
9.4.8.8.3.2.3
Control
9.4.8.8.3.3
Control Descriptor Types
9.4.8.8.3.3.1
Sync on Client
9.4.8.8.3.3.2
Sync on List
9.4.8.8.3.3.3
Sync on External Event
9.4.8.8.3.3.4
Sync on Channel
9.4.8.8.3.3.5
Sync on LM Timer
9.4.8.8.3.3.6
Change Client Interrupt
9.4.8.8.3.3.7
Send Interrupt
9.4.8.8.3.3.8
Reload List
9.4.8.8.3.3.9
Abort Channel
9.4.8.9
VPDMA Configuration
9.4.8.9.1
Regular List
9.4.8.9.2
Video Input Ports
9.4.8.9.2.1
Multiplexed Data Streams
9.4.8.9.2.2
Single YUV Color Separate
9.4.8.9.2.3
Dual YUV Interleaved
9.4.8.10
VPDMA Data Formats
9.4.8.10.1
YUV Data Formats
9.4.8.10.1.1
Y 4:4:4 (Data Type 0)
9.4.8.10.1.2
Y 4:2:2 (Data Type 1)
9.4.8.10.1.3
Y 4:2:0 (Data Type 2)
9.4.8.10.1.4
C 4:4:4 (Data Type 4)
9.4.8.10.1.5
C 4:2:2 (Data Type 5)
9.4.8.10.1.6
C 4:2:0 (Data Type 6)
9.4.8.10.1.7
YC 4:2:2 (Data Type 7)
9.4.8.10.1.8
YC 4:4:4 (Data Type 8)
9.4.8.10.1.9
CY 4:2:2 (Data Type 23)
9.4.8.10.2
RGB Data Formats
9.4.8.10.2.1
RGB16-565 (Data Type 0)
9.4.8.10.2.2
ARGB-1555 (Data Type 1)
9.4.8.10.2.3
ARGB-4444 (Data Type 2)
9.4.8.10.2.4
RGBA-5551 (Data Type 3)
9.4.8.10.2.5
RGBA-4444 (Data Type 4)
9.4.8.10.2.6
ARGB24-6666 (Data Type 5)
9.4.8.10.2.7
RGB24-888 (Data Type 6)
9.4.8.10.2.8
ARGB32-8888 (Data Type 7)
9.4.8.10.2.9
RGBA24-6666 (Data Type 8)
9.4.8.10.2.10
RGBA32-8888 (Data Type 9)
9.4.8.10.3
Miscellaneous Data Type
9.5
VIP Register Manual
9.5.1
VIP Instance Summary
9.5.2
VIP Top Level Registers
9.5.2.1
VIP Top Level Register Summary
9.5.2.2
VIP Top Level Register Description
9.5.3
VIP Parser Registers
9.5.3.1
VIP Parser Register Summary
9.5.3.2
VIP Parser Register Description
9.5.4
VIP CSC Registers
9.5.4.1
VIP CSC Register Summary
9.5.4.2
VIP CSC Register Description
9.5.5
VIP SC registers
9.5.5.1
VIP SC Register Summary
9.5.5.2
VIP SC Register Description
9.5.6
VIP VPDMA Registers
9.5.6.1
VIP VPDMA Register Summary
9.5.6.2
VIP VPDMA Register Description
10
Video Processing Engine
10.1
VPE Overview
10.2
VPE Integration
10.3
VPE Functional Description
10.3.1
VPE Block Diagram
10.3.2
VPE VC1 Range Mapping/Range Reduction
10.3.3
VPE Deinterlacer (DEI)
10.3.3.1
Functional Description
10.3.3.2
Bypass Mode
10.3.3.3
1229
10.3.3.3.1
VPDMA Interface
10.3.3.3.2
MDT
10.3.3.3.3
EDI
10.3.3.3.4
FMD
10.3.3.3.5
MUX
10.3.3.3.6
LINE BUFFER
10.3.4
VPE Scaler (SC)
10.3.4.1
SC Features
10.3.4.2
SC Functional Description
10.3.4.2.1
Trimmer
10.3.4.2.2
1240
10.3.4.2.3
Peaking
10.3.4.2.4
Vertical Scaler
10.3.4.2.4.1
Running Average Filter
10.3.4.2.4.2
Vertical Scaler Configuration Parameters
10.3.4.2.5
Horizontal Scaler
10.3.4.2.5.1
Half Decimation Filter
10.3.4.2.5.2
Polyphase Filter
10.3.4.2.5.3
Nonlinear Horizontal Scaling
10.3.4.2.5.4
Horizontal Scaler Configuration Registers
10.3.4.2.6
Basic Configurations
10.3.4.2.7
Coefficient Memory
10.3.4.2.7.1
Overview
10.3.4.2.7.2
Physical Coefficient SRAM Layout
10.3.4.2.7.3
Scaler Coefficients Packing on 128-bit VPI Control I/F
10.3.4.2.7.4
VPI Control I/F Memory Map for Scaler Coefficients
10.3.4.2.7.5
VPI Control Interface
10.3.4.2.7.6
Coefficient Table Selection Guide
10.3.4.3
SC Code
10.3.4.3.1
Generate Coefficient Memory Image
10.3.4.3.2
Scaler Configuration Calculation
10.3.4.3.3
Typical Configuration Values
10.3.4.4
SC Coefficient Data Files
10.3.4.4.1
HS Polyphase Filter Coefficients
10.3.4.4.1.1
ppfcoef_scale_eq_1_32_phases_flip.dat
10.3.4.4.1.2
ppfcoef_scale_eq_8div16_32_phases_flip.dat
10.3.4.4.1.3
ppfcoef_scale_eq_9div16_32_phases_flip.dat
10.3.4.4.1.4
ppfcoef_scale_eq_10div16_32_phases_flip.dat
10.3.4.4.1.5
ppfcoef_scale_eq_11div16_32_phases_flip.dat
10.3.4.4.1.6
ppfcoef_scale_eq_12div16_32_phases_flip.dat
10.3.4.4.1.7
ppfcoef_scale_eq_13div16_32_phases_flip.dat
10.3.4.4.1.8
ppfcoef_scale_eq_14div16_32_phases_flip.dat
10.3.4.4.1.9
ppfcoef_scale_eq_15div16_32_phases_flip.dat
10.3.4.4.2
VS Polyphase Filter Coefficients
10.3.4.4.2.1
ppfcoef_scale_eq_1_32_phases_ver_5tap_flip.dat
10.3.4.4.2.2
ppfcoef_scale_eq_3_32_phases_flip.dat
10.3.4.4.2.3
ppfcoef_scale_eq_4_32_phases_flip.dat
10.3.4.4.2.4
ppfcoef_scale_eq_5_32_phases_flip.dat
10.3.4.4.2.5
ppfcoef_scale_eq_6_32_phases_flip.dat
10.3.4.4.2.6
ppfcoef_scale_eq_7_32_phases_flip.dat
10.3.4.4.2.6.1
ppfcoef_scale_eq_8div16_32_phases_ver_5tap_flip.dat
10.3.4.4.2.6.2
ppfcoef_scale_eq_9div16_32_phases_ver_5tap_flip.dat
10.3.4.4.2.6.3
ppfcoef_scale_eq_10div16_32_phases_ver_5tap_flip.dat
10.3.4.4.2.6.4
ppfcoef_scale_eq_11div16_32_phases_ver_5tap_flip.dat
10.3.4.4.2.6.5
ppfcoef_scale_eq_12div16_32_phases_ver_5tap_flip.dat
10.3.4.4.2.6.6
ppfcoef_scale_eq_13div16_32_phases_ver_5tap_flip.dat
10.3.4.4.2.6.7
ppfcoef_scale_eq_14div16_32_phases_ver_5tap_flip.dat
10.3.4.4.2.6.8
ppfcoef_scale_eq_15div16_32_phases_ver_5tap_flip.dat
10.3.4.4.2.6.9
ppcoef_scale_1x_ver_5tap.dat
10.3.4.4.3
VS (Bilinear Filter Coefficients)
10.3.4.4.3.1
ppfcoef_scale_eq_1_32_phases_flip_PPF3_peak5_gain_eq_1_25.dat
10.3.5
VPE Color Space Converter (CSC)
10.3.5.1
CSC Features
10.3.5.2
CSC Functional Description
10.3.5.3
1294
10.3.5.3.1
HDTV Application
10.3.5.3.1.1
HDTV Application with Video Data Range
10.3.5.3.1.2
HDTV Application with Graphics Data Range
10.3.5.3.1.3
Quantized Coefficients for Color Space Converter in HDTV
10.3.5.3.2
SDTV Application
10.3.5.3.2.1
SDTV Application with Video Data Range
10.3.5.3.2.2
SDTV Application with Graphics Data Range
10.3.5.3.2.3
Quantized Coefficients for Color Space Converter in SDTV
10.3.5.4
CSC Bypass Mode
10.3.6
VPE Chroma Up-Sampler (CHR_US)
10.3.6.1
Features
10.3.6.2
Functional Description
10.3.6.3
For Interlaced YUV420 Input Data
10.3.6.4
Edge Effects
10.3.6.5
Modes of Operation (VPDMA)
10.3.6.6
Coefficient Configuration
10.3.7
VPE Chroma Down-Sampler (CHR_DS)
10.3.8
VPE YUV422 to YUV444 Conversion
10.3.9
VPE Video Port Direct Memory Access (VPDMA)
10.3.9.1
VPDMA Introduction
10.3.9.2
VPDMA Basic Definitions
10.3.9.2.1
Client
10.3.9.2.2
Channel
10.3.9.2.3
List
10.3.9.2.4
Data Formats Supported
10.3.9.3
VPDMA Client Buffering and Functionality
10.3.9.4
VPDMA Channels Assignment
10.3.9.5
VPDMA Interrupts
10.3.9.6
VPDMA Descriptors
10.3.9.6.1
Data Transfer Descriptors
10.3.9.6.1.1
Data Packet Descriptor Word 0 (Data)
10.3.9.6.1.1.1
Data Type
10.3.9.6.1.1.2
Notify
10.3.9.6.1.1.3
Field
10.3.9.6.1.1.4
1D
10.3.9.6.1.1.5
Even Line Skip
10.3.9.6.1.1.6
Odd Line Skip
10.3.9.6.1.1.7
Line Stride
10.3.9.6.1.2
Data Packet Descriptor Word 1
10.3.9.6.1.2.1
Line Length
10.3.9.6.1.2.2
Transfer Height
10.3.9.6.1.3
Data Packet Descriptor Word 2
10.3.9.6.1.3.1
Start Address
10.3.9.6.1.4
Data Packet Descriptor Word 3
10.3.9.6.1.4.1
Packet Type
10.3.9.6.1.4.2
Mode
10.3.9.6.1.4.3
Direction
10.3.9.6.1.4.4
Channel
10.3.9.6.1.4.5
Priority
10.3.9.6.1.4.6
Next Channel
10.3.9.6.1.5
Data Packet Descriptor Word 4
10.3.9.6.1.5.1
Inbound data
10.3.9.6.1.5.1.1
Frame Width
10.3.9.6.1.5.1.2
Frame Height
10.3.9.6.1.5.2
Outbound data
10.3.9.6.1.5.2.1
Descriptor Write Address
10.3.9.6.1.5.2.2
Write Descriptor
10.3.9.6.1.5.2.3
Drop Data
10.3.9.6.1.5.2.4
Use Descriptor Register
10.3.9.6.1.6
Data Packet Descriptor Word 5
10.3.9.6.1.6.1
Outbound data
10.3.9.6.1.6.1.1
Max Width
10.3.9.6.1.6.1.2
Max Height
10.3.9.6.1.7
Data Packet Descriptor Word 6/7 (Data)
10.3.9.6.2
Configuration Descriptor
10.3.9.6.2.1
Configuration Descriptor Header Word0
10.3.9.6.2.2
Configuration Descriptor Header Word1
10.3.9.6.2.2.1
Number of Data Words
10.3.9.6.2.3
Configuration Descriptor Header Word2
10.3.9.6.2.3.1
Payload Location
10.3.9.6.2.4
Configuration Descriptor Header Word3
10.3.9.6.2.4.1
Packet Type
10.3.9.6.2.4.2
Direct
10.3.9.6.2.4.3
Class
10.3.9.6.2.4.3.1
Address Data Block Format
10.3.9.6.2.4.4
Destination
10.3.9.6.2.4.5
Descriptor Length
10.3.9.6.3
Control Descriptor
10.3.9.6.3.1
Generic Control Descriptor Format
10.3.9.6.3.2
Control Descriptor Header Description
10.3.9.6.3.2.1
Packet Type
10.3.9.6.3.2.2
Source
10.3.9.6.3.2.3
Control
10.3.9.6.3.3
Control Descriptor Types
10.3.9.6.3.3.1
Sync on Client
10.3.9.6.3.3.2
Sync on List
10.3.9.6.3.3.3
Sync on External Event
10.3.9.6.3.3.4
Sync on Channel
10.3.9.6.3.3.5
Sync on LM Timer
10.3.9.6.3.3.6
Change Client Interrupt
10.3.9.6.3.3.7
Send Interrupt
10.3.9.6.3.3.8
Reload List
10.3.9.6.3.3.9
Abort Channel
10.3.9.7
VPDMA Configuration
10.3.9.7.1
Regular List
10.3.9.7.2
Video Input Ports
10.3.9.7.2.1
Single YUV Color Separate
10.3.9.7.2.2
Dual YUV Interleaved
10.3.9.7.2.3
Single RGB Stream
10.3.9.8
VPDMA Data Formats
10.3.9.8.1
YUV Data Formats
10.3.9.8.1.1
Y 4:4:4 (Data Type 0)
10.3.9.8.1.2
Y 4:2:2 (Data Type 1)
10.3.9.8.1.3
Y 4:2:0 (Data Type 2)
10.3.9.8.1.4
C 4:4:4 (Data Type 4)
10.3.9.8.1.5
C 4:2:2 (Data Type 5)
10.3.9.8.1.6
C 4:2:0 (Data Type 6)
10.3.9.8.1.7
YC 4:2:2 (Data Type 7)
10.3.9.8.1.8
YC 4:4:4 (Data Type 8)
10.3.9.8.1.9
CY 4:2:2 (Data Type 23)
10.3.9.8.2
RGB Data Formats
10.3.9.8.2.1
Input Data Formats
10.3.9.8.2.1.1
RGB16-565 (Data Type 0)
10.3.9.8.2.1.2
ARGB-1555 (Data Type 1)
10.3.9.8.2.1.3
ARGB-4444 (Data Type 2)
10.3.9.8.2.1.4
RGBA-5551 (Data Type 3)
10.3.9.8.2.1.5
RGBA-4444 (Data Type 4)
10.3.9.8.2.1.6
ARGB24-6666 (Data Type 5)
10.3.9.8.2.1.7
RGB24-888 (Data Type 6)
10.3.9.8.2.1.8
ARGB32-8888 (Data Type 7)
10.3.9.8.2.1.9
RGBA24-6666 (Data Type 8)
10.3.9.8.2.1.10
RGBA32-8888 (Data Type 9)
10.3.9.8.2.2
Output Data Formats
10.3.9.8.2.2.1
RGB16-565 (Data Type 0)
10.3.9.8.2.2.2
ARGB-1555 (Data Type 1)
10.3.9.8.2.2.3
ARGB-4444 (Data Type 2)
10.3.9.8.2.2.4
RGBA-5551 (Data Type 3)
10.3.9.8.2.2.5
RGBA-4444 (Data Type 4)
10.3.9.8.2.2.6
ARGB24-6666 (Data Type 5)
10.3.9.8.2.2.7
RGB24-888 (Data Type 6)
10.3.9.8.2.2.8
ARGB32-8888 (Data Type 7)
10.3.9.8.2.2.9
RGBA24-6666 (Data Type 8)
10.3.9.8.2.2.10
RGBA32-8888 (Data Type 9)
10.3.9.8.3
Miscellaneous Data Type
10.3.10
VPE Software Reset
10.3.11
VPE Power and Clocks Management
10.3.11.1
VPE Clocks
10.3.11.2
VPE Idle Mode
10.3.11.3
VPE StandBy Mode
10.4
VPE Register Manual
10.4.1
VPE Instance Summary
10.4.2
VPE_CSC Registers
10.4.2.1
VPE_CSC Register Summary
10.4.2.2
VPE_CSC Register Description
10.4.3
VPE_SC Registers
10.4.3.1
VPE_SC Register Summary
10.4.3.2
VPE_SC Register Description
10.4.4
VPE_CHR_US Registers
10.4.4.1
VPE_CHR_US Register Summary
10.4.4.2
VPE_CHR_US Register Description
10.4.5
VPE_DEI Registers
10.4.5.1
VPE_DEI Register Summary
10.4.5.2
VPE_DEI Register Description
10.4.6
VPE_VPDMA Registers
10.4.6.1
VPE_VPDMA Register Summary
10.4.6.2
VPE_VPDMA Register Description
10.4.7
VPE_TOP_LEVEL Registers
10.4.7.1
VPE_TOP_LEVEL Register Summary
10.4.7.2
VPE_TOP_LEVEL Register Description
11
Display Subsystem
11.1
Display Subsystem Overview
11.1.1
Display Subsystem Environment
11.1.1.1
Display Subsystem LCD Support
11.1.1.1.1
Display Subsystem LCD with Parallel Interfaces
11.1.1.2
Display Subsystem TV Display Support
11.1.1.2.1
Display Subsystem TV With Parallel Interfaces
11.1.1.2.2
Display Subsystem TV With Serial Interfaces
11.1.2
Display Subsystem Integration
11.1.2.1
Display Subsystem Clocks
11.1.2.2
Display Subsystem Resets
11.1.2.3
Display Subsystem Power Management
11.1.2.3.1
Display Subsystem Standby Mode
11.1.2.3.2
1467
11.1.2.3.3
Display Subsystem Wake-Up Mode
11.1.3
Display Subsystem DPLL Controllers Functional Description
11.1.3.1
DPLL Controllers Overview
11.1.3.2
OCP2SCP2 Functional Description
11.1.3.2.1
OCP2SCP2 Reset
11.1.3.2.1.1
Hardware Reset
11.1.3.2.1.2
Software Reset
11.1.3.2.2
OCP2SCP2 Power Management
11.1.3.2.2.1
Idle Mode
11.1.3.2.2.2
Clock Gating
11.1.3.2.3
OCP2SCP2 Timing Registers
11.1.3.3
DPLL_VIDEO Functional Description
11.1.3.3.1
DPLL_VIDEO Controller Architecture
11.1.3.3.2
DPLL_VIDEO Operations
11.1.3.3.3
DPLL_VIDEO Error Handling
11.1.3.3.4
DPLL_VIDEO Software Reset
11.1.3.3.5
DPLL_VIDEO Power Management
11.1.3.3.6
DPLL_VIDEO HSDIVIDER Loading Operation
11.1.3.3.7
DPLL_VIDEO Clock Sequence
11.1.3.3.8
DPLL_VIDEO Go Sequence
11.1.3.3.9
DPLL_VIDEO Recommended Values
11.1.3.4
DPLL_HDMI Functional Description
11.1.3.4.1
DPLL_HDMI and PLLCTRL_HDMI Overview
11.1.3.4.2
DPLL_HDMI and PLLCTRL_HDMI Architecture
11.1.3.4.3
DPLL_HDMI Operations
11.1.3.4.4
DPLL_HDMI Register Access
11.1.3.4.5
DPLL_HDMI Error Handling
11.1.3.4.6
DPLL_HDMI Software Reset
11.1.3.4.7
DPLL_HDMI Power Management
11.1.3.4.8
DPLL_HDMI Lock Sequence
11.1.3.4.9
DPLL_HDMI Go Sequence
11.1.3.4.10
DPLL_HDMI Recommended Values
11.1.4
Display Subsystem Programming Guide
11.1.5
Display Subsystem Register Manual
11.1.5.1
Display Subsystem Instance Summary
11.1.5.2
Display Subsystem Registers
11.1.5.2.1
Display Subsystem Registers Mapping Summary
11.1.5.2.2
Display Subsystem Register Description
11.1.5.3
OCP2SCP2 registers
11.1.5.3.1
OCP2SCP2 Register Summary
11.1.5.3.2
OCP2SCP Register Description
11.1.5.4
DPLL_VIDEO Registers
11.1.5.4.1
DPLL_VIDEO Register Summary
11.1.5.4.2
DPLL_VIDEO Register Description
11.1.5.5
DPLL_HDMI Registers
11.1.5.5.1
DPLL_HDMI Registers Mapping Summary
11.1.5.5.2
DPLL_HDMI Register Description
11.1.5.6
HDMI_WP Registers
11.1.5.6.1
HDMI_WP Registers Mapping Summary
11.1.5.6.2
HDMI_WP Register Description
11.1.5.7
DSI Registers
11.1.5.7.1
DSI Register Summary
11.1.5.7.2
DSI Register Description
11.2
Display Controller
11.2.1
DISPC Overview
11.2.2
DISPC Environment
11.2.2.1
DISPC LCD Output and Data Format for the Parallel Interface
11.2.2.2
DISPC Transaction Timing Diagrams
11.2.2.3
DISPC TV Output and Data Format for the Parallel Interface
11.2.3
DISPC Integration
11.2.4
DISPC Functional Description
11.2.4.1
DISPC Clock Configuration
11.2.4.2
DISPC Software Reset
11.2.4.3
DISPC Power Management
11.2.4.3.1
DISPC Idle Mode
11.2.4.3.2
DISPC StandBy Mode
11.2.4.3.3
DISPC Wakeup
11.2.4.4
DISPC Interrupt Requests
11.2.4.5
DISPC DMA Requests
11.2.4.6
DISPC DMA Engine
11.2.4.6.1
DISPC Addressing and Bursts
11.2.4.6.2
DISPC Immediate Base Address Flip Mechanism
11.2.4.6.3
DISPC DMA Buffers
11.2.4.6.3.1
DISPC READ DMA Buffers (GFX and VID Pipelines)
11.2.4.6.3.2
DISPC WRITE DMA Buffer (WB Pipeline)
11.2.4.6.4
DISPC MFLAG Mechanism and Arbitration
11.2.4.6.5
DISPC Predecimation
11.2.4.6.6
DISPC Progressive-to-Interlaced Format Conversion
11.2.4.6.7
DISPC Arbitration
11.2.4.6.8
DISPC DMA Power Modes
11.2.4.6.8.1
DISPC DMA Low-Power Mode
11.2.4.6.8.2
DISPC DMA Ultralow-Power Mode
11.2.4.7
DISPC Rotation and Mirroring
11.2.4.8
DISPC Memory Format
11.2.4.9
DISPC Graphics Pipeline
11.2.4.9.1
DISPC Replication Logic
11.2.4.9.2
DISPC Antiflicker Filter
11.2.4.10
DISPC Video Pipelines
11.2.4.10.1
DISPC Replication Logic
11.2.4.10.2
DISPC VC-1 Range Mapping Unit
11.2.4.10.3
DISPC CSC Unit YUV to RGB
11.2.4.10.3.1
DISPC Chrominance Resampling
11.2.4.10.4
DISPC Scaler Unit
11.2.4.10.4.1
DISPC Scaling Algorithms
11.2.4.10.4.2
DISPC Scaling limitations
11.2.4.11
DISPC Write-Back Pipeline
11.2.4.11.1
DISPC Write-Back CSC Unit RGB to YUV
11.2.4.11.2
DISPC Write-Back Scaler Unit
11.2.4.11.3
DISPC Write-Back RGB Truncation Logic
11.2.4.12
DISPC Hardware Cursor
11.2.4.13
DISPC LCD Outputs
11.2.4.13.1
DISPC Overlay Manager
11.2.4.13.1.1
DISPC Priority Rule
11.2.4.13.1.2
DISPC Alpha Blender
11.2.4.13.1.3
DISPC Transparency Color Keys
11.2.4.13.1.4
DISPC Overlay Optimization
11.2.4.13.2
DISPC Gamma Correction Unit
11.2.4.13.3
DISPC Color Phase Rotation Unit
11.2.4.13.4
DISPC Color Space Conversion
11.2.4.13.5
DISPC BT.656 and BT.1120 Modes
11.2.4.13.5.1
Blanking
11.2.4.13.5.2
EAV and SAV
11.2.4.13.6
DISPC Active Matrix
11.2.4.13.6.1
DISPC Spatial/Temporal Dithering
11.2.4.13.6.2
DISPC Multiple Cycle Output Format (TDM)
11.2.4.13.7
DISPC Synchronized Buffer Update
11.2.4.13.8
DISPC Timing Generator and Panel Settings
11.2.4.14
DISPC TV Output
11.2.4.14.1
DISPC Overlay Manager
11.2.4.14.2
DISPC Gamma Correction Unit
11.2.4.14.3
DISPC Synchronized Buffer Update
11.2.4.14.4
DISPC Timing and TV Format Settings
11.2.4.15
DISPC Frame Width Considerations
11.2.4.16
DISPC Extended 3D Support
11.2.4.16.1
DISPC Extended 3D Support - Line Alternative Format
11.2.4.16.2
1593
11.2.4.16.3
DISPC Extended 3D Support - Frame Packing Format Format
11.2.4.16.4
DISPC Extended 3D Support - DLP 3D Format
11.2.4.17
DISPC Shadow Registers
11.2.5
DISPC Programming Guide
11.2.5.1
DISPC Low-Level Programming Models
11.2.5.1.1
DISPC Global Initialization
11.2.5.1.1.1
DISPC Surrounding Modules Global Initialization
11.2.5.1.2
DISPC Operational Modes Configuration
11.2.5.1.2.1
DISPC DMA Configuration
11.2.5.1.2.1.1
DISPC Main Sequence – DISPC DMA Channel Configuration
11.2.5.1.2.2
DISPC GFX Pipeline Configuration
11.2.5.1.2.2.1
DISPC Main Sequence – Configure the GFX Pipeline
11.2.5.1.2.2.2
DISPC Subsequence – Configure the GFX Window
11.2.5.1.2.2.3
DISPC Subsequence – Configure the GFX Pipeline Processing
11.2.5.1.2.2.4
DISPC Subsequence – Configure the GFX Pipeline Layer Output
11.2.5.1.2.3
DISPC Video Pipeline Configuration
11.2.5.1.2.3.1
DISPC Main Sequence – Configure the Video Pipeline
11.2.5.1.2.3.2
DISPC Subsequence – Configure the Video Window
11.2.5.1.2.3.3
DISPC Subsequence – Configure the Video Pipeline Processing
11.2.5.1.2.3.4
DISPC Subsequence – Configure the VC-1 Range Mapping
11.2.5.1.2.3.5
DISPC Subsequence – Configure the Video Color Space Conversion
11.2.5.1.2.3.6
DISPC Subsequence – Configure the Video Scaler Unit
11.2.5.1.2.3.7
DISPC Subsequence – Configure the Video Pipeline Layer Output
11.2.5.1.2.4
DISPC WB Pipeline Configuration
11.2.5.1.2.4.1
DISPC Main Sequence – Configure the WB Pipeline
11.2.5.1.2.4.2
DISPC Subsequence – Configure the Capture Window
11.2.5.1.2.4.3
DISPC Subsequence – Configure the WB Scaler Unit
11.2.5.1.2.4.4
DISPC Subsequence – Configure the WB Color Space Conversion Unit
11.2.5.1.2.5
DISPC LCD Output Configuration
11.2.5.1.2.5.1
DISPC Main Sequence – Configure the LCD Output
11.2.5.1.2.5.2
DISPC Subsequence – Configure the Overlay Manager
11.2.5.1.2.5.3
DISPC Subsequence – Configure the Gamma Table for Gamma Correction
11.2.5.1.2.5.4
DISPC Subsequence – Configure the Color Phase Rotation
11.2.5.1.2.5.5
DISPC Subsequence – Configure the LCD Panel Timings and Parameters
11.2.5.1.2.5.6
DISPC Subsequence – Configure BT.656 or BT.1120 Mode
11.2.5.1.2.6
DISPC TV Output Configuration
11.2.5.1.2.6.1
DISPC Main Sequence – Configure the TV Output
11.2.5.1.2.6.1.1
DISPC Subsequence – Configure the TV Overlay Manager
11.2.5.1.2.6.1.2
DISPC Subsequence – Configure the Gamma Table for Gamma Correction
11.2.5.1.2.6.1.3
DISPC Subsequence – Configure the TV Panel Timings and Parameters
11.2.6
DISPC Register Manual
11.2.6.1
DISPC Instance Summary
11.2.6.2
DISPC Logical Register Mapping
11.2.6.3
DISPC Registers
11.2.6.3.1
DISPC Register Summary
11.2.6.3.2
DISPC Register Description
11.3
High-Definition Multimedia Interface
11.3.1
HDMI Overview
11.3.1.1
HDMI Main Features
11.3.1.2
HDMI Video Formats and Timings
11.3.1.2.1
HDMI CEA-861-D Video Formats and Timings
11.3.1.2.2
VESA DMT Video Formats and Timings
12
3D Graphics Accelerator
12.1
GPU Overview
12.1.1
GPU Features Overview
12.1.2
Graphics Feature Overview
12.2
GPU Integration
12.3
GPU Functional Description
12.3.1
GPU Block Diagram
12.3.2
GPU Clock Configuration
12.3.3
GPU Software Reset
12.3.4
GPU Power Management
12.3.5
GPU Thermal Management
12.3.6
GPU Interrupt Requests
12.4
GPU Register Manual
12.4.1
GPU Instance Summary
12.4.2
GPU Registers
12.4.2.1
GPU_WRAPPER Register Summary
12.4.2.2
GPU_WRAPPER Register Description
13
2D Graphics Accelerator
13.1
BB2D Overview
13.1.1
BB2D Key Features Overview
13.2
BB2D Integration
13.3
BB2D Functional Description
13.3.1
BB2D Block Diagram
13.3.2
BB2D Clock Configuration
13.3.3
BB2D Software Reset
13.3.4
BB2D Power Management
13.4
BB2D Register Manual
13.4.1
BB2D Instance Summary
13.4.2
BB2D Registers
13.4.2.1
BB2D Register Summary
13.4.2.2
BB2D Register Description
14
Interconnect
14.1
Interconnect Overview
14.1.1
Terminology
14.1.2
Architecture Overview
14.2
L3_MAIN Interconnect
14.2.1
L3_MAIN Interconnect Overview
14.2.2
L3_MAIN Interconnect Integration
14.2.3
L3_MAIN Interconnect Functional Description
14.2.3.1
Module Use in L3_MAIN Interconnect
14.2.3.2
Module Distribution
14.2.3.2.1
L3_MAIN Interconnect Agents
14.2.3.2.2
L3_MAIN Connectivity Matrix
14.2.3.2.2.1
Clock Domain Mapping of the L3_MAIN Interconnect Modules
14.2.3.2.2.2
1690
14.2.3.2.3
Master NIU Identification
14.2.3.3
Bandwidth Regulators
14.2.3.4
Bandwidth Limiters
14.2.3.5
Flag Muxing
14.2.3.5.1
Flag Mux Time-out
14.2.3.6
Statistic Collectors Group
14.2.3.7
L3_MAIN Protection and Firewalls
14.2.3.7.1
L3_MAIN Firewall Reset
14.2.3.7.1.1
L3_MAIN Firewall – Exported Reset Values
14.2.3.7.2
Power Management
14.2.3.7.3
L3_MAIN Firewall Functionality
14.2.3.7.3.1
Protection Regions
14.2.3.7.3.2
L3_MAIN Firewall Registers Overview
14.2.3.7.3.3
Protection Mechanism per Region Examples
14.2.3.7.3.4
L3_MAIN Firewall Error Logging
14.2.3.7.3.5
L3_MAIN Firewall Default Configuration
14.2.3.8
L3_MAIN Interconnect Error Handling
14.2.3.8.1
Global Error-Routing Scheme
14.2.3.8.2
Slave NIU Error Logging
14.2.3.8.3
Flag Mux Error Logging
14.2.3.8.4
Severity Level of Standard and Custom Errors
14.2.3.8.5
Example for Decoding Standard/Custom Errors Logged in L3_MAIN
14.2.4
L3_MAIN Interconnect Programming Guide
14.2.4.1
L3 _MAIN Interconnect Low-Level Programming Models
14.2.4.1.1
Global Initialization
14.2.4.1.1.1
Global Initialization of Surrounding Modules
14.2.4.2
Operational Modes Configuration
14.2.4.2.1
L3_MAIN Interconnect Error Analysis Mode
14.2.4.2.1.1
Main Sequence: L3_MAIN Interconnect Error Analysis Mode
14.2.4.2.1.1.1
Subsequence: L3_MAIN Custom Error Identification
14.2.4.2.1.1.2
Subsequence: L3_MAIN Interconnect Protection Violation Error Identification
14.2.4.2.1.1.3
Subsequence: L3_MAIN Interconnect Standard Error Identification
14.2.4.2.1.1.4
Subsequence: L3_MAIN Interconnect FLAGMUX Configuration
14.2.5
L3_MAIN Interconnect Register Manual
14.2.5.1
L3_MAIN Register Group Summary
14.2.5.1.1
L3_MAIN Firewall Registers Summary and Description
14.2.5.1.1.1
L3_MAIN Firewall Registers Summary
14.2.5.1.1.2
L3_MAIN Firewall Registers Description
14.2.5.1.2
L3_MAIN Host Register Summary and Description
14.2.5.1.2.1
L3_MAIN HOST Register Summary
14.2.5.1.2.2
L3_MAIN HOST Register Description
14.2.5.1.3
L3_MAIN TARG Register Summary and Description
14.2.5.1.3.1
L3_MAIN TARG Register Summary
14.2.5.1.3.2
L3_MAIN TARG Register Description
14.2.5.1.4
L3_MAIN FLAGMUX Registers Summary and Description
14.2.5.1.4.1
L3_MAIN FLAGMUX Registers Summary
14.2.5.1.4.2
L3_MAIN FLAGMUX Rebisters Description
14.2.5.1.5
L3_MAIN FLAGMUX CLK1MERGE Registers Summary and Description
14.2.5.1.5.1
L3_MAIN FLAGMUX CLK1MERGE Registers Summary
14.2.5.1.5.2
L3_MAIN FLAGMUX CLK1MERGE Registers Description
14.2.5.1.6
L3_MAIN FLAGMUX TIMEOUT Registers Summary and Description
14.2.5.1.6.1
L3_MAIN FLAGMUX TIMEOUT Registers Summary
14.2.5.1.6.2
L3_MAIN FLAGMUX TIMEOUT Registers Description
14.2.5.1.7
L3_MAIN BW Regulator Register Summary and Description
14.2.5.1.7.1
L3_MAIN BW_REGULATOR Register Summary
14.2.5.1.7.2
L3_MAIN BW_REGULATOR Register Description
14.2.5.1.8
L3_MAIN Bandwidth Limiter Register Summary and Description
14.2.5.1.8.1
L3_MAIN BW Limiter Register Summary
14.2.5.1.8.2
L3_MAIN BW Limiter Register Description
14.2.5.1.9
L3_MAIN STATCOLL Register Summary and Description
14.2.5.1.9.1
L3_MAIN STATCOLL Register Summary
14.2.5.1.9.2
L3_MAIN STATCOLL Register Description
14.3
L4 Interconnects
14.3.1
L4 Interconnect Overview
14.3.2
L4 Interconnect Integration
14.3.3
L4 Interconnect Functional Description
14.3.3.1
Module Distribution
14.3.3.1.1
L4_PER1 Interconnect Agents
14.3.3.1.2
L4_PER2 Interconnect Agents
14.3.3.1.3
L4_PER3 Interconnect Agents
14.3.3.1.4
L4_CFG Interconnect Agents
14.3.3.1.5
L4_WKUP Interconnect Agents
14.3.3.2
Power Management
14.3.3.3
L4 Firewalls
14.3.3.3.1
Protection Group
14.3.3.3.2
Segments and Regions
14.3.3.3.3
L4 Firewall Address and Protection Register Settings
14.3.3.4
L4 Error Detection and Reporting
14.3.3.4.1
IA and TA Error Detection and Logging
14.3.3.4.2
Time-Out
14.3.3.4.3
Error Reporting
14.3.3.4.4
Error Recovery
14.3.3.4.5
Firewall Error Logging in the Control Module
14.3.4
L4 Interconnect Programming Guide
14.3.4.1
L4 Interconnect Low-level Programming Models
14.3.4.1.1
Global Initialization
14.3.4.1.1.1
Surrounding Modules Global Initialization
14.3.4.1.2
Operational Modes Configuration
14.3.4.1.2.1
L4 Interconnect Error Analysis Mode
14.3.4.1.2.1.1
Main Sequence: L4 Interconnect Error Analysis Mode
14.3.4.1.2.1.2
Subsequence: L4 Interconnect Protection Violation Error Identification
14.3.4.1.2.1.3
Subsequence: L4 Interconnect Unsupported Command/Address Hole Error Identification
14.3.4.1.2.1.4
Subsequence: L4 Interconnect Reset TA and Module
14.3.4.1.2.2
L4 Interconnect Time-Out Configuration Mode
14.3.4.1.2.2.1
Main Sequence: L4 Interconnect Time-Out Configuration Mode
14.3.4.1.2.3
L4 Interconnect Firewall Configuration Mode
14.3.4.1.2.3.1
Main Sequence: L4 Interconnect Firewall Configuration Mode
14.3.5
L4 Interconnects Register Manual
14.3.5.1
L4 Interconnects Instance Summary
14.3.5.2
L4 Initiator Agent (L4 IA)
14.3.5.2.1
L4 Initiator Agent (L4 IA) Register Summary
14.3.5.2.2
L4 Initiator Agent (L4 IA) Register Description
14.3.5.3
L4 Target Agent (L4 TA)
14.3.5.3.1
L4 Target Agent (L4 TA) Register Summary
14.3.5.3.2
L4 Target Agent (L4 TA) Register Description
14.3.5.4
L4 Link Agent (L4 LA)
14.3.5.4.1
L4 Link Agent (L4 LA) Register Summary
14.3.5.4.2
L4 Link Agent (L4 LA) Register Description
14.3.5.5
L4 Address Protection (L4 AP)
14.3.5.5.1
L4 Address Protection (L4 AP) Register Summary
14.3.5.5.2
L4 Address Protection (L4 AP) Register Description
15
Memory Subsystem
15.1
Memory Subsystem Overview
15.1.1
DMM Overview
15.1.2
TILER Overview
15.1.3
EMIF Overview
15.1.4
GPMC Overview
15.1.5
ELM Overview
15.1.6
OCM Overview
15.2
Dynamic Memory Manager
15.2.1
DMM Overview
15.2.2
DMM Integration
15.2.2.1
DMM Configuration
15.2.3
DMM Functional Description
15.2.3.1
DMM Block Diagram
15.2.3.2
DMM Clock Configuration
15.2.3.3
DMM Power Management
15.2.3.4
DMM Interrupt Requests
15.2.3.5
DMM
15.2.3.5.1
DMM Concepts
15.2.3.5.1.1
Dynamic Mapping
15.2.3.5.1.2
Address Mapping
15.2.3.5.1.3
Address Translation
15.2.3.5.1.3.1
PAT View Mappings
15.2.3.5.1.3.2
PAT View Map Base Address
15.2.3.5.1.3.3
PAT Views
15.2.3.5.1.3.3.1
PAT Direct Access Translation
15.2.3.5.1.3.3.2
PAT Indirect Access Translation
15.2.3.5.1.3.3.3
PAT View Configuration
15.2.3.5.1.3.3.4
PAT Address Translation LUT
15.2.3.5.1.3.3.5
Direct Access to the PAT Table Vectors
15.2.3.5.1.3.3.6
Automatic Refill Through the Refill Engines
15.2.3.5.2
DMM Transaction Flows
15.2.3.5.2.1
Nontiled Transaction Flow
15.2.3.5.2.2
Tiled Transaction Flow
15.2.3.5.3
DMM Internal Macro-Architecture
15.2.3.5.3.1
LISA Description
15.2.3.5.3.2
PAT Description
15.2.3.5.3.3
PEG Description
15.2.3.5.3.4
LISA Interconnect Arbitration
15.2.3.5.3.5
ROBIN Description
15.2.3.5.3.6
TILER Description
15.2.3.6
TILER
15.2.3.6.1
TILER Concepts
15.2.3.6.1.1
TILER Rationale
15.2.3.6.1.1.1
The TILER is a 4-GiB Virtual Address Space Composed of Eight Views
15.2.3.6.1.1.2
A View is a 512-MiB Virtual Address Space Composed of Four Containers
15.2.3.6.1.1.3
A Container is a 128-MiB Virtual Address Space
15.2.3.6.1.1.4
A Page is a 4-kiB Virtual Address Space
15.2.3.6.1.1.5
A Tile is a 1-kiB Address Space
15.2.3.6.1.1.6
1851
15.2.3.6.1.1.7
A Subtile is a 128-Bit Address Space
15.2.3.6.1.2
TILER Modes
15.2.3.6.1.2.1
Bypass Mode
15.2.3.6.1.2.2
Page Mode
15.2.3.6.1.2.3
Tiled Mode
15.2.3.6.1.3
Object Container Definition
15.2.3.6.1.4
Page Definition
15.2.3.6.1.4.1
Container Geometry With 4-kiB Pages
15.2.3.6.1.4.2
Container Geometry and Page Mapping Summary
15.2.3.6.1.5
Orientation
15.2.3.6.1.6
Tile Definition
15.2.3.6.1.7
Subtiles
15.2.3.6.1.7.1
Subtiling Definition
15.2.3.6.1.8
TILER Virtual Addressing
15.2.3.6.1.8.1
Page Mode Virtual Addressing and Characteristics
15.2.3.6.1.8.2
Tiled Mode Virtual Addressing and Characteristics
15.2.3.6.1.8.3
Element Ordering in the TILER Container
15.2.3.6.1.8.3.1
Natural View or 0-Degree View (Orientation 0)
15.2.3.6.1.8.3.2
0-Degree View With Vertical Mirror or 180-Degree View With Horizontal Mirror (Orientation 1)
15.2.3.6.1.8.3.3
0-Degree View With Horizontal Mirror or 180-Degree View With Vertical Mirror (Orientation 2)
15.2.3.6.1.8.3.4
180-Degree View (Orientation 3)
15.2.3.6.1.8.3.5
90-Degree View With Vertical Mirror or 270-Degree View With Horizontal Mirror (Orientation 4)
15.2.3.6.1.8.3.6
270-Degree View (Orientation 5)
15.2.3.6.1.8.3.7
90-Degree View (Orientation 6)
15.2.3.6.1.8.3.8
90-Degree View With Horizontal Mirror or 270-Degree View With Vertical Mirror (Orientation 7)
15.2.3.6.2
TILER Macro-Architecture
15.2.3.6.3
TILER Guidelines for Initiators
15.2.3.6.3.1
Buffered Raster-Based Initiators
15.2.3.6.3.1.1
Buffer Size
15.2.3.6.3.1.2
Performance
15.2.4
DMM Use Cases and Tips
15.2.4.1
PAT Use Cases
15.2.4.1.1
Simple Manual Area Refill
15.2.4.1.2
Single Auto-Configured Area Refill
15.2.4.1.3
Chained Auto-Configured Area Refill
15.2.4.1.4
Synchronized Auto-Configured Area Refill
15.2.4.1.5
Cyclic Synchronized Auto-Configured Area Refill
15.2.4.2
Addressing Management with LISA
15.2.4.2.1
Case 1: Use of One Memory Controller
15.2.5
DMM Basic Programming Model
15.2.5.1
Global Initialization
15.2.5.2
DMM Module Global Initialization
15.2.5.3
DMM Operational Modes Configuration
15.2.5.3.1
Different Operational Modes
15.2.5.3.2
Configuration Settings and LUT Refill
15.2.5.3.3
LISA Settings
15.2.5.3.4
Aliased Tiled View Orientation Settings and LUT Refill
15.2.5.3.5
Priority Settings
15.2.5.3.6
Error Handling
15.2.5.3.7
PAT Programming Model
15.2.5.3.7.1
PAT in Direct Translation Mode
15.2.5.3.7.2
PAT in Indirect Translation Mode
15.2.5.4
Addressing an Object in Tiled Mode
15.2.5.4.1
Frame-Buffer Addressing
15.2.5.4.2
TILER Page Mapping
15.2.5.5
Addressing an Object in Page Mode
15.2.5.6
Sharing Containers Between Different Modes
15.2.6
DMM Register Manual
15.2.6.1
DMM Instance Summary
15.2.6.2
DMM Registers
15.2.6.2.1
DMM Register Summary
15.2.6.2.2
DMM Register Description
15.3
EMIF Controller
15.3.1
EMIF Controller Overview
15.3.2
EMIF Module Environment
15.3.3
EMIF Module Integration
15.3.4
EMIF Functional Description
15.3.4.1
Block Diagram
15.3.4.1.1
Local Interface
15.3.4.1.2
FIFO Description
15.3.4.1.3
MPU Port Restrictions
15.3.4.1.4
Arbitration of Commands in the Command FIFO
15.3.4.2
Clock Management
15.3.4.2.1
EMIF_FICLK Overview
15.3.4.2.2
EMIF Dependency on MPU Clock Rate
15.3.4.3
Reset
15.3.4.4
System Power Management
15.3.4.4.1
Power-Down Mode
15.3.4.4.2
Self-Refresh Mode
15.3.4.5
Interrupt Requests
15.3.4.6
SDRAM Refresh Scheduling
15.3.4.7
SDRAM Initialization
15.3.4.7.1
DDR3/DDR3L SDRAM Initialization
15.3.4.8
DDR3/DDR3L Read-Write Leveling
15.3.4.8.1
Full Leveling
15.3.4.8.2
Software Leveling
15.3.4.9
EMIF Access Cycles
15.3.4.10
Turnaround Time
15.3.4.11
PHY DLL Calibration
15.3.4.12
SDRAM Address Mapping
15.3.4.12.1
Address Mapping for IBANK_POS = 0 and EBANK_POS = 0
15.3.4.12.2
Address Mapping for IBANK_POS = 1 and EBANK_POS = 0
15.3.4.12.3
Address Mapping for IBANK_POS = 2 and EBANK_POS = 0
15.3.4.12.4
Address Mapping for IBANK_POS = 3 and EBANK_POS = 0
15.3.4.12.5
Address Mapping for IBANK_POS = 0 and EBANK_POS = 1
15.3.4.12.6
Address Mapping for IBANK_POS = 1 and EBANK_POS = 1
15.3.4.12.7
Address Mapping for IBANK_POS = 2 and EBANK_POS = 1
15.3.4.12.8
1949
15.3.4.12.9
Address Mapping for IBANK_POS = 3 and EBANK_POS = 1
15.3.4.12.10
1951
15.3.4.13
DDR3/DDR3L Output Impedance Calibration
15.3.4.14
Error Correction And Detection Feature
15.3.4.15
Class of Service
15.3.4.16
Performance Counters
15.3.4.16.1
Performance Counters General Examples
15.3.4.17
Forcing CKE to tri-state
15.3.5
EMIF Programming Guide
15.3.5.1
EMIF Low-Level Programming Models
15.3.5.1.1
Global Initialization
15.3.5.1.1.1
EMIF Configuration Sequence
15.3.5.1.2
Operational Modes Configuration
15.3.5.1.2.1
EMIF Output Impedance Calibration Mode
15.3.5.1.2.2
EMIF SDRAM Self-Refresh
15.3.5.1.2.3
EMIF SDRAM Power-Down Mode
15.3.5.1.2.4
EMIF ECC Configuration
15.3.6
EMIF Register Manual
15.3.6.1
EMIF Instance Summary
15.3.6.2
EMIF Registers
15.3.6.2.1
EMIF Register Summary
15.3.6.2.2
EMIF Register Description
15.4
General-Purpose Memory Controller
15.4.1
GPMC Overview
15.4.2
GPMC Environment
15.4.2.1
GPMC Modes
15.4.2.2
GPMC Signals
15.4.3
GPMC Integration
15.4.4
GPMC Functional Description
15.4.4.1
GPMC Block Diagram
15.4.4.2
GPMC Clock Configuration
15.4.4.3
GPMC Software Reset
15.4.4.4
GPMC Power Management
15.4.4.5
GPMC Interrupt Requests
15.4.4.6
L3 Interconnect Interface
15.4.4.7
GPMC Address and Data Bus
15.4.4.7.1
GPMC I/O Configuration Setting
15.4.4.7.2
GPMC CS0 Default Configuration at Device Reset
15.4.4.8
Address Decoder and Chip-Select Configuration
15.4.4.8.1
Chip-Select Base Address and Region Size
15.4.4.8.2
Access Protocol
15.4.4.8.2.1
Supported Devices
15.4.4.8.2.2
Access Size Adaptation and Device Width
15.4.4.8.2.3
Address/Data-Multiplexing Interface
15.4.4.8.3
External Signals
15.4.4.8.3.1
Wait Pin Monitoring Control
15.4.4.8.3.1.1
Wait Monitoring During Asynchronous Read Access
15.4.4.8.3.1.2
Wait Monitoring During Asynchronous Write Access
15.4.4.8.3.1.3
Wait Monitoring During Synchronous Read Access
15.4.4.8.3.1.4
Wait Monitoring During Synchronous Write Access
15.4.4.8.3.1.5
Wait With NAND Device
15.4.4.8.3.1.6
Idle Cycle Control Between Successive Accesses
15.4.4.8.3.1.6.1
Bus Turnaround (BUSTURNAROUND)
15.4.4.8.3.1.6.2
Idle Cycles Between Accesses to Same Chip-Select (CYCLE2CYCLESAMECSEN, CYCLE2CYCLEDELAY)
15.4.4.8.3.1.6.3
Idle Cycles Between Accesses to Different Chip-Select (CYCLE2CYCLEDIFFCSEN, CYCLE2CYCLEDELAY)
15.4.4.8.3.1.7
Slow Device Support (TIMEPARAGRANULARITY Parameter)
15.4.4.8.3.2
Reset
15.4.4.8.3.3
Byte Enable (nBE1/nBE0)
15.4.4.8.4
Error Handling
15.4.4.9
Timing Setting
15.4.4.9.1
Read Cycle Time and Write Cycle Time (RDCYCLETIME / WRCYCLETIME)
15.4.4.9.2
nCS: Chip-Select Signal Control Assertion/Deassertion Time (CSONTIME / CSRDOFFTIME / CSWROFFTIME / CSEXTRADELAY)
15.4.4.9.3
nADV/ALE: Address Valid/Address Latch Enable Signal Control Assertion/Deassertion Time (ADVONTIME / ADVRDOFFTIME / ADVWROFFTIME / ADVEXTRADELAY/ADVAADMUXONTIME/ADVAADMUXRDOFFTIME/ADVAADMUXWROFFTIME)
15.4.4.9.4
nOE/nRE: Output Enable/Read Enable Signal Control Assertion/Deassertion Time (OEONTIME / OEOFFTIME / OEEXTRADELAY / OEAADMUXONTIME / OEAADMUXOFFTIME)
15.4.4.9.5
nWE: Write Enable Signal Control Assertion/Deassertion Time (WEONTIME / WEOFFTIME / WEEXTRADELAY)
15.4.4.9.6
GPMC_CLK
15.4.4.9.7
GPMC_CLK and Control Signals Setup and Hold
15.4.4.9.8
Access Time (RDACCESSTIME / WRACCESSTIME)
15.4.4.9.8.1
Access Time on Read Access
15.4.4.9.8.2
Access Time on Write Access
15.4.4.9.9
Page Burst Access Time (PAGEBURSTACCESSTIME)
15.4.4.9.9.1
Page Burst Access Time on Read Access
15.4.4.9.9.2
Page Burst Access Time on Write Access
15.4.4.9.10
Bus Keeping Support
15.4.4.10
NOR Access Description
15.4.4.10.1
Asynchronous Access Description
15.4.4.10.1.1
Access on Address/Data Multiplexed Devices
15.4.4.10.1.1.1
Asynchronous Single-Read Operation on an Address/Data Multiplexed Device
15.4.4.10.1.1.2
Asynchronous Single-Write Operation on an Address/Data-Multiplexed Device
15.4.4.10.1.1.3
Asynchronous Multiple (Page) Write Operation on an Address/Data-Multiplexed Device
15.4.4.10.1.2
Access on Address/Address/Data-Multiplexed Devices
15.4.4.10.1.2.1
Asynchronous Single Read Operation on an AAD-Multiplexed Device
15.4.4.10.1.2.2
Asynchronous Single-Write Operation on an AAD-Multiplexed Device
15.4.4.10.1.2.3
Asynchronous Multiple (Page) Read Operation on an AAD-Multiplexed Device
15.4.4.10.2
Synchronous Access Description
15.4.4.10.2.1
Synchronous Single Read
15.4.4.10.2.2
Synchronous Multiple (Burst) Read (4-, 8-, 16-Word16 Burst With Wraparound Capability)
15.4.4.10.2.3
Synchronous Single Write
15.4.4.10.2.4
Synchronous Multiple (Burst) Write
15.4.4.10.3
Asynchronous and Synchronous Accesses in Nonmultiplexed Mode
15.4.4.10.3.1
Asynchronous Single-Read Operation on Nonmultiplexed Device
15.4.4.10.3.2
Asynchronous Single-Write Operation on Nonmultiplexed Device
15.4.4.10.3.3
Asynchronous Multiple (Page Mode) Read Operation on Nonmultiplexed Device
15.4.4.10.3.4
Synchronous Operations on a Nonmultiplexed Device
15.4.4.10.4
Page and Burst Support
15.4.4.10.5
System Burst vs External Device Burst Support
15.4.4.11
pSRAM Access Specificities
15.4.4.12
NAND Access Description
15.4.4.12.1
NAND Memory Device in Byte or 16-bit Word Stream Mode
15.4.4.12.1.1
Chip-Select Configuration for NAND Interfacing in Byte or Word Stream Mode
15.4.4.12.1.2
NAND Device Command and Address Phase Control
15.4.4.12.1.3
Command Latch Cycle
15.4.4.12.1.4
Address Latch Cycle
15.4.4.12.1.5
NAND Device Data Read and Write Phase Control in Stream Mode
15.4.4.12.1.6
NAND Device General Chip-Select Timing Control Requirement
15.4.4.12.1.7
Read and Write Access Size Adaptation
15.4.4.12.1.7.1
8-Bit-Wide NAND Device
15.4.4.12.1.7.2
16-Bit-Wide NAND Device
15.4.4.12.2
NAND Device-Ready Pin
15.4.4.12.2.1
Ready Pin Monitored by Software Polling
15.4.4.12.2.2
Ready Pin Monitored by Hardware Interrupt
15.4.4.12.3
ECC Calculator
15.4.4.12.3.1
Hamming Code
15.4.4.12.3.1.1
ECC Result Register and ECC Computation Accumulation Size
15.4.4.12.3.1.2
ECC Enabling
15.4.4.12.3.1.3
ECC Computation
15.4.4.12.3.1.4
ECC Comparison and Correction
15.4.4.12.3.1.5
ECC Calculation Based on 8-Bit Word
15.4.4.12.3.1.6
ECC Calculation Based on 16-Bit Word
15.4.4.12.3.2
BCH Code
15.4.4.12.3.2.1
Requirements
15.4.4.12.3.2.2
Memory Mapping of BCH Codeword
15.4.4.12.3.2.2.1
Memory Mapping of Data Message
15.4.4.12.3.2.2.2
Memory-Mapping of the ECC
15.4.4.12.3.2.2.3
Wrapping Modes
4.4.12.3.2.2.3.1
Manual Mode (0x0)
4.4.12.3.2.2.3.2
Mode 0x1
4.4.12.3.2.2.3.3
Mode 0xA (10)
4.4.12.3.2.2.3.4
Mode 0x2
4.4.12.3.2.2.3.5
Mode 0x3
4.4.12.3.2.2.3.6
Mode 0x7
4.4.12.3.2.2.3.7
Mode 0x8
4.4.12.3.2.2.3.8
Mode 0x4
4.4.12.3.2.2.3.9
Mode 0x9
4.4.12.3.2.2.3.10
Mode 0x5
4.4.12.3.2.2.3.11
Mode 0xB (11)
4.4.12.3.2.2.3.12
Mode 0x6
15.4.4.12.3.2.3
Supported NAND Page Mappings and ECC Schemes
15.4.4.12.3.2.3.1
Per-Sector Spare Mappings
15.4.4.12.3.2.3.2
Pooled Spare Mapping
15.4.4.12.3.2.3.3
Per-Sector Spare Mapping, with ECC Separated at the End of the Page
15.4.4.12.4
Prefetch and Write-Posting Engine
15.4.4.12.4.1
General Facts About the Engine Configuration
15.4.4.12.4.2
Prefetch Mode
15.4.4.12.4.3
FIFO Control in Prefetch Mode
15.4.4.12.4.4
Write-Posting Mode
15.4.4.12.4.5
FIFO Control in Write-Posting Mode
15.4.4.12.4.6
Optimizing NAND Access Using the Prefetch and Write-Posting Engine
15.4.4.12.4.7
Interleaved Accesses Between Prefetch and Write-Posting Engine and Other Chip-Selects
15.4.5
GPMC Basic Programming Model
15.4.5.1
GPMC High-Level Programming Model Overview
15.4.5.2
GPMC Initialization
15.4.5.3
GPMC Configuration in NOR Mode
15.4.5.4
GPMC Configuration in NAND Mode
15.4.5.5
Set Memory Access
15.4.5.6
GPMC Timing Parameters
15.4.5.6.1
GPMC Timing Parameters Formulas
15.4.5.6.1.1
NAND Flash Interface Timing Parameters Formulas
15.4.5.6.1.2
Synchronous NOR Flash Timing Parameters Formulas
15.4.5.6.1.3
Asynchronous NOR Flash Timing Parameters Formulas
15.4.6
GPMC Use Cases and Tips
15.4.6.1
How to Set GPMC Timing Parameters for Typical Accesses
15.4.6.1.1
External Memory Attached to the GPMC Module
15.4.6.1.2
Typical GPMC Setup
15.4.6.1.2.1
GPMC Configuration for Synchronous Burst Read Access
15.4.6.1.2.2
GPMC Configuration for Asynchronous Read Access
15.4.6.1.2.3
GPMC Configuration for Asynchronous Single Write Access
15.4.6.2
How to Choose a Suitable Memory to Use With the GPMC
15.4.6.2.1
Supported Memories or Devices
15.4.6.2.1.1
Memory Pin Multiplexing
15.4.6.2.1.2
NAND Interface Protocol
15.4.6.2.1.3
NOR Interface Protocol
15.4.6.2.1.4
Other Technologies
15.4.6.2.1.5
Supported Protocols
15.4.6.2.2
GPMC Features and Settings
15.4.7
GPMC Register Manual
15.4.7.1
GPMC Register Summary
15.4.7.2
GPMC Register Descriptions
15.5
Error Location Module
15.5.1
Error Location Module Overview
15.5.2
ELM Integration
15.5.3
ELM Functional Description
15.5.3.1
ELM Software Reset
15.5.3.2
ELM Power Management
15.5.3.3
ELM Interrupt Requests
15.5.3.4
Processing Initialization
15.5.3.5
Processing Sequence
15.5.3.6
Processing Completion
15.5.4
ELM Basic Programming Model
15.5.4.1
ELM Low-Level Programming Model
15.5.4.1.1
Processing Initialization
15.5.4.1.2
Read Results
15.5.4.1.3
2142
15.5.4.2
Use Case: ELM Used in Continuous Mode
15.5.4.3
Use Case: ELM Used in Page Mode
15.5.5
ELM Register Manual
15.5.5.1
ELM Instance Summary
15.5.5.2
ELM Registers
15.5.5.2.1
ELM Register Summary
15.5.5.2.2
ELM Register Description
15.6
On-Chip Memory (OCM) Subsystem
15.6.1
OCM Subsystem Overview
15.6.2
OCM Subsystem Integration
15.6.3
OCM Subsystem Functional Desctiption
15.6.3.1
Block Diagram
15.6.3.2
Resets
15.6.3.3
Clock Management
15.6.3.4
Interrupt Requests
15.6.3.5
OCM Subsystem Memory Regions
15.6.3.6
OCM Controller Modes Of Operation
15.6.3.7
ECC Associated FIFOs
15.6.3.8
ECC Counters And Corrected Bit Distribution Register
15.6.3.9
ECC Support
15.6.3.10
Circular Buffer (CBUF) Support
15.6.3.11
CBUF Mode Error Handling
15.6.3.11.1
VBUF Address Not Mapped to a CBUF Memory Space
15.6.3.11.2
VBUF Access Not Starting At The Base Address
15.6.3.11.3
Illegal Address Change Between Two Same Type Accesses
15.6.3.11.4
Illegal Frame SIze (Short Frame Detection)
15.6.3.11.5
CBUF Overflow
15.6.3.11.6
CBUF Underflow
15.6.3.12
Status Reporting
15.6.4
OCM Subsystem Register Manual
15.6.4.1
OCM Subsystem Instance Summary
15.6.4.2
OCM Subsystem Registers
15.6.4.2.1
OCM Subsystem Register Summary
15.6.4.2.2
OCM Subsystem Register Description
16
DMA Controllers
16.1
System DMA
16.1.1
DMA_SYSTEM Module Overview
16.1.2
DMA_SYSTEM Controller Environment
16.1.3
DMA_SYSTEM Module Integration
16.1.3.1
DMA Requests to the DMA_SYSTEM Controller
16.1.3.2
Mapping of DMA Requests to DMA_CROSSBAR Inputs
16.1.4
DMA_SYSTEM Functional Description
16.1.4.1
DMA_SYSTEM Controller Power Management
16.1.4.2
DMA_SYSTEM Controller Interrupt Requests
16.1.4.2.1
Interrupt Generation
16.1.4.3
Logical Channel Transfer Overview
16.1.4.4
FIFO Queue Memory Pool
16.1.4.5
Addressing Modes
16.1.4.6
Packed Accesses
16.1.4.7
Burst Transactions
16.1.4.8
Endianism Conversion
16.1.4.9
Transfer Synchronization
16.1.4.9.1
Software Synchronization
16.1.4.9.2
Hardware Synchronization
16.1.4.10
Thread Budget Allocation
16.1.4.11
FIFO Budget Allocation
16.1.4.12
Chained Logical Channel Transfers
16.1.4.13
Reprogramming an Active Channel
16.1.4.14
Packet Synchronization
16.1.4.15
Graphics Acceleration Support
16.1.4.16
Supervisor Modes
16.1.4.17
Posted and Nonposted Writes
16.1.4.18
Disabling a Channel During Transfer
16.1.4.19
FIFO Draining Mechanism
16.1.4.20
Linked List
16.1.4.20.1
Overview
16.1.4.20.2
Link-List Transfer Profile
16.1.4.20.3
Descriptors
16.1.4.20.3.1
Type 1
16.1.4.20.3.2
Type 2
16.1.4.20.3.3
Type 3
16.1.4.20.4
Linked-List Control and Monitoring
16.1.4.20.4.1
Transfer Mode Setting
16.1.4.20.4.2
Starting a Linked List
16.1.4.20.4.3
Monitoring a Linked-List Progression
16.1.4.20.4.4
Interrupt During Linked-List Execution
16.1.4.20.4.5
Pause a Linked List
16.1.4.20.4.6
Stop a Linked List (Abort or Drain)
16.1.4.20.4.6.1
Drain
16.1.4.20.4.6.2
Abort
16.1.4.20.4.7
Status Bit Behavior
16.1.4.20.4.8
Linked-List Channel Linking
16.1.5
DMA_SYSTEM Basic Programming Model
16.1.5.1
Setup Configuration
16.1.5.2
Software-Triggered (Nonsynchronized) Transfer
16.1.5.3
Hardware-Synchronized Transfer
16.1.5.4
Synchronized Transfer Monitoring Using CDAC
16.1.5.5
Concurrent Software and Hardware Synchronization
16.1.5.6
Chained Transfer
16.1.5.7
90-Degree Clockwise Image Rotation
16.1.5.8
Graphic Operations
16.1.5.9
Linked-List Programming Guidelines
16.1.6
DMA_SYSTEM Register Manual
16.1.6.1
DMA_SYSTEM Instance Summary
16.1.6.2
DMA_SYSTEM Registers
16.1.6.2.1
DMA_SYSTEM Register Summary
16.1.6.2.2
DMA_SYSTEM Register Description
16.2
Enhanced DMA
16.2.1
EDMA Module Overview
16.2.1.1
EDMA Features
16.2.1.2
2243
16.2.1.3
EDMA Controllers Configuration
16.2.2
EDMA Controller Environment
16.2.3
EDMA Controller Integration
16.2.3.1
EDMA Requests to the EDMA Controller
16.2.4
EDMA Controller Functional Description
16.2.4.1
Block Diagram
16.2.4.1.1
Third-Party Channel Controller
16.2.4.1.2
Third-Party Transfer Controller
16.2.4.2
Types of EDMA controller Transfers
16.2.4.2.1
A-Synchronized Transfers
16.2.4.2.2
AB-Synchronized Transfers
16.2.4.3
Parameter RAM (PaRAM)
16.2.4.3.1
PaRAM
16.2.4.3.2
EDMA Channel PaRAM Set Entry Fields
16.2.4.3.2.1
Channel Options Parameter (OPT)
16.2.4.3.2.2
Channel Source Address (SRC)
16.2.4.3.2.3
Channel Destination Address (DST)
16.2.4.3.2.4
Count for 1st Dimension (ACNT)
16.2.4.3.2.5
Count for 2nd Dimension (BCNT)
16.2.4.3.2.6
Count for 3rd Dimension (CCNT)
16.2.4.3.2.7
BCNT Reload (BCNTRLD)
16.2.4.3.2.8
Source B Index (SBIDX)
16.2.4.3.2.9
Destination B Index (DBIDX)
16.2.4.3.2.10
Source C Index (SCIDX)
16.2.4.3.2.11
Destination C Index (DCIDX)
16.2.4.3.2.12
Link Address (LINK)
16.2.4.3.3
Null PaRAM Set
16.2.4.3.4
Dummy PaRAM Set
16.2.4.3.5
Dummy Versus Null Transfer Comparison
16.2.4.3.6
Parameter Set Updates
16.2.4.3.7
Linking Transfers
16.2.4.3.8
Constant Addressing Mode Transfers/Alignment Issues
16.2.4.3.9
Element Size
16.2.4.4
Initiating a DMA Transfer
16.2.4.4.1
DMA Channel
16.2.4.4.1.1
Event-Triggered Transfer Request
16.2.4.4.1.2
Manually-Triggered Transfer Request
16.2.4.4.1.3
Chain-Triggered Transfer Request
16.2.4.4.2
QDMA Channels
16.2.4.4.2.1
Auto-triggered and Link-Triggered Transfer Request
16.2.4.4.3
Comparison Between DMA and QDMA Channels
16.2.4.5
Completion of a DMA Transfer
16.2.4.5.1
Normal Completion
16.2.4.5.2
Early Completion
16.2.4.5.3
Dummy or Null Completion
16.2.4.6
Event, Channel, and PaRAM Mapping
16.2.4.6.1
DMA Channel to PaRAM Mapping
16.2.4.6.2
QDMA Channel to PaRAM Mapping
16.2.4.7
EDMA Channel Controller Regions
16.2.4.7.1
Region Overview
16.2.4.7.2
Channel Controller Regions
16.2.4.7.2.1
Resource Pool Division Across Two Regions
16.2.4.7.3
Region Interrupts
16.2.4.8
Chaining EDMA Channels
16.2.4.9
EDMA Interrupts
16.2.4.9.1
Transfer Completion Interrupts
16.2.4.9.1.1
Enabling Transfer Completion Interrupts
16.2.4.9.1.2
Clearing Transfer Completion Interrupts
16.2.4.9.2
EDMA Interrupt Servicing
16.2.4.9.3
Interrupt Servicing
16.2.4.9.4
2304
16.2.4.9.5
Interrupt Servicing
16.2.4.9.6
Interrupt Evaluation Operations
16.2.4.9.7
Error Interrupts
16.2.4.9.8
2308
16.2.4.10
Memory Protection
16.2.4.10.1
Active Memory Protection
16.2.4.10.2
Proxy Memory Protection
16.2.4.11
Event Queue(s)
16.2.4.11.1
DMA/QDMA Channel to Event Queue Mapping
16.2.4.11.2
Queue RAM Debug Visibility
16.2.4.11.3
Queue Resource Tracking
16.2.4.11.4
Performance Considerations
16.2.4.12
EDMA Transfer Controller (EDMA_TPTC)
16.2.4.12.1
Architecture Details
16.2.4.12.1.1
Command Fragmentation
16.2.4.12.1.2
TR Pipelining
16.2.4.12.1.3
Command Fragmentation (DBS = 64)
16.2.4.12.1.4
Performance Tuning
16.2.4.12.2
Memory Protection
16.2.4.12.3
Error Generation
16.2.4.12.4
Debug Features
16.2.4.12.4.1
Destination FIFO Register Pointer
16.2.4.12.5
EDMA_TPTC Configuration
16.2.4.13
Event Dataflow
16.2.4.14
EDMA controller Prioritization
16.2.4.14.1
Channel Priority
16.2.4.14.2
Trigger Source Priority
16.2.4.14.3
Dequeue Priority
16.2.4.15
EDMA Power, Reset and Clock Management
16.2.4.15.1
Clock and Power Management
16.2.4.15.2
Reset Considerations
16.2.4.16
Emulation Considerations
16.2.5
EDMA Transfer Examples
16.2.5.1
Block Move Example
16.2.5.2
Subframe Extraction Example
16.2.5.3
Data Sorting Example
16.2.5.4
Peripheral Servicing Example
16.2.5.4.1
Non-bursting Peripherals
16.2.5.4.2
Bursting Peripherals
16.2.5.4.3
Continuous Operation
16.2.5.4.3.1
Receive Channel
16.2.5.4.3.2
Transmit Channel
16.2.5.4.3.3
2347
16.2.5.4.4
Ping-Pong Buffering
16.2.5.4.4.1
Synchronization with the CPU
16.2.5.4.5
Transfer Chaining Examples
16.2.5.4.5.1
Servicing Input/Output FIFOs with a Single Event
16.2.5.4.5.2
Breaking Up Large Transfers with Intermediate Chaining
16.2.5.5
Setting Up an EDMA Transfer
16.2.5.5.1
2354
16.2.6
EDMA Debug Checklist and Programming Tips
16.2.6.1
EDMA Debug Checklist
16.2.6.2
EDMA Programming Tips
16.2.7
EDMA Register Manual
16.2.7.1
EDMA Instance Summary
16.2.7.2
EDMA Registers
16.2.7.2.1
EDMA Register Summary
16.2.7.2.2
EDMA Register Description
16.2.7.2.2.1
EDMA_TPCC Register Description
16.2.7.2.2.2
EDMA_TPTC0 and EDMA_TPTC1 Register Description
17
Interrupt Controllers
17.1
Interrupt Controllers Overview
17.2
Interrupt Controllers Environment
17.3
Interrupt Controllers Integration
17.3.1
Interrupt Requests to MPU_INTC
17.3.2
Interrupt Requests to DSP1_INTC
17.3.3
Interrupt Requests to IPU1_Cx_INTC
17.3.4
Interrupt Requests to IPU2_Cx_INTC
17.3.5
Interrupt Requests to PRUSS1_INTC
17.3.6
Interrupt Requests to PRUSS2_INTC
17.3.7
Mapping of Device Interrupts to IRQ_CROSSBAR Inputs
17.4
Interrupt Controllers Functional Description
18
Control Module
18.1
Control Module Overview
18.2
Control Module Environment
18.3
Control Module Integration
18.4
Control Module Functional Description
18.4.1
Control Module Clock Configuration
18.4.2
Control Module Resets
18.4.3
Control Module Power Management
18.4.3.1
Power Management Protocols
18.4.4
Hardware Requests
18.4.5
Control Module Initialization
18.4.6
Functional Description Of The Various Register Types In CTRL_MODULE_CORE Submodule
18.4.6.1
Pad Configuration
18.4.6.1.1
Pad Configuration Registers
18.4.6.1.1.1
Permanent PU/PD disabling (SR 2.x only)
18.4.6.1.2
Pull Selection
18.4.6.1.3
Pad multiplexing
18.4.6.1.4
IOSETs
18.4.6.1.5
Virtual IO Timing Modes
18.4.6.1.6
Manual IO Timing Modes
18.4.6.1.7
Isolation Requirements
18.4.6.1.8
IO Delay Recalibration
18.4.6.2
Thermal Management Related Registers
18.4.6.2.1
Temperature Sensors Control Registers
18.4.6.2.2
Registers For The Thermal Alert Comparators
18.4.6.2.3
Thermal Shutdown Comparators
18.4.6.2.4
Temperature Timestamp Registers
18.4.6.2.5
Other Thermal Management Related Registers
18.4.6.2.6
Summary Of The Thermal Management Related Registers
18.4.6.2.7
ADC Values Versus Temperature
18.4.6.3
PBIAS Cell And MMC1 I/O Cells Control Registers
18.4.6.4
IRQ_CROSSBAR Module Functional Description
18.4.6.5
DMA_CROSSBAR Module Functional Description
18.4.6.6
SDRAM Initiator Priority Registers
18.4.6.7
L3_MAIN Initiator Priority Registers
18.4.6.8
Memory Region Lock Registers
18.4.6.9
NMI Mapping To Respective Cores
18.4.6.10
Software Controls for the DDR3 I/O Cells
18.4.6.11
Reference Voltage for the Device DDR3 Receivers
18.4.6.12
AVS Class 0 Associated Registers
18.4.6.13
ABB Associated Registers
18.4.6.14
Registers For Other Miscellaneous Functions
18.4.6.14.1
System Boot Status Settings
18.4.6.14.2
Force MPU Write Nonposted Transactions
18.4.6.14.3
Firewall Error Status Registers
18.4.6.14.4
Settings Related To Different Peripheral Modules
18.4.7
Functional Description Of The Various Register Types In CTRL_MODULE_WKUP Submodule
18.4.7.1
Registers For Basic EMIF configuration
18.5
Control Module Register Manual
18.6
IODELAYCONFIG Module Integration
18.7
IODELAYCONFIG Module Register Manual
19
Mailbox
19.1
Mailbox Overview
19.2
Mailbox Integration
19.2.1
System MAILBOX Integration
19.2.2
IVA Mailbox Integration
19.3
Mailbox Functional Description
19.3.1
Mailbox Block Diagram
19.3.1.1
2435
19.3.2
Mailbox Software Reset
19.3.3
Mailbox Power Management
19.3.4
Mailbox Interrupt Requests
19.3.5
Mailbox Assignment
19.3.5.1
Description
19.3.6
Sending and Receiving Messages
19.3.6.1
Description
19.3.7
16-Bit Register Access
19.3.7.1
Description
19.3.8
Example of Communication
19.4
Mailbox Programming Guide
19.4.1
Mailbox Low-level Programming Models
19.4.1.1
Global Initialization
19.4.1.1.1
Surrounding Modules Global Initialization
19.4.1.1.2
Mailbox Global Initialization
19.4.1.1.2.1
Main Sequence - Mailbox Global Initialization
19.4.1.2
Mailbox Operational Modes Configuration
19.4.1.2.1
Mailbox Processing modes
19.4.1.2.1.1
Main Sequence - Sending a Message (Polling Method)
19.4.1.2.1.2
Main Sequence - Sending a Message (Interrupt Method)
19.4.1.2.1.3
Main Sequence - Receiving a Message (Polling Method)
19.4.1.2.1.4
Main Sequence - Receiving a Message (Interrupt Method)
19.4.1.3
Mailbox Events Servicing
19.4.1.3.1
Events Servicing in Sending Mode
19.4.1.3.2
Events Servicing in Receiving Mode
19.5
Mailbox Register Manual
19.5.1
Mailbox Instance Summary
19.5.2
Mailbox Registers
19.5.2.1
Mailbox Register Summary
19.5.2.2
Mailbox Register Description
20
Memory Management Units
20.1
MMU Overview
20.2
MMU Integration
20.3
MMU Functional Description
20.3.1
MMU Block Diagram
20.3.1.1
MMU Address Translation Process
20.3.1.2
Translation Tables
20.3.1.2.1
Translation Table Hierarchy
20.3.1.2.2
First-Level Translation Table
20.3.1.2.2.1
First-Level Descriptor Format
20.3.1.2.2.2
First-Level Page Descriptor Format
20.3.1.2.2.3
First-Level Section Descriptor Format
20.3.1.2.2.4
Section Translation Summary
20.3.1.2.2.5
Supersection Translation Summary
20.3.1.2.3
Two-Level Translation
20.3.1.2.3.1
Second-Level Descriptor Format
20.3.1.2.3.2
Small Page Translation Summary
20.3.1.2.3.3
Large Page Translation Summary
20.3.1.3
Translation Lookaside Buffer
20.3.1.3.1
TLB Entry Format
20.3.1.4
No Translation (Bypass) Regions
20.3.2
MMU Software Reset
20.3.3
MMU Power Management
20.3.4
MMU Interrupt Requests
20.3.5
MMU Error Handling
20.4
MMU Low-level Programming Models
20.4.1
Global Initialization
20.4.1.1
Surrounding Modules Global Initialization
20.4.1.2
MMU Global Initialization
20.4.1.2.1
Main Sequence - MMU Global Initialization
20.4.1.2.2
Subsequence - Configure a TLB entry
20.4.1.3
Operational Modes Configuration
20.4.1.3.1
Main Sequence - Writing TLB Entries Statically
20.4.1.3.2
Main Sequence - Protecting TLB Entries
20.4.1.3.3
Main Sequence - Deleting TLB Entries
20.4.1.3.4
Main Sequence - Read TLB Entries
20.5
MMU Register Manual
20.5.1
MMU Instance Summary
20.5.2
MMU Registers
20.5.2.1
MMU Register Summary
20.5.2.2
MMU Register Description
21
Spinlock
21.1
Spinlock Overview
21.2
Spinlock Integration
21.3
Spinlock Functional Description
21.3.1
Spinlock Software Reset
21.3.2
Spinlock Power Management
21.3.3
About Spinlocks
21.3.4
Spinlock Functional Operation
21.4
Spinlock Programming Guide
21.4.1
Spinlock Low-level Programming Models
21.4.1.1
Surrounding Modules Global Initialization
21.4.1.2
Basic Spinlock Operations
21.4.1.2.1
Spinlocks Clearing After a System Bug Recovery
21.4.1.2.2
Take and Release Spinlock
21.5
Spinlock Register Manual
21.5.1
Spinlock Instance Summary
21.5.2
Spinlock Registers
21.5.2.1
Spinlock Register Summary
21.5.2.2
Spinlock Register Description
22
Timers
22.1
Timers Overview
22.2
General-Purpose Timers
22.2.1
General-Purpose Timers Overview
22.2.1.1
GP Timer Features
22.2.2
GP Timer Environment
22.2.2.1
GP Timer External System Interface
22.2.3
GP Timer Integration
22.2.4
GP Timer Functional Description
22.2.4.1
GP Timer Block Diagram
22.2.4.2
TIMER1, TIMER2 and TIMER10 Power Management
22.2.4.2.1
Wake-Up Capability
22.2.4.3
Power Management of Other GP Timers
22.2.4.3.1
Wake-Up Capability
22.2.4.4
Software Reset
22.2.4.5
GP Timer Interrupts
22.2.4.6
Timer Mode Functionality
22.2.4.6.1
1-ms Tick Generation (Only TIMER1, TIMER2 and TIMER10)
22.2.4.7
Capture Mode Functionality
22.2.4.8
Compare Mode Functionality
22.2.4.9
Prescaler Functionality
22.2.4.10
Pulse-Width Modulation
22.2.4.11
Timer Counting Rate
22.2.4.12
Timer Under Emulation
22.2.4.13
Accessing GP Timer Registers
22.2.4.13.1
Writing to Timer Registers
22.2.4.13.1.1
Write Posting Synchronization Mode
22.2.4.13.1.2
Write Nonposting Synchronization Mode
22.2.4.13.2
Reading From Timer Counter Registers
22.2.4.13.2.1
Read Posted
22.2.4.13.2.2
Read Non-Posted
22.2.4.14
Posted Mode Selection
22.2.5
GP Timer Low-Level Programming Models
22.2.5.1
Global Initialization
22.2.5.1.1
Global Initialization of Surrounding Modules
22.2.5.1.2
GP Timer Module Global Initialization
22.2.5.1.2.1
Main Sequence – GP Timer Module Global Initialization
22.2.5.2
Operational Mode Configuration
22.2.5.2.1
GP Timer Mode
22.2.5.2.1.1
Main Sequence – GP Timer Mode Configuration
22.2.5.2.2
GP Timer Compare Mode
22.2.5.2.2.1
Main Sequence – GP Timer Compare Mode Configuration
22.2.5.2.3
GP Timer Capture Mode
22.2.5.2.3.1
Main Sequence – GP Timer Capture Mode Configuration
22.2.5.2.3.2
Subsequence – Initialize Capture Mode
22.2.5.2.3.3
Subsequence – Detect Event
22.2.5.2.4
GP Timer PWM Mode
22.2.5.2.4.1
Main Sequence – GP Timer PWM Mode Configuration
22.2.6
GP Timer Register Manual
22.2.6.1
GP Timer Instance Summary
22.2.6.2
GP Timer Registers
22.2.6.2.1
GP Timer Register Summary
22.2.6.2.2
GP Timer Register Description
22.2.6.2.3
TIMER1, TIMER2, and TIMER10 Register Description
22.3
32-kHz Synchronized Timer (COUNTER_32K)
22.3.1
32-kHz Synchronized Timer Overview
22.3.1.1
32-kHz Synchronized Timer Features
22.3.2
32-kHz Synchronized Timer Integration
22.3.3
32-kHz Synchronized Timer Functional Description
22.3.3.1
Reading the 32-kHz Synchronized Timer
22.3.4
COUNTER_32K Timer Register Manual
22.3.4.1
COUNTER_32K Timer Register Mapping Summary
22.3.4.2
COUNTER_32K Timer Register Description
22.4
Watchdog Timer
22.4.1
Watchdog Timer Overview
22.4.1.1
Watchdog Timer Features
22.4.2
Watchdog Timer Integration
22.4.3
Watchdog Timer Functional Description
22.4.3.1
Power Management
22.4.3.1.1
Wake-Up Capability
22.4.3.2
Interrupts
22.4.3.3
General Watchdog Timer Operation
22.4.3.4
Reset Context
22.4.3.5
Overflow/Reset Generation
22.4.3.6
Prescaler Value/Timer Reset Frequency
22.4.3.7
Triggering a Timer Reload
22.4.3.8
Start/Stop Sequence for Watchdog Timer (Using the WSPR Register)
22.4.3.9
Modifying Timer Count/Load Values and Prescaler Setting
22.4.3.10
Watchdog Counter Register Access Restriction (WCRR)
22.4.3.11
Watchdog Timer Interrupt Generation
22.4.3.12
Watchdog Timer Under Emulation
22.4.3.13
Accessing Watchdog Timer Registers
22.4.4
Watchdog Timer Low-Level Programming Model
22.4.4.1
Global Initialization
22.4.4.1.1
Surrounding Modules Global Initialization
22.4.4.1.2
Watchdog Timer Module Global Initialization
22.4.4.1.2.1
Main Sequence – Watchdog Timer Module Global Initialization
22.4.4.2
Operational Mode Configuration
22.4.4.2.1
Watchdog Timer Basic Configuration
22.4.4.2.1.1
Main Sequence – Watchdog Timer Basic Configuration
22.4.4.2.1.2
Subsequence – Disable the Watchdog Timer
22.4.4.2.1.3
Subsequence – Enable the Watchdog Timer
22.4.5
Watchdog Timer Register Manual
22.4.5.1
Watchdog Timer Instance Summary
22.4.5.2
Watchdog Timer Registers
22.4.5.2.1
Watchdog Timer Register Summary
22.4.5.2.2
2622
22.4.5.2.3
Watchdog Timer Register Description
23
Real-Time Clock (RTC)
23.1
RTC Overview
23.1.1
RTC Features
23.2
RTC Environment
23.2.1
RTC External Interface
23.3
RTC Integration
23.4
RTC Functional Description
23.4.1
Clock Source
23.4.2
Interrupt Support
23.4.2.1
CPU Interrupts
23.4.2.2
Interrupt Description
23.4.2.2.1
Timer Interrupt (timer_intr)
23.4.2.2.2
Alarm Interrupt (alarm_intr)
23.4.3
RTC Programming/Usage Guide
23.4.3.1
Time/Calendar Data Format
23.4.3.2
Register Access
23.4.3.3
Register Spurious Write Protection
23.4.3.4
Reading the Timer/Calendar (TC) Registers
23.4.3.4.1
Rounding Seconds
23.4.3.5
Modifying the TC Registers
23.4.3.5.1
General Registers
23.4.3.6
Crystal Compensation
23.4.4
Scratch Registers
23.4.5
Debouncing
23.4.6
Power Management
23.4.6.1
Device-Level Power Management
23.4.6.2
Subsystem-Level Power Management — PMIC Mode
23.5
RTC Low-Level Programming Guide
23.5.1
Global Initialization
23.5.1.1
Surrounding Modules Global Initialization
23.5.1.2
RTC Module Global Initialization
23.5.1.2.1
Main Sequence – RTC Module Global Initialization
23.6
RTC Register Manual
23.6.1
RTC Instance Summary
23.6.2
RTC_SS Registers
23.6.2.1
RTC_SS Register Summary
23.6.2.2
RTC_SS Register Description
24
Serial Communication Interfaces
24.1
Multimaster High-Speed I2C Controller
24.1.1
HS I2C Overview
24.1.2
HS I2C Environment
24.1.2.1
HS I2C Typical Application
24.1.2.1.1
HS I2C Pins for Typical Connections in I2C Mode
24.1.2.1.2
HS I2C Interface Typical Connections
24.1.2.1.3
2668
24.1.2.2
HS I2C Typical Connection Protocol and Data Format
24.1.2.2.1
HS I2C Serial Data Format
24.1.2.2.2
HS I2C Data Validity
24.1.2.2.3
HS I2C Start and Stop Conditions
24.1.2.2.4
HS I2C Addressing
24.1.2.2.4.1
Data Transfer Formats in F/S Mode
24.1.2.2.4.2
Data Transfer Format in HS Mode
24.1.2.2.5
HS I2C Master Transmitter
24.1.2.2.6
HS I2C Master Receiver
24.1.2.2.7
HS I2C Slave Transmitter
24.1.2.2.8
HS I2C Slave Receiver
24.1.2.2.9
HS I2C Bus Arbitration
24.1.2.2.10
HS I2C Clock Generation and Synchronization
24.1.3
HS I2C Integration
24.1.4
HS I2C Functional Description
24.1.4.1
HS I2C Block Diagram
24.1.4.2
HS I2C Clocks
24.1.4.2.1
HS I2C Clocking
24.1.4.2.2
HS I2C Automatic Blocking of the I2C Clock Feature
24.1.4.3
HS I2C Software Reset
24.1.4.4
HS I2C Power Management
24.1.4.5
HS I2C Interrupt Requests
24.1.4.6
HS I2C DMA Requests
24.1.4.7
HS I2C Programmable Multislave Channel Feature
24.1.4.8
HS I2C FIFO Management
24.1.4.8.1
HS I2C FIFO Interrupt Mode
24.1.4.8.2
HS I2C FIFO Polling Mode
24.1.4.8.3
HS I2C FIFO DMA Mode
24.1.4.8.4
HS I2C Draining Feature
24.1.4.9
HS I2C Noise Filter
24.1.4.10
HS I2C System Test Mode
24.1.5
HS I2C Programming Guide
24.1.5.1
HS I2C Low-Level Programming Models
24.1.5.1.1
HS I2C Programming Model
24.1.5.1.1.1
Main Program
24.1.5.1.1.1.1
Configure the Module Before Enabling the I2C Controller
24.1.5.1.1.1.2
Initialize the I2C Controller
24.1.5.1.1.1.3
Configure Slave Address and the Data Control Register
24.1.5.1.1.1.4
Initiate a Transfer
24.1.5.1.1.1.5
Receive Data
24.1.5.1.1.1.6
Transmit Data
24.1.5.1.1.2
Interrupt Subroutine Sequence
24.1.5.1.1.3
Programming Flow-Diagrams
24.1.6
HS I2C Register Manual
24.1.6.1
HS I2C Instance Summary
24.1.6.2
HS I2C Registers
24.1.6.2.1
HS I2C Register Summary
24.1.6.2.2
HS I2C Register Description
24.2
HDQ/1-Wire
24.2.1
HDQ1W Overview
24.2.2
HDQ1W Environment
24.2.2.1
HDQ1W Functional Modes
24.2.2.2
HDQ and 1-Wire (SDQ) Protocols
24.2.2.2.1
HDQ Protocol Initialization (Default)
24.2.2.2.2
1-Wire (SDQ) Protocol Initialization
24.2.2.2.3
Communication Sequence (HDQ and 1-Wire Protocols)
24.2.3
HDQ1W Integration
24.2.4
HDQ1W Functional Description
24.2.4.1
HDQ1W Block Diagram
24.2.4.2
HDQ1W Clocking Configuration
24.2.4.2.1
HDQ1W Clocks
24.2.4.3
HDQ1W Hardware and Software Reset
24.2.4.4
HDQ1W Power Management
24.2.4.4.1
Auto-Idle Mode
24.2.4.4.2
Power-Down Mode
24.2.4.4.3
2734
24.2.4.5
HDQ Interrupt Requests
24.2.4.6
HDQ Mode (Default)
24.2.4.6.1
HDQ Mode Features
24.2.4.6.2
Description
24.2.4.6.3
Single-Bit Mode
24.2.4.6.4
Interrupt Conditions
24.2.4.7
1-Wire Mode
24.2.4.7.1
1-Wire Mode Features
24.2.4.7.2
Description
24.2.4.7.3
1-Wire Single-Bit Mode Operation
24.2.4.7.4
Interrupt Conditions
24.2.4.7.5
Status Flags
24.2.4.8
BITFSM Delay
24.2.5
HDQ1W Low-Level Programming Model
24.2.5.1
Global Initialization
24.2.5.1.1
Surrounding Modules Global Initialization
24.2.5.1.2
HDQ1W Module Global Initialization
24.2.5.2
HDQ Operational Modes Configuration
24.2.5.2.1
Main Sequence - HDQ Write Operation Mode
24.2.5.2.2
Main Sequence - HDQ Read Operation Mode
24.2.5.2.2.1
Sub-sequence - Initialize HDQ Slave
24.2.5.3
1-Wire Operational Modes Configuration
24.2.5.3.1
Main Sequence - 1-Wire Write Operation Mode
24.2.5.3.2
Main Sequence - 1-Wire Read Operation Mode
24.2.5.3.3
Sub-sequence - Initialize 1-Wire Slave
24.2.6
HDQ1W Register Manual
24.2.6.1
HDQ1W Instance Summary
24.2.6.2
HDQ1W Registers
24.2.6.2.1
HDQ1W Register Summary
24.2.6.2.2
HDQ1W Register Description
24.3
UART/IrDA/CIR
24.3.1
UART/IrDA/CIR Overview
24.3.1.1
UART Features
24.3.1.2
IrDA Features
24.3.1.3
CIR Features
24.3.2
UART/IrDA/CIR Environment
24.3.2.1
UART Interface
24.3.2.1.1
System Using UART Communication With Hardware Handshake
24.3.2.1.2
UART Interface Description
24.3.2.1.3
UART Protocol and Data Format
24.3.2.2
IrDA Functional Interfaces
24.3.2.2.1
System Using IrDA Communication Protocol
24.3.2.2.2
IrDA Interface Description
24.3.2.2.3
IrDA Protocol and Data Format
24.3.2.2.3.1
SIR Mode
24.3.2.2.3.1.1
Frame Format
24.3.2.2.3.1.2
Asynchronous Transparency
24.3.2.2.3.1.3
Abort Sequence
24.3.2.2.3.1.4
Pulse Shaping
24.3.2.2.3.1.5
Encoder
24.3.2.2.3.1.6
Decoder
24.3.2.2.3.1.7
IR Address Checking
24.3.2.2.3.2
SIR Free-Format Mode
24.3.2.2.3.3
MIR Mode
24.3.2.2.3.3.1
MIR Encoder/Decoder
24.3.2.2.3.3.2
SIP Generation
24.3.2.2.3.4
FIR Mode
24.3.2.3
CIR Functional Interfaces
24.3.2.3.1
System Using CIR Communication Protocol With Remote Control
24.3.2.3.2
CIR Interface Description
24.3.2.3.3
CIR Protocol and Data Format
24.3.2.3.3.1
Carrier Modulation
24.3.2.3.3.2
Pulse Duty Cycle
24.3.2.3.3.3
Consumer IR Encoding/Decoding
24.3.3
UART/IrDA/CIR Integration
24.3.3.1
2800
24.3.4
UART/IrDA/CIR Functional Description
24.3.4.1
Block Diagram
24.3.4.2
Clock Configuration
24.3.4.3
Software Reset
24.3.4.4
Power Management
24.3.4.4.1
UART Mode Power Management
24.3.4.4.1.1
Module Power Saving
24.3.4.4.1.2
System Power Saving
24.3.4.4.2
IrDA Mode Power Management (UART3 Only)
24.3.4.4.2.1
Module Power Saving
24.3.4.4.2.2
System Power Saving
24.3.4.4.3
CIR Mode Power Management (UART3 Only)
24.3.4.4.3.1
Module Power Saving
24.3.4.4.3.2
System Power Saving
24.3.4.4.4
Local Power Management
24.3.4.5
Interrupt Requests
24.3.4.5.1
UART Mode Interrupt Management
24.3.4.5.1.1
UART Interrupts
24.3.4.5.1.2
Wake-Up Interrupt
24.3.4.5.2
IrDA Mode Interrupt Management
24.3.4.5.2.1
IrDA Interrupts
24.3.4.5.2.2
Wake-Up Interrupts
24.3.4.5.3
CIR Mode Interrupt Management
24.3.4.5.3.1
CIR Interrupts
24.3.4.5.3.2
Wake-Up Interrupts
24.3.4.6
FIFO Management
24.3.4.6.1
FIFO Trigger
24.3.4.6.1.1
Transmit FIFO Trigger
24.3.4.6.1.2
Receive FIFO Trigger
24.3.4.6.2
FIFO Interrupt Mode
24.3.4.6.3
FIFO Polled Mode Operation
24.3.4.6.4
FIFO DMA Mode Operation
24.3.4.6.4.1
DMA sequence to disable TX DMA
24.3.4.6.4.2
DMA Transfers (DMA Mode 1, 2, or 3)
24.3.4.6.4.3
DMA Transmission
24.3.4.6.4.4
DMA Reception
24.3.4.7
Mode Selection
24.3.4.7.1
Register Access Modes
24.3.4.7.1.1
Operational Mode and Configuration Modes
24.3.4.7.1.2
Register Access Submode
24.3.4.7.1.3
Registers Available for the Register Access Modes
24.3.4.7.2
UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection
24.3.4.7.2.1
Registers Available for the UART Function
24.3.4.7.2.2
Registers Available for the IrDA Function (UART3 Only)
24.3.4.7.2.3
Registers Available for the CIR Function (UART3 Only)
24.3.4.8
Protocol Formatting
24.3.4.8.1
UART Mode
24.3.4.8.1.1
UART Clock Generation: Baud Rate Generation
24.3.4.8.1.2
Choosing the Appropriate Divisor Value
24.3.4.8.1.3
UART Data Formatting
24.3.4.8.1.3.1
Frame Formatting
24.3.4.8.1.3.2
Hardware Flow Control
24.3.4.8.1.3.3
Software Flow Control
24.3.4.8.1.3.3.1
Receive (RX)
24.3.4.8.1.3.3.2
Transmit (TX)
24.3.4.8.1.3.4
Autobauding Modes
24.3.4.8.1.3.5
Error Detection
24.3.4.8.1.3.6
Overrun During Receive
24.3.4.8.1.3.7
Time-Out and Break Conditions
24.3.4.8.1.3.7.1
Time-Out Counter
24.3.4.8.1.3.7.2
Break Condition
24.3.4.8.2
IrDA Mode (UART3 Only)
24.3.4.8.2.1
IrDA Clock Generation: Baud Generator
24.3.4.8.2.2
Choosing the Appropriate Divisor Value
24.3.4.8.2.3
IrDA Data Formatting
24.3.4.8.2.3.1
IR RX Polarity Control
24.3.4.8.2.3.2
IrDA Reception Control
24.3.4.8.2.3.3
IR Address Checking
24.3.4.8.2.3.4
Frame Closing
24.3.4.8.2.3.5
Store and Controlled Transmission
24.3.4.8.2.3.6
Error Detection
24.3.4.8.2.3.7
Underrun During Transmission
24.3.4.8.2.3.8
Overrun During Receive
24.3.4.8.2.3.9
Status FIFO
24.3.4.8.2.4
SIR Mode Data Formatting
24.3.4.8.2.4.1
Abort Sequence
24.3.4.8.2.4.2
Pulse Shaping
24.3.4.8.2.4.3
SIR Free Format Programming
24.3.4.8.2.5
MIR and FIR Mode Data Formatting
24.3.4.8.3
CIR Mode (UART3 Only)
24.3.4.8.3.1
CIR Mode Clock Generation
24.3.4.8.3.2
CIR Data Formatting
24.3.4.8.3.2.1
IR RX Polarity Control
24.3.4.8.3.2.2
CIR Transmission
24.3.5
UART/IrDA/CIR Basic Programming Model
24.3.5.1
Global Initialization
24.3.5.1.1
Surrounding Modules Global Initialization
24.3.5.1.2
UART/IrDA/CIR Module Global Initialization
24.3.5.2
Mode selection
24.3.5.3
Submode selection
24.3.5.4
Load FIFO trigger and DMA mode settings
24.3.5.4.1
DMA mode Settings
24.3.5.4.2
FIFO Trigger Settings
24.3.5.5
Protocol, Baud rate and interrupt settings
24.3.5.5.1
Baud rate settings
24.3.5.5.2
Interrupt settings
24.3.5.5.3
Protocol settings
24.3.5.5.4
UART/IrDA(SIR/MIR/FIR)/CIR
24.3.5.6
Hardware and Software Flow Control Configuration
24.3.5.6.1
Hardware Flow Control Configuration
24.3.5.6.2
Software Flow Control Configuration
24.3.5.7
IrDA Programming Model (UART3 Only)
24.3.5.7.1
SIR mode
24.3.5.7.1.1
Receive
24.3.5.7.1.2
Transmit
24.3.5.7.2
MIR mode
24.3.5.7.2.1
Receive
24.3.5.7.2.2
Transmit
24.3.5.7.3
FIR mode
24.3.5.7.3.1
Receive
24.3.5.7.3.2
Transmit
24.3.6
UART/IrDA/CIR Register Manual
24.3.6.1
UART/IrDA/CIR Instance Summary
24.3.6.2
UART/IrDA/CIR Registers
24.3.6.2.1
UART/IrDA/CIR Register Summary
24.3.6.2.2
UART/IrDA/CIR Register Description
24.4
Multichannel Serial Peripheral Interface
24.4.1
McSPI Overview
24.4.2
McSPI Environment
24.4.2.1
Basic McSPI Pins for Master Mode
24.4.2.2
Basic McSPI Pins for Slave Mode
24.4.2.3
Multichannel SPI Protocol and Data Format
24.4.2.3.1
Transfer Format
24.4.2.4
SPI in Master Mode
24.4.2.5
SPI in Slave Mode
24.4.3
McSPI Integration
24.4.4
McSPI Functional Description
24.4.4.1
McSPI Block Diagram
24.4.4.2
Reset
24.4.4.3
Master Mode
24.4.4.3.1
Master Mode Features
24.4.4.3.2
Master Transmit-and-Receive Mode (Full Duplex)
24.4.4.3.3
Master Transmit-Only Mode (Half Duplex)
24.4.4.3.4
Master Receive-Only Mode (Half Duplex)
24.4.4.3.5
Single-Channel Master Mode
24.4.4.3.5.1
Programming Tips When Switching to Another Channel
24.4.4.3.5.2
Force SPIEN[x] Mode
24.4.4.3.5.3
Turbo Mode
24.4.4.3.6
Start-Bit Mode
24.4.4.3.7
Chip-Select Timing Control
24.4.4.3.8
Programmable SPI Clock
24.4.4.3.8.1
Clock Ratio Granularity
24.4.4.4
Slave Mode
24.4.4.4.1
Dedicated Resources
24.4.4.4.2
Slave Transmit-and-Receive Mode
24.4.4.4.3
Slave Transmit-Only Mode
24.4.4.4.4
Slave Receive-Only Mode
24.4.4.5
3-Pin or 4-Pin Mode
24.4.4.6
FIFO Buffer Management
24.4.4.6.1
Buffer Almost Full
24.4.4.6.2
Buffer Almost Empty
24.4.4.6.3
End of Transfer Management
24.4.4.7
Interrupts
24.4.4.7.1
Interrupt Events in Master Mode
24.4.4.7.1.1
TXx_EMPTY
24.4.4.7.1.2
TXx_UNDERFLOW
24.4.4.7.1.3
RXx_ FULL
24.4.4.7.1.4
End Of Word Count
24.4.4.7.2
Interrupt Events in Slave Mode
24.4.4.7.2.1
TXx_EMPTY
24.4.4.7.2.2
TXx_UNDERFLOW
24.4.4.7.2.3
RXx_FULL
24.4.4.7.2.4
RX0_OVERFLOW
24.4.4.7.2.5
End Of Word Count
24.4.4.7.3
Interrupt-Driven Operation
24.4.4.7.4
Polling
24.4.4.8
DMA Requests
24.4.4.9
Power Saving Management
24.4.4.9.1
Normal Mode
24.4.4.9.2
Idle Mode
24.4.4.9.2.1
Wake-Up Event in Smart-Idle Mode
24.4.4.9.2.2
Transitions From Smart-Idle Mode to Normal Mode
24.4.4.9.2.3
Force-Idle Mode
24.4.5
McSPI Programming Guide
24.4.5.1
Global Initialization
24.4.5.1.1
Surrounding Modules Global Initialization
24.4.5.1.2
McSPI Global Initialization
24.4.5.1.2.1
Main Sequence – McSPI Global Initialization
24.4.5.2
Operational Mode Configuration
24.4.5.2.1
McSPI Operational Modes
24.4.5.2.1.1
Common Transfer Sequence
24.4.5.2.1.2
End of Transfer Sequences
24.4.5.2.1.3
Transmit-and-Receive (Master and Slave)
24.4.5.2.1.4
Transmit-Only (Master and Slave)
24.4.5.2.1.4.1
Based on Interrupt Requests
24.4.5.2.1.4.2
Based on DMA Write Requests
24.4.5.2.1.5
Master Normal Receive-Only
24.4.5.2.1.5.1
Based on Interrupt Requests
24.4.5.2.1.5.2
Based on DMA Read Requests
24.4.5.2.1.6
Master Turbo Receive-Only
24.4.5.2.1.6.1
Based on Interrupt Requests
24.4.5.2.1.6.2
Based on DMA Read Requests
24.4.5.2.1.7
Slave Receive-Only
24.4.5.2.1.8
Transfer Procedures With FIFO
24.4.5.2.1.8.1
Common Transfer Sequence in FIFO Mode
24.4.5.2.1.8.2
End of Transfer Sequences in FIFO Mode
24.4.5.2.1.8.3
Transmit-and-Receive With Word Count
24.4.5.2.1.8.4
Transmit-and-Receive Without Word Count
24.4.5.2.1.8.5
Transmit-Only
24.4.5.2.1.8.6
Receive-Only With Word Count
24.4.5.2.1.8.7
Receive-Only Without Word Count
24.4.5.3
Common Transfer Procedures Without FIFO – Polling Method
24.4.5.3.1
Receive-Only Procedure – Polling Method
24.4.5.3.2
Receive-Only Procedure – Interrupt Method
24.4.5.3.3
Transmit-Only Procedure – Polling Method
24.4.5.3.4
Transmit-and-Receive Procedure – Polling Method
24.4.6
McSPI Register Manual
24.4.6.1
McSPI Instance Summary
24.4.6.2
McSPI Registers
24.4.6.2.1
McSPI Register Summary
24.4.6.2.2
McSPI Register Description
24.5
Quad Serial Peripheral Interface
24.5.1
Quad Serial Peripheral Interface Overview
24.5.2
QSPI Environment
24.5.3
QSPI Integration
24.5.4
QSPI Functional Description
24.5.4.1
QSPI Block Diagram
24.5.4.1.1
SFI Register Control
24.5.4.1.2
SFI Translator
24.5.4.1.3
SPI Control Interface
24.5.4.1.4
SPI Clock Generator
24.5.4.1.5
SPI Control State-Machine
24.5.4.1.6
SPI Data Shifter
24.5.4.2
QSPI Clock Configuration
24.5.4.3
QSPI Interrupt Requests
24.5.4.4
QSPI Memory Regions
24.5.5
QSPI Register Manual
24.5.5.1
QSPI Instance Summary
24.5.5.2
QSPI registers
24.5.5.2.1
QSPI Register Summary
24.5.5.2.2
QSPI Register Description
24.6
Multichannel Audio Serial Port
24.6.1
McASP Overview
24.6.2
McASP Environment
24.6.2.1
McASP Signals
24.6.2.2
Protocols and Data Formats
24.6.2.2.1
Protocols Supported
24.6.2.2.2
Definition of Terms
24.6.2.2.3
TDM Format
24.6.2.2.4
I2S Format
24.6.2.2.5
S/PDIF Coding Format
24.6.2.2.5.1
Biphase-Mark Code
24.6.2.2.5.2
S/PDIF Subframe Format
24.6.2.2.5.3
Frame Format
24.6.3
McASP Integration
24.6.4
McASP Functional Description
24.6.4.1
McASP Block Diagram
24.6.4.2
McASP Clock and Frame-Sync Configurations
24.6.4.2.1
McASP Transmit Clock
24.6.4.2.2
McASP Receive Clock
24.6.4.2.3
Frame-Sync Generator
24.6.4.2.4
Synchronous and Asynchronous Transmit and Receive Operations
24.6.4.3
Serializers
24.6.4.4
Format Units
24.6.4.4.1
Transmit Format Unit
24.6.4.4.1.1
TDM Mode Transmission Data Alignment Settings
24.6.4.4.1.2
DIT Mode Transmission Data Alignment Settings
24.6.4.4.2
Receive Format Unit
24.6.4.4.2.1
TDM Mode Reception Data Alignment Settings
24.6.4.5
State-Machines
24.6.4.6
TDM Sequencers
24.6.4.7
McASP Software Reset
24.6.4.8
McASP Power Management
24.6.4.9
Transfer Modes
24.6.4.9.1
Burst Transfer Mode
24.6.4.9.2
Time-Division Multiplexed (TDM) Transfer Mode
24.6.4.9.2.1
TDM Time Slots Generation and Processing
24.6.4.9.2.2
Special 384-Slot TDM Mode for Connection to External DIR
24.6.4.9.3
DIT Transfer Mode
24.6.4.9.3.1
Transmit DIT Encoding
24.6.4.9.3.2
Transmit DIT Clock and Frame-Sync Generation
24.6.4.9.3.3
DIT Channel Status and User Data Register Files
24.6.4.10
Data Transmission and Reception
24.6.4.10.1
Data Ready Status and Event/Interrupt Generation
24.6.4.10.1.1
Transmit Data Ready
24.6.4.10.1.2
Receive Data Ready
24.6.4.10.1.3
Transfers Through the Data Port (DATA)
24.6.4.10.1.4
Transfers Through the Configuration Bus (CFG)
24.6.4.10.1.5
Using a Device CPU for McASP Servicing
24.6.4.10.1.6
Using the DMA for McASP Servicing
24.6.4.11
McASP Audio FIFO (AFIFO)
24.6.4.11.1
AFIFO Data Transmission
24.6.4.11.1.1
Transmit DMA Event Pacer
24.6.4.11.2
AFIFO Data Reception
24.6.4.11.2.1
Receive DMA Event Pacer
24.6.4.11.3
Arbitration Between Transmit and Receive DMA Requests
24.6.4.12
McASP Events and Interrupt Requests
24.6.4.12.1
Transmit Data Ready Event and Interrupt
24.6.4.12.2
Receive Data Ready Event and Interrupt
24.6.4.12.3
Error Interrupt
24.6.4.12.4
Multiple Interrupts
24.6.4.13
DMA Requests
24.6.4.14
Loopback Modes
24.6.4.14.1
Loopback Mode Configurations
24.6.4.15
Error Reporting
24.6.4.15.1
Buffer Underrun Error -Transmitter
24.6.4.15.2
Buffer Overrun Error-Receiver
24.6.4.15.3
DATA Port Error - Transmitter
24.6.4.15.4
DATA Port Error - Receiver
24.6.4.15.5
Unexpected Frame Sync Error
24.6.4.15.6
Clock Failure Detection
24.6.4.15.6.1
Clock Failure Check Startup
24.6.4.15.6.2
Transmit Clock Failure Check and Recovery
24.6.4.15.6.3
Receive Clock Failure Check and Recovery
24.6.5
McASP Low-Level Programming Model
24.6.5.1
Global Initialization
24.6.5.1.1
Surrounding Modules Global Initialization
24.6.5.1.2
McASP Global Initialization
24.6.5.1.2.1
Main Sequence – McASP Global Initialization for DIT-Transmission
24.6.5.1.2.1.1
Subsequence – Transmit Format Unit Configuration for DIT-Transmission
24.6.5.1.2.1.2
Subsequence – Transmit Frame Synchronization Generator Configuration for DIT-Transmission
24.6.5.1.2.1.3
Subsequence – Transmit Clock Generator Configuration for DIT-Transmission
24.6.5.1.2.1.4
Subsequence - McASP Pins Functional Configuration
24.6.5.1.2.1.5
Subsequence – DIT-specific Subframe Fields Configuration
24.6.5.1.2.2
Main Sequence – McASP Global Initialization for TDM-Reception
24.6.5.1.2.2.1
Subsequence – Receive Format Unit Configuration in TDM Mode
24.6.5.1.2.2.2
Subsequence – Receive Frame Synchronization Generator Configuration in TDM Mode
24.6.5.1.2.2.3
Subsequence – Receive Clock Generator Configuration
24.6.5.1.2.2.4
Subsequence—McASP Receiver Pins Functional Configuration
24.6.5.1.2.3
Main Sequence – McASP Global Initialization for TDM -Transmission
24.6.5.1.2.3.1
Subsequence – Transmit Format Unit Configuration in TDM Mode
24.6.5.1.2.3.2
Subsequence – Transmit Frame Synchronization Generator Configuration in TDM Mode
24.6.5.1.2.3.3
Subsequence – Transmit Clock Generator Configuration for TDM Cases
24.6.5.1.2.3.4
Subsequence—McASP Transmit Pins Functional Configuration
24.6.5.2
Operational Modes Configuration
24.6.5.2.1
McASP Transmission Modes
24.6.5.2.1.1
Main Sequence – McASP DIT- /TDM- Polling Transmission Method
24.6.5.2.1.2
Main Sequence – McASP DIT- /TDM - Interrupt Transmission Method
24.6.5.2.1.3
Main Sequence –McASP DIT- /TDM - Mode DMA Transmission Method
24.6.5.2.2
McASP Reception Modes
24.6.5.2.2.1
Main Sequence – McASP Polling Reception Method
24.6.5.2.2.2
Main Sequence – McASP TDM - Interrupt Reception Method
24.6.5.2.2.3
Main Sequence – McASP TDM - Mode DMA Reception Method
24.6.5.2.3
McASP Event Servicing
24.6.5.2.3.1
McASP DIT-/TDM- Transmit Interrupt Events Servicing
24.6.5.2.3.2
McASP TDM- Receive Interrupt Events Servicing
24.6.5.2.3.3
3137
24.6.5.2.3.4
Subsequence – McASP DIT-/TDM -Modes Transmit Error Handling
24.6.5.2.3.5
Subsequence – McASP Receive Error Handling
24.6.6
McASP Register Manual
24.6.6.1
McASP Instance Summary
24.6.6.2
McASP Registers
24.6.6.2.1
MCASP_CFG Register Summary
24.6.6.2.2
MCASP_CFG Register Description
24.6.6.2.3
MCASP_AFIFO Register Summary
24.6.6.2.4
MCASP_AFIFO Register Description
24.6.6.2.5
MCASP_DAT Register Summary
24.6.6.2.6
MCASP_DAT Register Description
24.7
SuperSpeed USB DRD
24.7.1
SuperSpeed USB DRD Subsystem Overview
24.7.1.1
Main Features
24.7.1.2
Unsupported Features
24.7.2
SuperSpeed USB DRD Subsystem Environment
24.7.2.1
SuperSpeed USB DRD Subsystem I/O Interfaces
24.7.2.2
SuperSpeed USB Subsystem Application
24.7.3
SuperSpeed USB Subsystem Integration
24.8
SATA Controller
24.8.1
SATA Controller Overview
24.8.1.1
SATA Controller
24.8.1.1.1
AHCI Mode Overview
24.8.1.1.2
Native Command Queuing
24.8.1.1.3
SATA Transport Layer Functionalities
24.8.1.1.4
SATA Link Layer Functionalities
24.8.1.2
SATA Controller Features
24.8.2
SATA Controller Environment
24.8.3
SATA Controller Integration
24.8.4
SATA Controller Functional Description
24.8.4.1
SATA Controller Block Diagram
24.8.4.2
SATA Controller Link Layer Protocol and Data Format
24.8.4.2.1
SATA 8b/10b Parallel Encoding/Decoding
24.8.4.2.2
SATA Stream Dword Components
24.8.4.2.3
Scrambling/Descrambling Processing
24.8.4.3
Resets
24.8.4.3.1
Hardware Reset
24.8.4.3.2
Software Initiated Resets
24.8.4.3.2.1
Software Reset
24.8.4.3.2.2
Port Reset
24.8.4.3.2.3
HBA Reset
24.8.4.4
Power Management
24.8.4.4.1
SATA Specific Power Management
24.8.4.4.1.1
PARTIAL Power Mode
24.8.4.4.1.2
Slumber Power Mode
24.8.4.4.1.3
Software Control over Low Power States
24.8.4.4.1.4
Aggressive Power Management
24.8.4.4.2
Master Standby and Slave Idle Management Protocols
24.8.4.4.3
Clock Gating Synchronization
24.8.4.4.4
3187
24.8.4.5
Interrupt Requests
24.8.4.5.1
Interrupt Generation
24.8.4.5.2
Levels of Interrupt Control
24.8.4.5.3
Interrupt Events Description
24.8.4.5.3.1
Task File Error Status
24.8.4.5.3.2
Host Bus Fatal Error
24.8.4.5.3.3
Interface Fatal Error Status
24.8.4.5.3.4
Interface Non-Fatal Error Status
24.8.4.5.3.5
Overflow Status
24.8.4.5.3.6
Incorrect Port Multiplier Status
24.8.4.5.3.7
PHYReady Change Status
24.8.4.5.3.8
Port Connect Change Status
24.8.4.5.3.9
Descriptor Processed
24.8.4.5.3.10
Unknown FIS Interrupt
24.8.4.5.3.11
Set Device Bits Interrupt
24.8.4.5.3.12
DMA Setup FIS Interrupt
24.8.4.5.3.13
PIO Setup FIS Interrupt
24.8.4.5.3.14
Device to Host Register FIS Interrupt
24.8.4.5.4
Interrupt Condition Control
24.8.4.5.5
Command Completion Coalescing Interrupts
24.8.4.5.5.1
CCC Interrupt Based on Expired Timeout Value
24.8.4.5.5.2
CCC Interrupt Based on Completion Count
24.8.4.6
System Memory FIS Descriptors
24.8.4.6.1
Command List Structure Basics
24.8.4.6.2
Supported Types of Commands
24.8.4.6.3
Received FIS Structures
24.8.4.6.4
FIS Descriptors Summary
24.8.4.7
Transport Layer FIS-Based Interactions
24.8.4.7.1
Software Processing of the Port Command List
24.8.4.7.2
Handling the Received FIS Descriptors
24.8.4.8
DMA Port Configuration
24.8.4.9
Port Multiplier Operation
24.8.4.9.1
Command-Based Switching Mode
24.8.4.9.1.1
Port Multiplier NCQ and Non-NCQ Commands Generation
24.8.4.9.2
Port Multiplier Enumeration
24.8.4.10
Activity LED Generation Functionality
24.8.4.11
Supported Types of SATA Transfers
24.8.4.11.1
Supported Higher Level Protocols
24.8.4.12
SATA Controller AHCI Hardware Register Interface
24.8.5
SATA Controller Low Level Programming Model
24.8.5.1
Global Initialization
24.8.5.1.1
Surrounding Modules Global Initialization
24.8.5.1.2
SATA Controller Global Initialization
24.8.5.1.2.1
Main Sequence SATA Controller Global Initialization
24.8.5.1.2.2
SubSequence – Firmware Capability Writes
24.8.5.1.3
Issue Command - Main Sequence
24.8.5.1.4
Receive FIS—Main Sequence
24.8.6
SATA Controller Register Manual
24.8.6.1
SATA Controller Instance Summary
24.8.6.2
DWC_ahsata Registers
24.8.6.2.1
DWC_ahsata Register Summary
24.8.6.2.2
DWC_ahsata Register Description
24.8.6.3
SATAMAC_wrapper Registers
24.8.6.3.1
SATAMAC_wrapper Register Summary
24.8.6.3.2
SATAMAC_wrapper Register Description
24.9
PCIe Controller
24.9.1
PCIe Controller Subsystem Overview
24.9.1.1
PCIe Controllers Key Features
24.9.2
PCIe Controller Environment
24.9.3
PCIe Controllers Integration
24.9.4
PCIe SS Controller Functional Description
24.9.4.1
PCIe Controller Functional Block Diagram
24.9.4.2
PCIe Traffics
24.9.4.3
PCIe Controller Ports on L3_MAIN Interconnect
24.9.4.3.1
PCIe Controller Master Port
24.9.4.3.1.1
PCIe Controller Master Port to MMU Routing
24.9.4.3.2
PCIe Controller Slave Port
24.9.4.3.3
3255
24.9.4.4
PCIe Controller Reset Management
24.9.4.4.1
PCIe Reset Types and Stickiness
24.9.4.4.2
PCIe Reset Conditions
24.9.4.4.2.1
PCIe Main Reset
24.9.4.4.2.1.1
PCIe Subsystem Cold Main Reset Source
24.9.4.4.2.1.2
PCIe Subsystem Warm Main Reset Sources
24.9.4.4.2.2
PCIe Standard Specific Resets to the PCIe Core Logic
24.9.4.5
PCIe Controller Power Management
24.9.4.5.1
PCIe Protocol Power Management
24.9.4.5.1.1
PCIe Device/function power state (D-state)
24.9.4.5.1.2
PCIe Controller PIPE Powerstate (Powerdown Control)
24.9.4.5.2
PCIE Controller Clocks Management
24.9.4.5.2.1
PCIe Clock Domains
24.9.4.5.2.2
PCIe Controller Idle/Standby Clock Management Interfaces
24.9.4.5.2.2.1
PCIe Controller Master Standby Behavior
24.9.4.5.2.2.2
PCIe Controller Slave Idle/Disconnect Behavior
24.9.4.5.2.2.2.1
PCIe Controller Idle Sequence During D3cold/L3 State
24.9.4.6
PCIe Controller Interrupt Requests
24.9.4.6.1
PCIe Controller Main Hardware Management
24.9.4.6.1.1
PCIe Management Interrupt Events
24.9.4.6.1.2
PCIe Error Interrupt Events
24.9.4.6.1.3
Summary of PCIe Controller Main Hardware Interrupt Events
24.9.4.6.2
PCIe Controller Legacy and MSI Virtual Interrupts Management
24.9.4.6.2.1
Legacy PCI Interrupts (INTx)
24.9.4.6.2.1.1
Legacy PCI Interrupt Events Overview
24.9.4.6.2.1.2
Legacy PCI Interrupt Transmission (EP mode only)
24.9.4.6.2.1.3
Legacy PCI Interrupt Reception (RC mode only)
24.9.4.6.2.2
PCIe Controller Message Signaled Interrupts (MSI)
24.9.4.6.2.2.1
PCIe Specific MSI Interrupt Event Overview
24.9.4.6.2.2.2
PCIe Controller MSI Transmission Methods (EP mode)
24.9.4.6.2.2.2.1
PCIe Controller MSI transmission, hardware method
24.9.4.6.2.2.2.2
PCIe Controller MSI transmission, software method
24.9.4.6.2.2.3
PCIe Controller MSI Reception (RC mode)
24.9.4.6.3
PCIe Controller MSI Hardware Interrupt Events
24.9.4.7
PCIe Controller Address Spaces and Address Translation
24.9.4.8
PCIe Traffic Requesting and Responding
24.9.4.8.1
PCIe Memory-type (Mem) Traffic Management
24.9.4.8.1.1
PCIe Memory Requesting
24.9.4.8.1.2
PCIe Memory Responding
24.9.4.8.2
PCIe Configuration Type (Cfg) Traffic Management
24.9.4.8.2.1
RC Self-configuration (RC Only)
24.9.4.8.2.2
Configuration Requests over PCIe (RC Only)
24.9.4.8.2.3
Configuration Responding over PCIe (EP Only)
24.9.4.8.3
PCIe I/O-type (IO) traffic management
24.9.4.8.3.1
PCIe I/O requesting (RC only)
24.9.4.8.3.2
PCIe IO BAR initialization before enumeration (EP only)
24.9.4.8.3.3
PCIe I/O responding (PCI legacy EP only)
24.9.4.8.4
PCIe Message-type (Msg) traffic management
24.9.4.9
PCIe Programming Register Interface
24.9.4.9.1
PCIe Register Access
24.9.4.9.2
Double Mapping of the PCIe Local Control Registers
24.9.4.9.3
Base Address Registers (BAR) Initialization
24.9.5
PCIe Controller Low Level Programming Model
24.9.5.1
Surrounding Modules Global Initialization
24.9.5.2
Main Sequence of PCIe Controllers Initalization
24.9.6
PCIe Standard Registers vs PCIe Subsystem Hardware Registers Mapping
24.9.7
PCIe Controller Register Manual
24.9.7.1
PCIe Controller Instance Summary
24.9.7.2
PCIe_SS_EP_CFG_PCIe Registers
24.9.7.2.1
PCIe_SS_EP_CFG_PCIe Register Summary
24.9.7.2.2
PCIe_SS_EP_CFG_PCIe Register Description
24.9.7.2.3
3317
24.9.7.3
PCIe_SS_EP_CFG_DBICS Registers
24.9.7.3.1
PCIe_SS_EP_CFG_DBICS Register Summary
24.9.7.3.2
PCIe_SS_EP_CFG_DBICS Register Description
24.9.7.4
PCIe_SS_RC_CFG_DBICS Registers
24.9.7.4.1
PCIe_SS_RC_CFG_DBICS Register Summary
24.9.7.4.2
PCIe_SS_RC_CFG_DBICS Register Description
24.9.7.5
PCIe_SS_PL_CONF Registers
24.9.7.5.1
PCIe_SS_PL_CONF Register Summary
24.9.7.5.2
PCIe_SS_PL_CONF Register Description
24.9.7.6
PCIe_SS_EP_CFG_DBICS2 Registers
24.9.7.6.1
PCIe_SS_EP_CFG_DBICS2 Register Summary
24.9.7.6.2
PCIe_SS_EP_CFG_DBICS2 Register Description
24.9.7.7
PCIe_SS_RC_CFG_DBICS2 Registers
24.9.7.7.1
PCIe_SS_RC_CFG_DBICS2 Register Summary
24.9.7.7.2
PCIe_SS_RC_CFG_DBICS2 Register Description
24.9.7.8
PCIe_SS_TI_CONF Registers
24.9.7.8.1
PCIe_SS_TI_CONF Register Summary
24.9.7.8.2
PCIe_SS_TI_CONF Register Description
24.10
DCAN
24.10.1
DCAN Overview
24.10.1.1
Features
24.10.2
DCAN Environment
24.10.2.1
CAN Network Basics
24.10.3
DCAN Integration
24.10.4
DCAN Functional Description
24.10.4.1
Module Clocking Requirements
24.10.4.2
Interrupt Functionality
24.10.4.2.1
Message Object Interrupts
24.10.4.2.2
Status Change Interrupts
24.10.4.2.3
Error Interrupts
24.10.4.3
DMA Functionality
24.10.4.4
Local Power-Down Mode
24.10.4.4.1
Entering Local Power-Down Mode
24.10.4.4.2
Wakeup From Local Power Down
24.10.4.5
Parity Check Mechanism
24.10.4.5.1
Behavior on Parity Error
24.10.4.5.2
Parity Testing
24.10.4.6
Debug/Suspend Mode
24.10.4.7
Configuration of Message Objects Description
24.10.4.7.1
Configuration of a Transmit Object for Data Frames
24.10.4.7.2
Configuration of a Transmit Object for Remote Frames
24.10.4.7.3
Configuration of a Single Receive Object for Data Frames
24.10.4.7.4
Configuration of a Single Receive Object for Remote Frames
24.10.4.7.5
Configuration of a FIFO Buffer
24.10.4.8
Message Handling
24.10.4.8.1
Message Handler Overview
24.10.4.8.2
Receive/Transmit Priority
24.10.4.8.3
Transmission of Messages in Event Driven CAN Communication
24.10.4.8.4
Updating a Transmit Object
24.10.4.8.5
Changing a Transmit Object
24.10.4.8.6
Acceptance Filtering of Received Messages
24.10.4.8.7
Reception of Data Frames
24.10.4.8.8
Reception of Remote Frames
24.10.4.8.9
Reading Received Messages
24.10.4.8.10
Requesting New Data for a Receive Object
24.10.4.8.11
Storing Received Messages in FIFO Buffers
24.10.4.8.12
Reading From a FIFO Buffer
24.10.4.9
CAN Bit Timing
24.10.4.9.1
Bit Time and Bit Rate
24.10.4.9.1.1
Synchronization Segment
24.10.4.9.1.2
Propagation Time Segment
24.10.4.9.1.3
Phase Buffer Segments and Synchronization
24.10.4.9.1.4
Oscillator Tolerance Range
24.10.4.9.2
DCAN Bit Timing Registers
24.10.4.9.2.1
Calculation of the Bit Timing Parameters
24.10.4.9.2.2
Example for Bit Timing Calculation
24.10.4.10
Message Interface Register Sets
24.10.4.10.1
Message Interface Register Sets 1 and 2
24.10.4.10.2
IF3 Register Set
24.10.4.11
Message RAM
24.10.4.11.1
Structure of Message Objects
24.10.4.11.2
Addressing Message Objects in RAM
24.10.4.11.3
Message RAM Representation in Debug/Suspend Mode
24.10.4.11.4
Message RAM Representation in Direct Access Mode
24.10.4.12
CAN Operation
24.10.4.12.1
CAN Module Initialization
24.10.4.12.1.1
Configuration of CAN Bit Timing
24.10.4.12.1.2
Configuration of Message Objects
24.10.4.12.1.3
DCAN RAM Hardware Initialization
24.10.4.12.2
CAN Message Transfer (Normal Operation)
24.10.4.12.2.1
Automatic Retransmission
24.10.4.12.2.2
Auto-Bus-On
24.10.4.12.3
Test Modes
24.10.4.12.3.1
Silent Mode
24.10.4.12.3.2
Loopback Mode
24.10.4.12.3.3
External Loopback Mode
24.10.4.12.3.4
Loopback Mode Combined With Silent Mode
24.10.4.12.3.5
Software Control of CAN_TX Pin
24.10.4.13
GPIO Support
24.10.5
DCAN Register Manual
24.10.5.1
DCAN Instance Summary
24.10.5.2
DCAN Registers
24.10.5.2.1
DCAN Register Summary
24.10.5.2.2
DCAN Register Description
24.11
Gigabit Ethernet Switch (GMAC_SW)
24.11.1
GMAC_SW Overview
24.11.1.1
Features
24.11.1.2
3415
24.11.2
GMAC_SW Environment
24.11.2.1
G/MII Interface
24.11.2.2
RMII Interface
24.11.2.3
RGMII Interface
24.11.3
GMAC_SW Integration
24.11.4
GMAC_SW Functional Description
24.11.4.1
Functional Block Diagram
24.11.4.2
GMAC_SW Ports
24.11.4.2.1
Interface Mode Selection
24.11.4.3
Clocking
24.11.4.3.1
Subsystem Clocking
24.11.4.3.2
Interface Clocking
24.11.4.3.2.1
G/MII Interface Clocking
24.11.4.3.2.2
RGMII Interface Clocking
24.11.4.3.2.3
RMII Interface Clocking
24.11.4.3.2.4
MDIO Clocking
24.11.4.4
Software IDLE
24.11.4.5
Interrupt Functionality
24.11.4.5.1
Receive Packet Completion Pulse Interrupt (RX_PULSE)
24.11.4.5.2
Transmit Packet Completion Pulse Interrupt (TX_PULSE)
24.11.4.5.3
Receive Threshold Pulse Interrupt (RX_THRESH_PULSE)
24.11.4.5.4
Miscellaneous Pulse Interrupt (MISC_PULSE)
24.11.4.5.4.1
EVNT_PEND( CPTS_PEND) Interrupt
24.11.4.5.4.2
Statistics Interrupt
24.11.4.5.4.3
Host Error interrupt
24.11.4.5.4.4
MDIO Interrupts
24.11.4.5.5
Interrupt Pacing
24.11.4.6
Reset Isolation
24.11.4.6.1
Reset Isolation Functional Description
24.11.4.7
Software Reset
24.11.4.8
CPSW_3G
24.11.4.8.1
CPDMA RX and TX Interfaces
24.11.4.8.1.1
Functional Operation
24.11.4.8.1.2
Receive DMA Interface
24.11.4.8.1.2.1
Receive DMA Host Configuration
24.11.4.8.1.2.2
Receive Channel Teardown
24.11.4.8.1.3
Transmit DMA Interface
24.11.4.8.1.3.1
Transmit DMA Host Configuration
24.11.4.8.1.3.2
Transmit Channel Teardown
24.11.4.8.1.4
Transmit Rate Limiting
24.11.4.8.1.5
Command IDLE
24.11.4.8.2
Address Lookup Engine (ALE)
24.11.4.8.2.1
Address Table Entry
24.11.4.8.2.1.1
Free Table Entry
24.11.4.8.2.1.2
Multicast Address Table Entry
24.11.4.8.2.1.3
VLAN/Multicast Address Table Entry
24.11.4.8.2.1.4
Unicast Address Table Entry
24.11.4.8.2.1.5
OUI Unicast Address Table Entry
24.11.4.8.2.1.6
VLAN/Unicast Address Table Entry
24.11.4.8.2.1.7
VLAN Table Entry
24.11.4.8.2.2
Packet Forwarding Processes
24.11.4.8.2.3
Learning Process
24.11.4.8.2.4
VLAN Aware Mode
24.11.4.8.2.5
VLAN Unaware Mode
24.11.4.8.3
Packet Priority Handling
24.11.4.8.4
FIFO Memory Control
24.11.4.8.5
FIFO Transmit Queue Control
24.11.4.8.5.1
Normal Priority Mode
24.11.4.8.5.2
Dual MAC Mode
24.11.4.8.5.3
Rate Limit Mode
24.11.4.8.6
Audio Video Bridging
24.11.4.8.6.1
IEEE 802.1AS: Timing and Synchronization for Time-Sensitive Applications in Bridged Local Area Networks (Precision Time Protocol (PTP))
24.11.4.8.6.1.1
IEEE 1722: "Layer 2 Transport Protocol for Time-Sensitive Streams"
24.11.4.8.6.1.2
IEEE 1733: Extends RTCP for RTP Streaming over AVB-supported Networks
24.11.4.8.6.2
IEEE 802.1Qav: "Virtual Bridged Local Area Networks: Forwarding and Queuing for Time-Sensitive Streams"
24.11.4.8.6.2.1
Configuring the Device for 802.1Qav Operation:
24.11.4.8.7
Ethernet MAC Sliver (CPGMAC_SL)
24.11.4.8.7.1
G/MII Media Independent Interface
24.11.4.8.7.1.1
Data Reception
24.11.4.8.7.1.1.1
Receive Control
24.11.4.8.7.1.1.2
Receive Inter-Frame Interval
24.11.4.8.7.1.2
Data Transmission
24.11.4.8.7.1.2.1
Transmit Control
24.11.4.8.7.1.2.2
CRC Insertion
24.11.4.8.7.1.2.3
MTXER
24.11.4.8.7.1.2.4
Adaptive Performance Optimization (APO)
24.11.4.8.7.1.2.5
Inter-Packet-Gap Enforcement
24.11.4.8.7.1.2.6
Back Off
24.11.4.8.7.1.2.7
Programmable Transmit Inter-Packet Gap
24.11.4.8.7.1.2.8
Speed, Duplex and Pause Frame Support Negotiation
24.11.4.8.7.2
RMII Interface
24.11.4.8.7.2.1
Features
24.11.4.8.7.2.2
RMII Receive (RX)
24.11.4.8.7.2.3
RMII Transmit (TX)
24.11.4.8.7.3
RGMII Interface
24.11.4.8.7.3.1
RGMII Features
24.11.4.8.7.3.2
RGMII Receive (RX)
24.11.4.8.7.3.3
In-Band Mode of Operation
24.11.4.8.7.3.4
Forced Mode of Operation
24.11.4.8.7.3.5
RGMII Transmit (TX)
24.11.4.8.7.4
Frame Classification
24.11.4.8.8
Embedded Memories
24.11.4.8.9
Flow Control
24.11.4.8.9.1
CPPI Port Flow Control
24.11.4.8.9.2
Ethernet Port Flow Control
24.11.4.8.9.2.1
Receive Flow Control
24.11.4.8.9.2.1.1
Collision Based Receive Buffer Flow Control
24.11.4.8.9.2.1.2
IEEE 802.3X Based Receive Flow Control
24.11.4.8.9.2.2
Transmit Flow Control
24.11.4.8.10
Short Gap
24.11.4.8.11
Switch Latency
24.11.4.8.12
Emulation Control
24.11.4.8.13
FIFO Loopback
24.11.4.8.14
Device Level Ring (DLR) Support
24.11.4.8.15
Energy Efficient Ethernet Support (802.3az)
24.11.4.8.16
CPSW_3G Network Statistics
24.11.4.8.16.1
3522
24.11.4.9
Static Packet Filter (SPF)
24.11.4.9.1
SPF Overview
24.11.4.9.2
SPF Functional Description
24.11.4.9.2.1
SPF Block Diagram
24.11.4.9.2.2
Interrupts
24.11.4.9.2.3
Protocol Header Extractor
24.11.4.9.2.4
Programmable Rule Engine
24.11.4.9.2.4.1
Internal Registers
24.11.4.9.2.4.2
Packet Buffer
24.11.4.9.2.5
Intrusion Event Logger
24.11.4.9.2.6
Rate Limiter
24.11.4.9.2.7
Rule Engine Instruction Set Architecture
24.11.4.9.2.7.1
Instruction Format
24.11.4.9.2.7.2
Operand Field
24.11.4.9.2.7.3
Arithmetic/Logical Function Field
24.11.4.9.2.7.4
Operation Field
24.11.4.9.3
Programming Guide
24.11.4.9.3.1
Initialization Routine
24.11.4.9.3.2
Interrupt Service Routine
24.11.4.9.3.3
Rule Engine Example Program
24.11.4.10
Common Platform Time Sync (CPTS)
24.11.4.10.1
CPTS Architecture
24.11.4.10.2
CPTS Initialization
24.11.4.10.3
Time Stamp Value
24.11.4.10.4
Event FIFO
24.11.4.10.5
Time Sync Events
24.11.4.10.5.1
Time Stamp Push Event
24.11.4.10.5.2
Time Stamp Counter Rollover Event
24.11.4.10.5.3
Time Stamp Counter Half-rollover Event
24.11.4.10.5.4
Hardware Time Stamp Push Event
24.11.4.10.5.5
Ethernet Port Events
24.11.4.10.6
CPTS Interrupt Handling
24.11.4.11
CPPI Buffer Descriptors
24.11.4.11.1
TX Buffer Descriptors
24.11.4.11.1.1
CPPI TX Data Word 0
24.11.4.11.1.2
CPPI TX Data Word 1
24.11.4.11.1.3
CPPI TX Data Word 2
24.11.4.11.1.4
CPPI TX Data Word 3
24.11.4.11.2
RX Buffer Descriptors
24.11.4.11.2.1
CPPI RX Data Word 0
24.11.4.11.2.2
CPPI RX Data Word 1
24.11.4.11.2.3
CPPI RX Data Word 2
24.11.4.11.2.4
CPPI RX Data Word 3
24.11.4.12
MDIO
24.11.4.12.1
MDIO Frame Formats
24.11.4.12.2
MDIO Functional Description
24.11.5
GMAC_SW Programming Guide
24.11.5.1
Transmit Operation
24.11.5.2
Receive Operation
24.11.5.3
MDIO Software Interface
24.11.5.3.1
Initializing the MDIO Module
24.11.5.3.2
Writing Data To a PHY Register
24.11.5.3.3
Reading Data From a PHY Register
24.11.5.4
Initialization and Configuration of CPSW
24.11.6
GMAC_SW Register Manual
24.11.6.1
GMAC_SW Instance Summary
24.11.6.2
SS Registers
24.11.6.2.1
SS Register Summary
24.11.6.2.2
SS Register Description
24.11.6.3
PORT Registers
24.11.6.3.1
PORT Register Summary
24.11.6.3.2
PORT Register Description
24.11.6.4
CPDMA registers
24.11.6.4.1
CPDMA Register Summary
24.11.6.4.2
CPDMA Register Description
24.11.6.5
STATS Registers
24.11.6.5.1
STATS Register Summary
24.11.6.5.2
STATS Register Description
24.11.6.6
STATERAM Registers
24.11.6.6.1
STATERAM Register Summary
24.11.6.6.2
STATERAM Register Description
24.11.6.7
CPTS registers
24.11.6.7.1
CPTS Register Summary
24.11.6.7.2
CPTS Register Description
24.11.6.8
ALE registers
24.11.6.8.1
ALE Register Summary
24.11.6.8.2
ALE Register Description
24.11.6.9
SL registers
24.11.6.9.1
SL Register Summary
24.11.6.9.2
SL Register Description
24.11.6.10
MDIO registers
24.11.6.10.1
MDIO Register Summary
24.11.6.10.2
MDIO Register Description
24.11.6.11
WR registers
24.11.6.11.1
WR Register Summary
24.11.6.11.2
WR Register Description
24.11.6.12
SPF Registers
24.11.6.12.1
SPF Register Summary
24.11.6.12.2
SPF Register Description
24.12
Media Local Bus (MLB)
25
eMMC/SD/SDIO
25.1
eMMC/SD/SDIO Overview
25.1.1
eMMC/SD/SDIO Features
25.2
eMMC/SD/SDIO Environment
25.2.1
eMMC/SD/SDIO Functional Modes
25.2.1.1
eMMC/SD/SDIO Connected to an eMMC, SD, or SDIO Card
25.2.2
Protocol and Data Format
25.2.2.1
Protocol
25.2.2.2
Data Format
25.3
eMMC/SD/SDIO Integration
25.4
eMMC/SD/SDIO Functional Description
25.4.1
Block Diagram
25.4.2
Resets
25.4.2.1
Hardware Reset
25.4.2.2
Software Reset
25.4.3
Power Management
25.4.4
Interrupt Requests
25.4.4.1
Interrupt-Driven Operation
25.4.4.2
Polling
25.4.4.3
Asynchronous Interrupt
25.4.5
DMA Modes
25.4.5.1
Master DMA Operations
25.4.5.1.1
Descriptor Table Description
25.4.5.1.2
Requirements for Descriptors
25.4.5.1.2.1
Data Length
25.4.5.1.2.2
Supported Features
25.4.5.1.2.3
Error Generation
25.4.5.1.3
Advanced DMA Description
25.4.5.2
Slave DMA Operations
25.4.5.2.1
DMA Receive Mode
25.4.5.2.2
DMA Transmit Mode
25.4.6
Mode Selection
25.4.7
Buffer Management
25.4.7.1
Data Buffer
25.4.7.1.1
Memory Size, Block Length, and Buffer-Management Relationship
25.4.7.1.2
Data Buffer Status
25.4.8
Transfer Process
25.4.8.1
Different Types of Commands
25.4.8.2
Different Types of Responses
25.4.9
Transfer or Command Status and Errors Reporting
25.4.9.1
Busy Time-Out for R1b, R5b Response Type
25.4.9.2
Busy Time-Out After Write CRC Status
25.4.9.3
Write CRC Status Time-Out
25.4.9.4
Read Data Time-Out
25.4.9.5
Boot Acknowledge Time-Out
25.4.10
Auto Command 12 Timings
25.4.10.1
Auto CMD12 Timings During Write Transfer
25.4.10.2
Auto CMD12 Timings During Read Transfer
25.4.11
Transfer Stop
25.4.12
Output Signals Generation
25.4.12.1
Generation on Falling Edge of MMC Clock
25.4.12.2
Generation on Rising Edge of MMC Clock
25.4.13
Sampling Clock Tuning
25.4.14
Card Boot Mode Management
25.4.14.1
Boot Mode Using CMD0
25.4.14.2
Boot Mode With CMD Line Tied to 0
25.4.15
MMC CE-ATA Command Completion Disable Management
25.4.16
Test Registers
25.4.17
eMMC/SD/SDIO Hardware Status Features
25.5
eMMC/SD/SDIO Programming Guide
25.5.1
Low-Level Programming Models
25.5.1.1
Global Initialization
25.5.1.1.1
Surrounding Modules Global Initialization
25.5.1.1.2
eMMC/SD/SDIO Host Controller Initialization Flow
25.5.1.1.2.1
Enable Interface and Functional Clock for MMC Controller
25.5.1.1.2.2
MMCHS Soft Reset Flow
25.5.1.1.2.3
Set MMCHS Default Capabilities
25.5.1.1.2.4
Wake-Up Configuration
25.5.1.1.2.5
MMC Host and Bus Configuration
25.5.1.2
Operational Modes Configuration
25.5.1.2.1
Basic Operations for eMMC/SD/SDIO Host Controller
25.5.1.2.1.1
Card Detection, Identification, and Selection
25.5.1.2.1.1.1
CMD Line Reset Procedure
25.5.1.2.1.2
Read/Write Transfer Flow in DMA Mode With Interrupt
25.5.1.2.1.2.1
DATA Lines Reset Procedure
25.5.1.2.1.3
Read/Write Transfer Flow in DMA Mode With Polling
25.5.1.2.1.4
Read/Write Transfer Flow Without DMA With Polling
25.5.1.2.1.5
Read/Write Transfer Flow in CE-ATA Mode
25.5.1.2.1.6
Suspend-Resume Flow
25.5.1.2.1.6.1
Suspend Flow
25.5.1.2.1.6.2
Resume Flow
25.5.1.2.1.7
Basic Operations – Steps Detailed
25.5.1.2.1.7.1
Command Transfer Flow
25.5.1.2.1.7.2
MMCHS Clock Frequency Change
25.5.1.2.1.7.3
Bus Width Selection
25.5.1.2.2
Bus Voltage Selection
25.5.1.2.3
Boot Mode Configuration
25.5.1.2.3.1
Boot Using CMD0
25.5.1.2.3.2
Boot With CMD Line Tied to 0
25.5.1.2.4
SDR104/HS200 DLL Tuning Procedure
25.6
eMMC/SD/SDIO Register Manual
25.6.1
eMMC/SD/SDIO Instance Summary
25.6.2
eMMC/SD/SDIO Registers
25.6.2.1
eMMC/SD/SDIO Register Summary
25.6.2.2
eMMC/SD/SDIO Register Description
26
Shared PHY Component Subsystem
26.1
SATA PHY Subsystem
26.1.1
SATA PHY Subsystem Overview
26.1.2
SATA PHY Subsystem Environment
26.1.2.1
SATA PHY I/O Signals
26.1.3
SATA PHY Subsystem Integration
26.1.4
SATA PHY Subsystem Functional Description
26.1.4.1
SATA PLL Controller L4 Interface Adapter Functional Description
26.1.4.2
SATA PHY Serializer and Deserializer Functional Descriptions
26.1.4.2.1
SATA PHY Reset
26.1.4.2.2
SATA_PHY Clocking
26.1.4.2.2.1
SATA_PHY Input Clocks
26.1.4.2.2.2
SATA_PHY Output Clocks
26.1.4.2.3
SATA_PHY Power Management
26.1.4.2.3.1
SATA_PHY Power-Up/-Down Sequences
26.1.4.2.3.2
SATA_PHY Low-Power Modes
26.1.4.2.4
SATA_PHY Hardware Requests
26.1.4.3
SATA Clock Generator Subsystem Functional Description
26.1.4.3.1
SATA DPLL Clock Generator Overview
26.1.4.3.2
SATA DPLL Clock Generator Reset
26.1.4.3.3
SATA DPLL Low-Power Modes
26.1.4.3.4
SATA DPLL Clocks Configuration
26.1.4.3.4.1
SATA DPLL Input Clock Control
26.1.4.3.4.2
SATA DPLL Output Clock Configuration
26.1.4.3.4.2.1
SATA DPLL Output Clock Gating
26.1.4.3.5
SATA DPLL Subsystem Architecture
26.1.4.3.6
SATA DPLL Clock Generator Modes and State Transitions
26.1.4.3.6.1
SATA Clock Generator Power Up
26.1.4.3.6.2
SATA DPLL Sequences
26.1.4.3.6.3
SATA DPLL Locked Mode
26.1.4.3.6.4
SATA DPLL Idle-Bypass Mode
26.1.4.3.6.5
SATA DPLL MN-Bypass Mode
26.1.4.3.6.6
SATA DPLL Error Conditions
26.1.4.3.7
SATA PLL Controller Functions
26.1.4.3.7.1
SATA PLL Controller Register Access
26.1.4.3.7.2
SATA DPLL Clock Programming Sequence
26.1.4.3.7.3
SATA DPLL Recommended Values
26.1.5
SATA PHY Subsystem Low-Level Programming Model
26.2
USB3_PHY Subsystem
26.2.1
USB3_PHY Subsystem Overview
26.2.2
USB3_PHY Subsystem Environment
26.2.2.1
USB3_PHY I/O Signals
26.2.3
USB3_PHY Subsystem Integration
26.2.4
USB3_PHY Subsystem Functional Description
26.2.4.1
Super-Speed USB PLL Controller L4 Interface Adapter Functional Description
26.2.4.2
USB3_PHY Serializer and Deserializer Functional Descriptions
26.2.4.2.1
USB3_PHY Module Resets
26.2.4.2.1.1
Hardware Reset
26.2.4.2.1.2
Software Reset
26.2.4.2.2
USB3_PHY Subsystem Clocking
26.2.4.2.2.1
USB3_PHY Subsystem Input Clocks
26.2.4.2.2.2
USB3_PHY Subsystem Output Clocks
26.2.4.2.3
USB3_PHY Power Management
26.2.4.2.3.1
USB3_PHY Power-Up/-Down Sequences
26.2.4.2.3.2
USB3_PHY Low-Power Modes
26.2.4.2.3.3
Clock Gating
26.2.4.2.4
USB3_PHY Hardware Requests
26.2.4.3
USB3_PHY Clock Generator Subsystem Functional Description
26.2.4.3.1
USB3_PHY DPLL Clock Generator Overview
26.2.4.3.2
USB3_PHY DPLL Clock Generator Reset
26.2.4.3.3
USB3_PHY DPLL Low-Power Modes
26.2.4.3.4
USB3_PHY DPLL Clocks Configuration
26.2.4.3.4.1
USB3_PHY DPLL Input Clock Control
26.2.4.3.4.2
USB3_PHY DPLL Output Clock Configuration
26.2.4.3.4.2.1
USB3_PHY DPLL Output Clock Gating
26.2.4.3.5
USB3_PHY DPLL Subsystem Architecture
26.2.4.3.6
USB3_PHY DPLL Clock Generator Modes and State Transitions
26.2.4.3.6.1
USB3_PHY Clock Generator Power Up
26.2.4.3.6.2
USB3_PHY DPLL Sequences
26.2.4.3.6.3
USB3_PHY DPLL Locked Mode
26.2.4.3.6.4
USB3_PHY DPLL Idle-Bypass Mode
26.2.4.3.6.5
USB3_PHY DPLL MN-Bypass Mode
26.2.4.3.6.6
USB3_PHY DPLL Error Conditions
26.2.4.3.7
USB3_PHY PLL Controller Functions
26.2.4.3.7.1
USB3_PHY PLL Controller Register Access
26.2.4.3.7.2
3783
26.2.4.3.7.3
USB3_PHY DPLL Clock Programming Sequence
26.2.4.3.7.4
USB3_PHY DPLL Recommended Values
26.2.5
USB3_PHY Subsystem Low-Level Programming Model
26.3
USB3 PHY and SATA PHY Register Manual
26.3.1
USB3 PHY and SATA PHY Instance Summary
26.3.2
USB3_PHY_RX Registers
26.3.2.1
USB3_PHY_RX Register Summary
26.3.2.2
USB3_PHY_RX Register Description
26.3.3
USB3_PHY_TX Registers
26.3.3.1
USB3_PHY_TX Register Summary
26.3.3.2
USB3_PHY_TX Register Description
26.3.4
SATA_PHY_RX Registers
26.3.4.1
SATA_PHY_RX Register Summary
26.3.4.2
SATA_PHY_RX Register Description
26.3.5
SATA_PHY_TX Registers
26.3.5.1
SATA_PHY_TX Register Summary
26.3.5.2
SATA_PHY_TX Register Description
26.3.6
DPLLCTRL Registers
26.3.6.1
DPLLCTRL Register Summary
26.3.6.2
DPLLCTRL Register Description
26.4
PCIe PHY Subsystem
26.4.1
PCIe PHY Subsystem Overview
26.4.1.1
PCIe PHY Subsystem Key Features
26.4.2
PCIe PHY Subsystem Environment
26.4.2.1
PCIe PHY I/O Signals
26.4.3
PCIe Shared PHY Subsystem Integration
26.4.4
PCIe PHY Subsystem Functional Description
26.4.4.1
PCIe PHY Subsystem Block Diagram
26.4.4.2
OCP2SCP Functional Description
26.4.4.2.1
OCP2SCP Reset
26.4.4.2.1.1
Hardware Reset
26.4.4.2.1.2
Software Reset
26.4.4.2.2
OCP2SCP Power Management
26.4.4.2.2.1
Idle Mode
26.4.4.2.2.2
Clock Gating
26.4.4.2.3
OCP2SCP Timing Registers
26.4.4.3
PCIe PHY Serializer and Deserializer Functional Descriptions
26.4.4.3.1
PCIe PHY Module Resets
26.4.4.3.1.1
Hardware Reset
26.4.4.3.1.2
Software Reset
26.4.4.3.2
PCIe PHY Subsystem Clocking
26.4.4.3.2.1
PCIe PHY Subsystem Input Clocks
26.4.4.3.2.2
PCIe PHY Subsystem Output Clocks
26.4.4.3.3
PCIe PHY Power Management
26.4.4.3.3.1
PCIe PHY Power-Up/-Down Sequences
26.4.4.3.3.2
PCIe PHY Low-Power Modes
26.4.4.3.3.3
Clock Gating
26.4.4.3.4
PCIe PHY Hardware Requests
26.4.4.4
PCIe PHY Clock Generator Subsystem Functional Description
26.4.4.4.1
PCIe PHY DPLL Clock Generator
26.4.4.4.1.1
PCIe PHY DPLL Clock Generator Overview
26.4.4.4.1.2
PCIe PHY DPLL Clock Generator Reset
26.4.4.4.1.3
PCIe PHY DPLL Low-Power Modes
26.4.4.4.1.4
PCIe PHY DPLL Clocks Configuration
26.4.4.4.1.4.1
PCIe PHY DPLL Input Clock Control
26.4.4.4.1.4.2
PCIe PHY DPLL Output Clock Configuration
26.4.4.4.1.4.2.1
PCIe PHY DPLL Output Clock Gating
26.4.4.4.1.5
PCIe PHY DPLL Subsystem Architecture
26.4.4.4.1.6
PCIe PHY DPLL Clock Generator Modes and State Transitions
26.4.4.4.1.6.1
PCIe PHY Clock Generator Power Up
26.4.4.4.1.6.2
PCIe PHY DPLL Sequences
26.4.4.4.1.6.3
PCIe PHY DPLL Locked Mode
26.4.4.4.1.6.4
PCIe PHY DPLL Idle-Bypass Mode
26.4.4.4.1.6.5
PCIe PHY DPLL Low Power Stop Mode
26.4.4.4.1.6.6
PCIe PHY DPLL Clock Programming Sequence
26.4.4.4.1.6.7
PCIe PHY DPLL Recommended Values
26.4.4.4.2
PCIe PHY APLL Clock Generator
26.4.4.4.2.1
PCIe PHY APLL Clock Generator Overview
26.4.4.4.2.2
PCIe PHY APLL Clock Generator Reset
26.4.4.4.2.3
PCIe PHY APLL Low-Power Mode
26.4.4.4.2.4
PCIe PHY APLL Clocks Configuration
26.4.4.4.2.4.1
PCIe PHY APLL Input Clock Control
26.4.4.4.2.4.2
PCIe PHY APLL Output Clock Configuration
26.4.4.4.2.4.2.1
PCIe PHY APLL Output Clock Gating
26.4.4.4.2.5
PCIe PHY APLL Subsystem Architecture
26.4.4.4.2.6
PCIe PHY APLL Clock Generator Modes and State Transitions
26.4.4.4.2.6.1
PCIe PHY APLL Clock Generator Power Up
26.4.4.4.2.6.2
PCIe PHY APLL Sequences
26.4.4.4.2.6.3
PCIe PHY APLL Locked Mode
26.4.4.4.3
ACSPCIE reference clock buffer
26.4.5
PCIePHY Subsystem Low-Level Programming Model
26.4.6
PCIe PHY Subsystem Register Manual
26.4.6.1
PCIe PHY Instance Summary
26.4.6.1.1
PCIe_PHY_RX Registers
26.4.6.1.1.1
PCIe_PHY_RX Register Summary
26.4.6.1.1.2
PCIe_PHY_RX Register Description
26.4.6.1.2
PCIe_PHY_TX Registers
26.4.6.1.2.1
PCIe_PHY_TX Register Summary
26.4.6.1.2.2
PCIe_PHY_TX Register Description
26.4.6.1.3
OCP2SCP Registers
26.4.6.1.3.1
OCP2SCP Register Summary
26.4.6.1.3.2
OCP2SCP Register Description
27
General-Purpose Interface
27.1
General-Purpose Interface Overview
27.2
General-Purpose Interface Environment
27.2.1
General-Purpose Interface as a Keyboard Interface
27.2.2
General-Purpose Interface Signals
27.3
General-Purpose Interface Integration
27.4
General-Purpose Interface Functional Description
27.4.1
General-Purpose Interface Block Diagram
27.4.2
General-Purpose Interface Interrupt and Wake-Up Features
27.4.2.1
Synchronous Path: Interrupt Request Generation
27.4.2.2
Asynchronous Path: Wake-Up Request Generation
27.4.2.3
Wake-Up Event Conditions During Transition To/From IDLE State
27.4.2.4
Interrupt (or Wake-Up) Line Release
27.4.3
General-Purpose Interface Clock Configuration
27.4.3.1
Clocking
27.4.4
General-Purpose Interface Hardware and Software Reset
27.4.5
General-Purpose Interface Power Management
27.4.5.1
Power Domain
27.4.5.2
Power Management
27.4.5.2.1
Idle Scheme
27.4.5.2.2
Operating Modes
27.4.5.2.3
System Power Management and Wakeup
27.4.5.2.4
Module Power Saving
27.4.6
General-Purpose Interface Interrupt and Wake-Up Requests
27.4.6.1
Interrupt Requests Generation
27.4.6.2
Wake-Up Requests Generation
27.4.7
General-Purpose Interface Channels Description
27.4.8
General-Purpose Interface Data Input/Output Capabilities
27.4.9
General-Purpose Interface Set-and-Clear Protocol
27.4.9.1
Description
27.4.9.2
Clear Instruction
27.4.9.2.1
Clear Register Addresses
27.4.9.2.2
Clear Instruction Example
27.4.9.3
Set Instruction
27.4.9.3.1
Set Register Addresses
27.4.9.3.2
Set Instruction Example
27.5
General-Purpose Interface Programming Guide
27.5.1
General-Purpose Interface Low-Level Programming Models
27.5.1.1
Global Initialization
27.5.1.1.1
Surrounding Modules Global Initialization
27.5.1.1.2
General-Purpose Interface Module Global Initialization
27.5.1.2
General-Purpose Interface Operational Modes Configuration
27.5.1.2.1
General-Purpose Interface Read Input Register
27.5.1.2.2
General-Purpose Interface Set Bit Function
27.5.1.2.3
General-Purpose Interface Clear Bit Function
27.6
General-Purpose Interface Register Manual
27.6.1
General-Purpose Interface Instance Summary
27.6.2
General-Purpose Interface Registers
27.6.2.1
General-Purpose Interface Register Summary
27.6.2.2
General-Purpose Interface Register Description
28
Keyboard Controller
28.1
Keyboard Controller Overview
28.2
Keyboard Controller Environment
28.2.1
Keyboard Controller Functions/Modes
28.2.2
Keyboard Controller Signals
28.2.3
Protocols and Data Formats
28.3
Keyboard Controller Integration
28.4
Keyboard Controller Functional Description
28.4.1
Keyboard Controller Block Diagram
28.4.2
Keyboard Controller Software Reset
28.4.3
Keyboard Controller Power Management
28.4.4
Keyboard Controller Interrupt Requests
28.4.5
Keyboard Controller Software Mode
28.4.6
Keyboard Controller Hardware Decoding Modes
28.4.6.1
Functional Modes
28.4.6.2
Keyboard Controller Timer
28.4.6.3
State-Machine Status
28.4.6.4
Keyboard Controller Interrupt Generation
28.4.6.4.1
Interrupt-Generation Scheme
28.4.6.4.2
Keyboard Buffer and Missed Events (Overrun Feature)
28.4.7
Keyboard Controller Key Coding Registers
28.4.8
Keyboard Controller Register Access
28.4.8.1
Write Registers Access
28.4.8.2
Read Registers Access
28.5
Keyboard Controller Programming Guide
28.5.1
Keyboard Controller Low-Level Programming Models
28.5.1.1
Global Initialization
28.5.1.1.1
Surrounding Modules Global Initialization
28.5.1.1.2
Keyboard Controller Global Initialization
28.5.1.1.2.1
Main Sequence – Keyboard Controller Global Initialization
28.5.1.2
Operational Modes Configuration
28.5.1.2.1
Keyboard Controller in Hardware Decoding Mode (Default Mode)
28.5.1.2.1.1
Main Sequence – Keyboard Controller Hardware Mode
28.5.1.2.2
Keyboard Controller Software Scanning Mode
28.5.1.2.2.1
Main Sequence – Keyboard Controller Software Mode
28.5.1.2.3
Using the Timer
28.5.1.2.4
State-Machine Status Register
28.5.1.3
Keyboard Controller Events Servicing
28.6
Keyboard Controller Register Manual
28.6.1
Keyboard Controller Instance Summary
28.6.2
Keyboard Controller Registers
28.6.2.1
Keyboard Controller Register Summary
28.6.2.2
Keyboard Controller Register Description
29
Pulse-Width Modulation Subsystem
29.1
PWM Subsystem Resources
29.1.1
PWMSS Overview
29.1.1.1
PWMSS Key Features
29.1.1.2
PWMSS Unsupported Fetaures
29.1.2
PWMSS Environment
29.1.2.1
PWMSS I/O Interface
29.1.3
PWMSS Integration
29.1.3.1
PWMSS Module Interfaces Implementation
29.1.3.1.1
Device Specific PWMSS Features
29.1.3.1.2
Daisy-Chain Connectivity between PWMSS Modules
29.1.3.1.3
eHRPWM Modules Time Base Clock Gating
29.1.4
PWMSS Subsystem Power, Reset and Clock Configuration
29.1.4.1
PWMSS Local Clock Management
29.1.4.2
PWMSS Modules Local Clock Gating
29.1.4.3
PWMSS Software Reset
29.1.5
PWMSS_CFG Register Manual
29.1.5.1
PWMSS_CFG Instance Summary
29.1.5.2
PWMSS_CFG Registers
29.1.5.2.1
PWMSS_CFG Register Summary
29.1.5.2.2
PWMSS_CFG Register Description
29.2
Enhanced PWM (ePWM) Module
29.3
Enhanced Capture (eCAP) Module
29.4
Enhanced Quadrature Encoder Pulse (eQEP) Module
30
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem
30.1
PRU-ICSS Overview
30.1.1
PRU-ICSS Key Features
30.2
PRU-ICSS Environment
30.2.1
PRU-ICSS I/O Interface
30.3
PRU-ICSS Integration
30.4
PRU-ICSS Level Resources Functional Description
30.4.1
PRU-ICSS Reset Management
30.4.2
PRU-ICSS Power and Clock Management
30.4.2.1
PRU-ICSS Idle and Standby States
30.4.2.2
Module Clock Configurations at PRU-ICSS Top Level
30.4.3
Other PRU-ICSS Module Functional Registers at Subsystem Level
30.4.4
PRU-ICSS Memory Maps
30.4.4.1
PRU-ICSS Local Memory Map
30.4.4.1.1
PRU-ICSS Local Instruction Memory Map
30.4.4.1.2
PRU-ICSS Local Data Memory Map
30.4.4.2
PRU-ICSS Global Memory Map
30.4.5
PRUSS_CFG Register Manual
30.4.5.1
PRUSS_CFG Instance Summary
30.4.5.2
PRUSS_CFG Registers
30.4.5.2.1
PRUSS_CFG Register Summary
30.4.5.2.2
PRUSS_CFG Register Description
30.5
PRU-ICSS PRU Cores
30.6
PRU-ICSS Local Interrupt Controller
30.6.1
PRU-ICSS Interrupt Controller Overview
30.6.2
PRU-ICSS Interrupt Controller Functional Description
30.6.2.1
PRU-ICSS Interrupt Controller System Events
30.6.2.2
PRU-ICSS Interrupt Controller System Events Flow
30.6.2.2.1
PRU-ICSS Interrupt Processing
30.6.2.2.1.1
PRU-ICSS Interrupt Enabling
30.6.2.2.2
PRU-ICSS Interrupt Status Checking
30.6.2.2.3
PRU-ICSS Interrupt Channel Mapping
30.6.2.2.3.1
PRU-ICSS Host Interrupt Mapping
30.6.2.2.3.2
PRU-ICSS Interrupt Prioritization
30.6.2.2.4
PRU-ICSS Interrupt Nesting
30.6.2.2.5
PRU-ICSS Interrupt Status Clearing
30.6.2.3
PRU-ICSS Interrupt Disabling
30.6.3
PRU-ICSS Interrupt Controller Basic Programming Model
30.6.4
PRU-ICSS Interrupt Requests Mapping
30.6.5
PRU-ICSS Interrupt Controller Register Manual
30.6.5.1
PRUSS_INTC Instance Summary
30.6.5.2
PRUSS_INTC Registers
30.6.5.2.1
PRUSS_INTC Register Summary
30.6.5.2.2
PRUSS_INTC Register Description
30.7
PRU-ICSS UART Module
30.7.1
PRU-ICSS UART Module Overview
30.7.1.1
Purpose of the PRU-ICSS integrated UART Peripheral
30.7.1.2
PRU-ICSS UART Key Features
30.7.1.2.1
PRU-ICSS UART Module Industry Standard Compliance Statement
30.7.2
PRU-ICSS UART Environment
30.7.2.1
PRU-ICSS UART Pin Multiplexing
30.7.2.2
PRU-ICSS UART Signal Descriptions
30.7.2.3
PRU-ICSS UART Data Format and Protocol Description
30.7.2.3.1
PRU-ICSS UART Transmission Protocol
30.7.2.3.2
PRU-ICSS UART Reception Protocol
30.7.2.3.3
PRU-ICSS UART Data Format
30.7.2.3.3.1
Frame Formatting
30.7.2.4
PRU-ICSS UART Clock Generation and Control
30.7.3
PRU-ICSS UART Module Functional Description
30.7.3.1
PRU-ICSS UART Functional Block Diagram
30.7.3.2
PRU-ICSS UART Reset Considerations
30.7.3.2.1
PRU-ICSS UART Software Reset Considerations
30.7.3.2.2
PRU-ICSS UART Hardware Reset Considerations
30.7.3.3
PRU-ICSS UART Power Management
30.7.3.4
PRU-ICSS UART Interrupt Support
30.7.3.4.1
PRU-ICSS UART Interrupt Events and Requests
30.7.3.4.2
PRU-ICSS UART Interrupt Multiplexing
30.7.3.4.3
4060
30.7.3.5
4061
30.7.3.6
PRU-ICSS UART DMA Event Support
30.7.3.7
PRU-ICSS UART Operations
30.7.3.7.1
PRU-ICSS UART Transmission
30.7.3.7.2
PRU-ICSS UART Reception
30.7.3.7.3
PRU-ICSS UART FIFO Modes
30.7.3.7.3.1
PRU-ICSS UART FIFO Interrupt Mode
30.7.3.7.3.2
PRU-ICSS UART FIFO Poll Mode
30.7.3.7.4
PRU-ICSS UART Autoflow Control
30.7.3.7.4.1
PRU-ICSS UART Signal UART0_RTS Behavior
30.7.3.7.4.2
PRU-ICSS UART Signal PRUSS_UART0_CTS Behavior
30.7.3.7.5
PRU-ICSS UART Loopback Control
30.7.3.8
PRU-ICSS UART Initialization
30.7.3.9
PRU-ICSS UART Exception Processing
30.7.3.9.1
PRU-ICSS UART Divisor Latch Not Programmed
30.7.3.9.2
Changing Operating Mode During Busy Serial Communication of PRU-ICSS UART
30.7.4
PRUSS_UART Register Manual
30.7.4.1
PRUSS_UART Instance Summary
30.7.4.2
PRUSS_UART Registers
30.7.4.2.1
PRUSS_UART Register Summary
30.7.4.2.2
PRUSS_UART Register Description
30.8
PRU-ICSS eCAP Module
30.8.1
4083
30.8.2
PRU-ICSS eCAP Functional Description
30.8.3
PRUSS_ECAP Register Manual
30.8.3.1
PRUSS_ECAP Instance Summary
30.8.3.2
PRUSS_ECAP Registers
30.8.3.2.1
PRUSS_ECAP Register Summary
30.8.3.2.2
PRUSS_ECAP Register Description
30.9
PRU-ICSS MII RT Module
30.9.1
Introduction
30.9.1.1
Features
30.9.1.2
Unsupported Features
30.9.1.3
Block Diagram
30.9.2
Functional Description
30.9.2.1
Data Path Configuration
30.9.2.1.1
Auto-forward with Optional PRU Snoop
30.9.2.1.2
8- or 16-bit Processing with On-the-Fly Modifications
30.9.2.1.3
32-byte Double Buffer or Ping-Pong Processing
30.9.2.2
Definition and Terms
30.9.2.2.1
Data Frame Structure
30.9.2.2.2
PRU R30 and R31
30.9.2.2.3
RX and TX L1 FIFO Data Movement
30.9.2.2.4
CRC Computation
30.9.2.2.4.1
Receive CRC Computation
30.9.2.2.4.2
Transmit CRC Computation
30.9.2.3
RX MII Interface
30.9.2.3.1
RX MII Submodule Overview
30.9.2.3.1.1
Receive Data Latch
30.9.2.3.1.1.1
Start of Frame Detection
30.9.2.3.1.1.2
CRC Error Detection
30.9.2.3.1.1.3
RX Error Detection and Action
30.9.2.3.1.2
RX Data Path Options to PRU
30.9.2.3.1.2.1
RX MII Port → RX L1 FIFO → PRU
30.9.2.3.1.2.2
RX MII Port → RX L1 FIFO → RX L2 Buffer → PRU
30.9.2.4
TX MII Interface
30.9.2.4.1
TX Data Path Options to TX L1 FIFO
30.9.2.4.1.1
PRU → TX L1 FIFO → TX MII Port
30.9.2.4.1.2
RX L1 FIFO → TX L1 FIFO → TX MII Port
30.9.2.5
PRU R31 Command Interface
30.9.2.6
Other Configuration Options
30.9.2.6.1
Nibble and Byte Order
30.9.2.6.2
Preamble Source
30.9.2.6.3
PRU and MII Port Multiplexer
30.9.2.6.3.1
Receive Multiplexer
30.9.2.6.3.2
Transmit Multiplexer
30.9.2.6.4
RX L2 Scratch Pad
30.9.3
PRU-ICSS MII RT Module Register Manual
30.9.3.1
PRUSS_MII_RT Instance Summary
30.9.3.2
PRUSS_MII_RT Registers
30.9.3.2.1
PRUSS_MII_RT Register Summary
30.9.3.2.2
PRUSS_MII_RT Register Description
30.10
PRU-ICSS MII MDIO Module
30.10.1
PRU-ICSS MII MDIO Overview
30.10.2
PRU-ICSS MII MDIO Functional Description
30.10.2.1
MII MDIO Management Interface Frame Formats
30.10.2.2
PRU-ICSS MII MDIO Interractions
30.10.2.3
PRU-ICSS MII MDIO Interrupts
30.10.3
PRU-ICSS MII MDIO Receive/Transmit Frame Host Software Interface
30.10.4
PRU-ICSS MII MDIO Module Register Manual
30.10.4.1
PRUSS_MII_MDIO Instance Summary
30.10.4.2
PRUSS_MII_MDIO Registers
30.10.4.2.1
PRUSS_MII_MDIO Register Summary
30.10.4.2.2
PRUSS_MII_MDIO Register Description
30.11
PRU-ICSS Industrial Ethernet Peripheral (IEP)
30.11.1
PRU-ICSS IEP Overview
30.11.2
PRU-ICSS IEP Functional Description
30.11.2.1
PRU-ICSS IEP Clock Generation
30.11.2.2
PRU-ICSS Industrial Ethernet Timer
30.11.2.2.1
PRU-ICSS Industrial Ethernet Timer Features
30.11.2.2.2
Industrial Ethernet Mapping
30.11.2.2.3
PRU-ICSS Industrial Ethernet Timer Basic Programming Sequence
30.11.2.3
PRU-ICSS IEP Sync0/Sync1 Signals Generation
30.11.2.3.1
PRU-ICSS IEP Sync0/Sync1 Features
30.11.2.3.2
PRU-ICSS IEP Sync0/Sync1 Generation Modes
30.11.2.4
PRU-ICSS Industrial Ethernet WatchDog
30.11.2.4.1
Features
30.11.2.5
PRU-ICSS Industrial Ethernet Digital IOs
30.11.2.5.1
Features
30.11.2.5.2
4160
30.11.2.5.3
DIGIO Block Diagrams
30.11.2.5.4
Basic Programming Model
30.11.3
PRUSS_IEP Register Manual
30.11.3.1
PRUSS_IEP Instance Summary
30.11.3.2
PRUSS_IEP Registers
30.11.3.2.1
PRUSS_IEP Register Summary
30.11.3.2.2
PRUSS_IEP Register Description
31
Viterbi-Decoder Coprocessor
32
Audio Tracking Logic
33
Initialization
33.1
Initialization Overview
33.1.1
Terminology
33.1.2
Initialization Process
33.2
Preinitialization
33.2.1
Power Requirements
33.2.2
Boot Device Conditions
33.2.3
Clock, Reset, and Control
33.2.3.1
Overview
33.2.3.2
Clocking Scheme
33.2.3.3
Reset Configuration
33.2.3.3.1
ON/OFF Interconnect and Power-On-Reset
33.2.3.3.2
Warm Reset
33.2.3.3.3
Peripheral Reset by GPIO
33.2.3.3.4
Warm Reset Impact on GPIOs
33.2.3.4
PMIC Control
33.2.3.5
PMIC Request Signals
33.2.4
Sysboot Configuration
33.2.4.1
GPMC Configuration for XIP/NAND
33.2.4.2
System Clock Speed Selection
33.2.4.3
QSPI Redundant SBL Images Offset
33.2.4.4
Booting Device Order Selection
33.2.4.5
4192
33.2.4.6
Boot Peripheral Pin Multiplexing
33.3
Device Initialization by ROM Code
33.3.1
Booting Overview
33.3.1.1
Booting Types
33.3.1.2
ROM Code Architecture
33.3.2
Memory Maps
33.3.2.1
ROM Memory Map
33.3.2.2
RAM Memory Map
33.3.3
Overall Booting Sequence
33.3.4
Startup and Configuration
33.3.4.1
Startup
33.3.4.2
Control Module Configuration
33.3.4.3
PRCM Module Mode Configuration
33.3.4.4
Clocking Configuration
33.3.4.5
Booting Device List Setup
33.3.5
Peripheral Booting
33.3.5.1
Description
33.3.5.2
Initialization Phase for UART Boot
33.3.5.3
Initialization Phase for USB Boot
33.3.5.3.1
Initialization Procedure
33.3.5.3.2
SATA Peripheral Device Flashing over USB Interface
33.3.5.3.3
USB Driver Descriptors
33.3.5.3.4
4215
33.3.5.3.5
USB Customized Vendor and Product IDs
33.3.5.3.6
USB Driver Functionality
33.3.6
Fast External Booting
33.3.6.1
Overview
33.3.6.2
Fast External Booting Procedure
33.3.7
Memory Booting
33.3.7.1
Overview
33.3.7.2
Non-XIP Memory
33.3.7.3
XIP Memory
33.3.7.3.1
GPMC Initialization
33.3.7.4
NAND
33.3.7.4.1
Initialization and NAND Detection
33.3.7.4.2
NAND Read Sector Procedure
33.3.7.5
SPI/QSPI Flash Devices
33.3.7.6
eMMC Memories and SD Cards
33.3.7.6.1
eMMC Memories
33.3.7.6.1.1
System Conditions and Limitations
33.3.7.6.1.2
eMMC Memory Connection
33.3.7.6.2
SD Cards
33.3.7.6.2.1
System Conditions and Limitations
33.3.7.6.2.2
SD Card Connection
33.3.7.6.2.3
Booting Procedure
33.3.7.6.2.4
eMMC Partitions Handling in Alternative Boot Operation Mode
33.3.7.6.2.4.1
eMMC Devices Preflashing
33.3.7.6.2.4.2
eMMC Device State After ROM Code Execution
33.3.7.6.2.4.3
Consideration on device Global Warm Reset
33.3.7.6.2.4.4
Booting Image Size
33.3.7.6.2.4.5
Booting Image Layout
33.3.7.6.3
Initialization and Detection
33.3.7.6.4
Read Sector Procedure
33.3.7.6.5
File System Handling
33.3.7.6.5.1
MBR and FAT File System
33.3.7.7
SATA Device Boot Operation
33.3.7.7.1
SATA Booting Overview
33.3.7.7.2
SATA Power-Up Initialization Sequence
33.3.7.7.3
System Conditions and Limitations for SATA Boot
33.3.7.7.4
SATA Read Sector Procedure in FAT Mode
33.3.8
Image Format
33.3.8.1
Overview
33.3.8.2
Configuration Header
33.3.8.2.1
CHSETTINGS Item
33.3.8.2.2
CHFLASH Item
33.3.8.2.3
CHMMCSD Item
33.3.8.2.4
CHQSPI Item
33.3.8.3
GP Header
33.3.8.4
Image Execution
33.3.9
Tracing
33.4
Services for HLOS Support
33.4.1
Hypervisor
33.4.2
Caches Maintenance
33.4.3
CP15 Registers
33.4.4
Wakeup Generator
33.4.5
Arm Timer
33.4.6
MReq Domain
34
On-Chip Debug Support
34.1
Introduction
34.1.1
Key Features
34.2
Debug Interfaces
34.2.1
IEEE1149.1
34.2.2
Debug (Trace) Port
34.2.3
Trace Connector and Board Layout Considerations
34.3
Debugger Connection
34.3.1
ICEPick Module
34.3.2
ICEPick Boot Modes
34.3.2.1
Default Boot Mode
34.3.2.2
Wait-In-Reset
34.3.3
Dynamic TAP Insertion
34.3.3.1
ICEPick Secondary TAPs
34.4
Primary Debug Support
34.4.1
Processor Native Debug Support
34.4.1.1
Cortex-A15 Processor
34.4.1.2
Cortex-M4 Processor
34.4.1.3
DSP C66x
34.4.1.4
IVA Arm968
34.4.1.5
PRU
34.4.2
Cross-Triggering
34.4.2.1
SoC-Level Cross-Triggering
34.4.2.2
Cross-Triggering With External Device
34.4.3
Suspend
34.4.3.1
Debug Aware Peripherals and Host Processors
34.5
Real-Time Debug
34.5.1
Real-Time Debug Events
34.5.1.1
Emulation Interrupts
34.6
Power, Reset, and Clock Management Debug Support
34.6.1
Power and Clock Management
34.6.1.1
Power and Clock Control Override From Debugger
34.6.1.1.1
Debugger Directives
34.6.1.1.1.1
FORCEACTIVE Debugger Directive
34.6.1.1.1.2
INHIBITSLEEP Debugger Directive
34.6.1.1.2
Intrusive Debug Model
34.6.1.2
Debug Across Power Transition
34.6.1.2.1
Nonintrusive Debug Model
34.6.1.2.2
Debug Context Save and Restore
34.6.1.2.2.1
Debug Context Save
34.6.1.2.2.2
Debug Context Restore
34.6.2
Reset Management
34.6.2.1
Debugger Directives
34.6.2.1.1
Assert Reset
34.6.2.1.2
Block Reset
34.6.2.1.3
Wait-In-Reset
34.7
Performance Monitoring
34.7.1
MPU Subsystem Performance Monitoring
34.7.1.1
Performance Monitoring Unit
34.7.1.2
L2 Cache Controller
34.7.2
IPU Subsystem Performance Monitoring
34.7.2.1
Subsystem Counter Timer Module
34.7.2.2
Cache Events
34.7.3
DSP Subsystem Performance Monitoring
34.7.3.1
Advanced Event Triggering
34.8
MPU Memory Adaptor (MPU_MA) Watchpoint
34.9
Processor Trace
34.9.1
Cortex-A15 Processor Trace
34.9.2
DSP Processor Trace
34.9.3
Trace Export
34.9.3.1
Trace Exported to External Trace Receiver
34.9.3.2
Trace Captured Into On-Chip Trace Buffer
34.9.3.3
Trace Exported Through USB
34.10
System Instrumentation
34.10.1
MIPI STM (CT_STM)
34.10.2
System Trace Export
34.10.2.1
CT_STM ATB Export
34.10.2.2
Trace Streams Interleaving
34.10.3
Software Instrumentation
34.10.3.1
MPU Software Instrumentation
34.10.3.2
SoC Software Instrumentation
34.10.4
OCP Watchpoint
34.10.4.1
OCP Target Traffic Monitoring
34.10.4.2
Messages Triggered from System Events
34.10.4.3
DMA Transfer Profiling
34.10.5
IVA Pipeline
34.10.6
L3 NOC Statistics Collector
34.10.6.1
L3 Target Load Monitoring
34.10.6.2
L3 Master Latency Monitoring
34.10.6.2.1
SC_LAT0 Configuration
34.10.6.2.2
SC_LAT1 Configuration
34.10.6.2.3
SC_LAT2 Configuration
34.10.6.2.4
SC_LAT3 Configuration
34.10.6.2.5
SC_LAT4 Configuration
34.10.6.2.6
SC_LAT5 Configuration
34.10.6.2.7
SC_LAT6 Configuration
34.10.6.2.8
SC_LAT7 Configuration
34.10.6.2.9
SC_LAT8 Configuration
34.10.6.2.10
Statistics Collector Alarm Mode
34.10.6.2.11
Statistics Collector Suspend Mode
34.10.7
PM Instrumentation
34.10.8
CM Instrumentation
34.10.9
Master-ID Encoding
34.10.9.1
Software Masters
34.10.9.2
Hardware Masters
34.11
Concurrent Debug Modes
34.12
DRM Register Manual
34.12.1
DRM Instance Summary
34.12.2
DRM Registers
34.12.2.1
DRM Register Summary
34.12.2.2
DRM Register Description
35
Glossary
36
Revision History
4.4.12
MPU_MA_WP Registers