SPRUJ42E March 2022 – October 2024 AM2631 , AM2631-Q1 , AM2632 , AM2632-Q1 , AM2634 , AM2634-Q1
PRODUCTION DATA
Offset | Length | Register Name | R5SS0 Physical Address | R5SS1 Physical Address |
---|---|---|---|---|
0h | 32 | ECC_AGG_CORE0_AGGR_REVISION | 5300 0000h | 5300 4000h |
8h | 32 | ECC_AGG_CORE0_ECC_VECTOR | 5300 0008h | 5300 4008h |
Ch | 32 | ECC_AGG_CORE0_MISC_STATUS | 5300 000Ch | 5300 400Ch |
10h | 32 | ECC_AGG_CORE0_ECC_WRAP_REVISION | 5300 0010h | 5300 4010h |
14h | 32 | ECC_AGG_CORE0_CONTROL | 5300 0014h | 5300 4014h |
18h | 32 | ECC_AGG_CORE0_ERROR_CTRL1 | 5300 0018h | 5300 4018h |
1Ch | 32 | ECC_AGG_CORE0_ERROR_CTRL2 | 5300 001Ch | 5300 401Ch |
20h | 32 | ECC_AGG_CORE0_ERROR_STATUS1 | 5300 0020h | 5300 4020h |
24h | 32 | ECC_AGG_CORE0_ERROR_STATUS2 | 5300 0024h | 5300 4024h |
28h | 32 | ECC_AGG_CORE0_ERROR_STATUS3 | 5300 0028h | 5300 4028h |
3Ch | 32 | ECC_AGG_CORE0_SEC_EOI_REG | 5300 003Ch | 5300 403Ch |
40h | 32 | ECC_AGG_CORE0_SEC_STATUS_REG0 | 5300 0040h | 5300 4040h |
80h | 32 | ECC_AGG_CORE0_SEC_ENABLE_SET_REG0 | 5300 0080h | 5300 4080h |
C0h | 32 | ECC_AGG_CORE0_SEC_ENABLE_CLR_REG0 | 5300 00C0h | 5300 40C0h |
13Ch | 32 | ECC_AGG_CORE0_DED_EOI_REG | 5300 013Ch | 5300 413Ch |
140h | 32 | ECC_AGG_CORE0_DED_STATUS_REG0 | 5300 0140h | 5300 4140h |
180h | 32 | ECC_AGG_CORE0_DED_ENABLE_SET_REG0 | 5300 0180h | 5300 4180h |
1C0h | 32 | ECC_AGG_CORE0_DED_ENABLE_CLR_REG0 | 5300 01C0h | 5300 41C0h |
200h | 32 | ECC_AGG_CORE0_AGGR_ENABLE_SET | 5300 0200h | 5300 4200h |
204h | 32 | ECC_AGG_CORE0_AGGR_ENABLE_CLR | 5300 0204h | 5300 4204h |
208h | 32 | ECC_AGG_CORE0_AGGR_STATUS_SET | 5300 0208h | 5300 4208h |
20Ch | 32 | ECC_AGG_CORE0_AGGR_STATUS_CLR | 5300 020Ch | 5300 420Ch |