• Menu
  • Product
  • Email
  • PDF
  • Order now
  • Calculating Conversion Latency and System Cycle Time for Delta-Sigma ADCs

    • SBAA535A March   2022  – March 2024 ADC128D818 , ADS1000 , ADS1000-Q1 , ADS1013 , ADS1013-Q1 , ADS1014 , ADS1014-Q1 , ADS1015 , ADS1015-Q1 , ADS1018 , ADS1018-Q1 , ADS1100 , ADS1110 , ADS1112 , ADS1113 , ADS1113-Q1 , ADS1114 , ADS1114-Q1 , ADS1115 , ADS1115-Q1 , ADS1118 , ADS1118-Q1 , ADS1119 , ADS1120 , ADS1120-Q1 , ADS112C04 , ADS112U04 , ADS1130 , ADS1131 , ADS1146 , ADS1147 , ADS1148 , ADS1148-Q1 , ADS114S06 , ADS114S06B , ADS114S08 , ADS114S08B , ADS1158 , ADS1216 , ADS1217 , ADS1218 , ADS1219 , ADS1220 , ADS122C04 , ADS122U04 , ADS1230 , ADS1231 , ADS1232 , ADS1234 , ADS1235 , ADS1235-Q1 , ADS1243-HT , ADS1246 , ADS1247 , ADS1248 , ADS124S06 , ADS124S08 , ADS1250 , ADS1251 , ADS1252 , ADS1253 , ADS1254 , ADS1255 , ADS1256 , ADS1257 , ADS1258 , ADS1258-EP , ADS1259 , ADS1259-Q1 , ADS125H01 , ADS125H02 , ADS1260 , ADS1260-Q1 , ADS1261 , ADS1261-Q1 , ADS1262 , ADS1263 , ADS127L01 , ADS1281 , ADS1282 , ADS1282-SP , ADS1283 , ADS1284 , ADS1287 , ADS1291 , LMP90080-Q1 , LMP90100 , TLA2021 , TLA2022 , TLA2024

       

  • CONTENTS
  • SEARCH
  • Calculating Conversion Latency and System Cycle Time for Delta-Sigma ADCs
  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Data Sheet Timing and Nomenclature
  6. 3 What Causes Conversion Latency in a Delta-Sigma ADC?
  7. 4 Digital Filter Operation and Behavior
    1.     8
    2.     9
    3. 4.1 Unsettled Data Due to an ADC Operation
  8. 5 ADC Features and Modes that Affect Conversion Latency
    1. 5.1 First Conversion Versus Second and Subsequent Conversion Latency
    2. 5.2 Conversion Mode
    3. 5.3 Programmable Delay
    4. 5.4 ADC Overhead Time
    5. 5.5 Clock Frequency
    6. 5.6 Chopping
  9. 6 Analog Settling
  10. 7 Important Takeaways
  11. 8 Cycle Time Calculation Examples
    1. 8.1 Example #1: Using the ADS124S08
    2. 8.2 Example #2: Changing the Conversion Mode
    3. 8.3 Example #3: Changing the Filter Type
    4. 8.4 Example #4: Changing the Clock Frequency
    5. 8.5 Example #5: Enabling Chop and Reducing the Number of Conversions per Channel
    6. 8.6 Example #6: Scanning Two Channels With Different System Parameters
    7. 8.7 Example #7: Using the ADS1261
    8. 8.8 Example #8: Changing Multiple Parameters Using the ADS1261
  12. 9 Summary
  13. 10Revision History
  14. IMPORTANT NOTICE
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

Application Note

Calculating Conversion Latency and System Cycle Time for Delta-Sigma ADCs

Abstract

Many precision data acquisition applications are constrained by a system cycle time, or the total time required to perform one complete loop through all measurement channels. However, it is not always clear how this metric correlates to the information provided in a delta-sigma analog-to-digital converter (ADC) data sheet, which may include multiple features and modes that affect the rate at which the device outputs data. To provide a deeper understanding of how to calculate the system cycle time using the ADC data sheet information, this application note offers a detailed discussion of the most important factors that affect ADC conversion latency. Additionally, key takeaways are summarized and several examples using actual ADCs are provided.

Trademarks

All trademarks are the property of their respective owners.

1 Introduction

One important consideration when choosing a delta-sigma analog-to-digital converter (ADC) for a specific application is the system cycle time, or the total time required to perform one complete loop through all measurement channels. This cycle time could require reading a single conversion result from a single channel, a single conversion result from multiple channels, or multiple conversion results from multiple channels. Additionally, individual conversion results can require multiple conversion periods to generate settled data. How does a design engineer use the information in the ADC data sheet to select a device that meets the cycle time requirements?

For example, if the cycle time requires retrieving three conversion results per channel on six channels in ten milliseconds, is it sufficient to choose an ADC that samples at 1800 SPS?

(3 conversions / channel) ∙ (6 channels) ∙ (1 / 10 ms) = 1800 SPS

Answering these questions requires a comprehensive understanding of how multiplexed delta-sigma ADCs sample and process data. To that end, this application note explores multiplexed delta-sigma ADC operation in detail, breaking up this broad topic into several subsections:

  • Data sheet timing and nomenclature
  • What causes conversion latency in a delta-sigma ADC?
  • Digital filter operation and behavior
  • First conversion versus second and subsequent conversion latency
  • Conversion mode
  • Programmable delay
  • ADC overhead time
  • Clock frequency
  • Chopping
  • Analog settling

Two additional sections at the end of this document summarize important takeaways and provide several examples that illustrate how to apply this information to a practical system.

Before introducing the first topic, note that external factors can impact delta-sigma ADC operation and timing that in turn can have an effect on cycle time. This includes but is not limited to unstable power supplies, low-accuracy clocks, and amplifier overload. This document does not discuss the impact external factors can have on calculating cycle time and assumes an ideal system, unless otherwise noted.

 

Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale