Static charge is an unbalanced electrical charge at rest. When two non-conductive materials are rubbed together or separated, there is gain of electrons on the surface of one material and loss on the other; this results in an unbalanced electrical conditions known as static charge. The voltage to which an object can be charged depends on the capacitance, following the law Q = CV. The human body can be charged to several kV. When this static charge moves from one surface to another, it is called ESD (Electrostatic Discharge). ESD is a single-event rapid transfer of electrostatic charge between two objects that are at different potentials. It can occur only when the voltage differential between the two objects is sufficiently high to break down the dielectric strength of the medium separating them. The rapid movement of the electrostatic charge generates current that damages or destroys gate oxide, metallization, and junctions within an integrated circuit (IC).

ESD can occur in any one of the four ways:

• Charged body touching an IC
• Charged IC touching a grounded surface or object
• Charged metallic tool touching an IC
• An electrostatic field inducing a voltage across a dielectric sufficient enough to break it down.

The coupling mechanisms in each of these cases are inductive, resistive, or capacitive. Creating an ESD-safe design is focused on minimizing ESD coupling by a combination of factors. To design an ESD robust product, it is important to understand that the ESD protection required at component or IC level and at system level are different.

Typically, silicon vendors design, test, and qualify their ICs according to industry standards to ensure no physical damage occurs during IC production or during assembly onto PCBs. The Original Equipment Manufacturer (OEM) should design ESD protection at a system or board level and test according to the IEC 61000-4-2 [1] or ISO 10605 [6] system-level ESD standard. Table 1-1 summarizes key differences between IC- or component-level standard HBM testing and system-level testing as required by IEC 61000-4-2 [1] and ISO 10605 [6] standards.

The component-level ESD and the system-level ESD test requirements are different as they address different ESD environments. Also, the ESD current waveforms associated with the two tests differ significantly in terms of peak current, duration, and total power. Therefore, to design an ESD robust system, it is important for the system board designers and OEMs to understand that system-level ESD protection requirements are much different from IC-level ESD protection capabilities..

The ESD protection design for an IC package is known to be critical for safe production and handling. It is commonly understood and accepted that this protection design is expected to meet or exceed the required ESD specification when these ICs are handled in an ESD-safe area, also known as ESD Protected Area (EPA) [1]. The ESD protection strategy for ICs involves discharging of the ESD events that might occur on any pin of the package that is exposed to its environment. The component-level ESD protection should consider the two basic ESD models defined for ICs: Human Body Model (HBM) and Charged Device Model (CDM).

The ESD protection circuitry within MSP430™ ICs is designed based on device technology, IC pin functionalities for different applications, power pins, and so on. The protection elements are first characterized and analyzed for effectiveness using test chips. Simulations and automated checks are used, where appropriate, to ensure effectiveness of the protection circuitry and check for its compatibility with the pin it is designed to protect.

Typical MSP430 devices are tested and qualified to the following industry-standard ESD ratings.