The AFE7799 is a high-performance, multichannel transceiver, integrating four direct up-conversion transmitter chains, four direct down-conversion receiver chains, and two wideband RF sampling digitizing auxiliary chains (feedback paths). The high dynamic range of the transmitter and receiver chains allows generating and receiving 2G, 3G, 4G, and 5G signals for wireless base stations. The low power dissipation and large channels integration makes the AFE7799 suitable to address the power and size constrained 4G and 5G massive MIMO base stations. The wideband and high dynamic range feedback path can assist the digital pre-distortion (DPD) of the power amplifiers in the transmitter chain. The fast SerDes speed can help reducing the number of lanes required to transfer the data in and out.
Each receiver chain of the AFE7799 includes a 28-dB range digital step attenuator (DSA), followed by a wideband passive IQ demodulator, and a baseband amplifier with integrated programmable antialiasing low pass filters, driving a continuous-time sigma-delta ADC. The RX chain can receive an instantaneous bandwidth (IBW) up to 200 MHz. Each receiver channel has two analog peak power detectors and various digital power detectors to assist an external or internal autonomous AGC control for receiver channels, and a RF overload detector for device reliability protection. The integrated QMC (quadrature mismatch compensation) algorithm is capable to continuously monitor and correct for the rx chain I and Q imbalance mismatch without the need to inject any specific signals or perform offline calibration.
Each transmitter chain includes two 14-bit, 3-Gsps IQ DACs, followed by a programmable reconstruction and DAC image rejection filter, an IQ modulator driving a wideband RF amplifier with 39-dB range gain control. The TX chain integrated QMC and LO leakage cancellation algorithms, leveraging the FB path can constantly track and correct for the TX chain IQ mismatch and LO leakage.
The FB path is based on RF sampling architecture, and includes an input RF DSA driving a 14-bit, 3-Gsps RF ADC. The direct sampling architecture provides an inherently wideband receiver chain and simplifies the calibration of the TX chains impairments. Each FB path integrates two independent NCO that allows a fast switching between two observed RF input bands.
See the full data sheet and other design resources for the commercial wireless-specific AFE7799. Request now
For all other applications, see our general-purpose RF-sampling AFEs.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | AFE7799 Quad-Channel RF Transceiver With Feedback Path datasheet | PDF | HTML | 06 Jun 2019 |
| Application note | Using AFE77xx in a Digital Pre-distortion System (Rev. B) | 02 Sep 2021 | ||
| Application note | System Design Considerations when Upgrading from JESD204B to JESD204C (Rev. A) | 05 Apr 2021 | ||
| Application note | Time Division Duplexing (TDD) in AFE77xx Integrated Transceiver (Rev. A) | 05 Apr 2021 | ||
| Application note | AFE76xx, AFE77xx, and AFE79xx JESD204 Layer Testing | 15 Apr 2020 | ||
| User guide | AFE77xx Latte GUI | 25 Jul 2019 | ||
| Application note | Temp Profile to Maintain Optimum FIT Performance | 23 Jul 2019 | ||
| Application note | Controlling Latte GUI from Python | 08 Jul 2019 | ||
| Application note | AFE77xx Power Solutions | 25 Jun 2019 |
For additional terms or required resources, click any title below to view the detail page where available.
The AFE7769-3P5 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE7769 and AFE7799 devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled (...)
The AFE7769 evaluation module (EVM) is a board used to evaluate the AFE77xx family of integrated RF transceivers. AFE77xx devices support up to four-transmit, four-receive, and two feedback channels (4T4R2F) and integrate phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs) for (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| FCBGA (ABJ) | 400 | Ultra Librarian |
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