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SN74CB3T3253

ACTIVE

3.3-V, 4:1, 2-channel FET bus switch with level shifter

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Data sheet

SN74CB3T3253

ACTIVE
Data sheet Order now

Product details

Configuration 4:1 Number of channels 2 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 5 CON (typ) (pF) 4 ON-state leakage current (max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 4:1 Number of channels 2 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 5 CON (typ) (pF) 4 ON-state leakage current (max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
SOIC (D) 16 59.4 mm² 9.9 x 6 SSOP (DBQ) 16 29.4 mm² 4.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4 TVSOP (DGV) 16 23.04 mm² 3.6 x 6.4
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation On All Data I/O Ports
    • 5-V Input Down To 3.3-V Output Level Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down To 2.5-V Output Level Shift With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered-Up or Powered-Down
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 5 Typical)
  • Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 20 µA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications: Level Translation, USB Interface, Memory Interleaving, Bus Isolation
  • Ideal for Low-Power Portable Equipment
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation On All Data I/O Ports
    • 5-V Input Down To 3.3-V Output Level Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down To 2.5-V Output Level Shift With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered-Up or Powered-Down
  • Bidirectional Data Flow, With Near-Zero Propagation Delay
  • Low ON-State Resistance (ron) Characteristics (ron = 5 Typical)
  • Low Input/Output Capacitance Minimizes Loading (Cio(OFF) = 5 pF Typical)
  • Data and Control Inputs Provide Undershoot Clamp Diodes
  • Low Power Consumption (ICC = 20 µA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
  • Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications: Level Translation, USB Interface, Memory Interleaving, Bus Isolation
  • Ideal for Low-Power Portable Equipment

The SN74CB3T3253 is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3253 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).

The SN74CB3T3253 is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable (1OE\, 2OE\) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When OE\ is low, the associated multiplexer/demultiplexer is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated multiplexer/demultiplexer is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3T3253 is a high-speed TTL-compatible FET multiplexer/demultiplexer with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T3253 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).

The SN74CB3T3253 is organized as two 1-of-4 multiplexer/demultiplexers with separate output-enable (1OE\, 2OE\) inputs. The select (S0, S1) inputs control the data path of each multiplexer/demultiplexer. When OE\ is low, the associated multiplexer/demultiplexer is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE\ is high, the associated multiplexer/demultiplexer is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Technical documentation

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Type Title Date
* Data sheet SN74CB3T3253 datasheet 15 Oct 2003
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dec 2021
Application note CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. C) PDF | HTML 19 Nov 2021
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 06 Jan 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Digital Bus Switch Selection Guide (Rev. A) 10 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Bus FET Switch Solutions for Live Insertion Applications 07 Feb 2003

Design & development

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Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

User guide: PDF
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Simulation model

SN74CB3T3253 IBIS Model

SCDM058.ZIP (26 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 16 Ultra Librarian
SSOP (DBQ) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian
TVSOP (DGV) 16 Ultra Librarian
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