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SN74HCS10

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Triple 3-input NAND gates with Schmitt-trigger inputs

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Data sheet

SN74HCS10

ACTIVE
Data sheet Order now

Product details

Technology family HCS Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 3 Inputs per channel 3 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 130 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family HCS Supply voltage (min) (V) 2 Supply voltage (max) (V) 6 Number of channels 3 Inputs per channel 3 IOL (max) (mA) 7.8 IOH (max) (mA) -7.8 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10- 50ns) Data rate (max) (Mbps) 130 Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 5 V
  • Extended ambient temperature range: –40°C to +125°C, TA
  • Wide operating voltage range: 2 V to 6 V
  • Schmitt-trigger inputs allow for slow or noisy input signals
  • Low power consumption
    • Typical ICC of 100 nA
    • Typical input leakage current of ±100 nA
  • ±7.8-mA output drive at 5 V
  • Extended ambient temperature range: –40°C to +125°C, TA

This device contains three independent 3-input NAND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B ● C in positive logic.

This device contains three independent 3-input NAND Gates with Schmitt-trigger inputs. Each gate performs the Boolean function Y = A ● B ● C in positive logic.
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Technical documentation

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* Data sheet SN74HCS10 Triple 3-Input NAND Gates with Schmitt-Trigger Inputs datasheet (Rev. A) PDF | HTML 18 May 2020

Design & development

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Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

SN74HCS10 Behavioral SPICE Model

SCLM294.ZIP (8 KB) - PSpice Model
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Simulation model

SN74HCS10 IBIS Model

SCLM155.ZIP (250 KB) - IBIS Model
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Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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