The TPS7A89 is a dual, low-noise (3.8 µVRMS), low-dropout (LDO) voltage regulator capable of sourcing 2 A per channel with only 400 mV of maximum dropout.
The TPS7A89 provides the flexibility of two independent LDOs and approximately 60% smaller solution size than two single-channel LDOs. Each output is adjustable with external resistors from 0.8 V to 5.2 V. The wide input-voltage range of the TPS7A89 supports operation as low as 1.4 V and up to 6.5 V.
With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in-rush current, the TPS7A89 is ideal for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), high-end processors, and field-programmable gate arrays (FPGAs)].
The TPS7A89 is designed to power noise-sensitive components such as those found in high-speed communication, video, medical, or test and measurement applications. The very low 3.8-µVRMS output noise and wideband PSRR (40 dB at 1 MHz) minimizes phase noise and clock jitter. These features maximize the performance of clocking devices, ADCs, and DACs.
The TPS7A89 is a dual, low-noise (3.8 µVRMS), low-dropout (LDO) voltage regulator capable of sourcing 2 A per channel with only 400 mV of maximum dropout.
The TPS7A89 provides the flexibility of two independent LDOs and approximately 60% smaller solution size than two single-channel LDOs. Each output is adjustable with external resistors from 0.8 V to 5.2 V. The wide input-voltage range of the TPS7A89 supports operation as low as 1.4 V and up to 6.5 V.
With 1% output voltage accuracy (over line, load, and temperature) and soft-start capabilities to reduce in-rush current, the TPS7A89 is ideal for powering sensitive analog low-voltage devices [such as voltage-controlled oscillators (VCOs), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), high-end processors, and field-programmable gate arrays (FPGAs)].
The TPS7A89 is designed to power noise-sensitive components such as those found in high-speed communication, video, medical, or test and measurement applications. The very low 3.8-µVRMS output noise and wideband PSRR (40 dB at 1 MHz) minimizes phase noise and clock jitter. These features maximize the performance of clocking devices, ADCs, and DACs.