Product details

Function Clock generator Number of outputs 2 Output frequency (max) (MHz) 1175 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
Function Clock generator Number of outputs 2 Output frequency (max) (MHz) 1175 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVPECL Operating temperature range (°C) -40 to 85 Features Design tool available, Integrated EEPROM, Serial interface Rating Catalog
VQFN (RHB) 32 25 mm² 5 x 5
  • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter
  • Fully Configurable Outputs Including Frequency and Output Format
  • Smart Input Multiplexer Automatically Switches Between One of Two Reference Inputs
  • Multiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover Mode
  • Integrated EEPROM Determines Device Configuration at Power Up
  • Excellent Jitter Performance
  • Integrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:
    • Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode
    • Programmable Charge Pump Gain and Loop Filter Settings
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.
  • Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:
    • 0.5 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
    • Low Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHz
    • Output Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer Mode
    • LVPECL, LVDS, and LVCMOS
    • Independent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32
  • Flexible Inputs With Innovative Smart Multiplexer:
    • Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)
    • One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHz
    • Clock Generator Mode Using Crystal Input
    • Smart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe Operation
  • Typical Power Consumption 750 mW at 3.3 V
  • Integrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined State
  • Offered in QFN-32 Package
  • ESD Protection Exceeds 2000 V HBM
  • Industrial Temperature Range: –40°C to +85°C
  • APPLICATIONS
    • Data Converter and Data Aggregation Clocking
    • Wireless Infrastructure
    • Switches and Routers
    • Medical Electronics
    • Military and Aerospace
    • Industrial
    • Clock Generation and Jitter Cleaning


All other trademarks are the property of their respective owners

  • Frequency Synthesizer With PLL/VCO and Partially Integrated Loop Filter
  • Fully Configurable Outputs Including Frequency and Output Format
  • Smart Input Multiplexer Automatically Switches Between One of Two Reference Inputs
  • Multiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover Mode
  • Integrated EEPROM Determines Device Configuration at Power Up
  • Excellent Jitter Performance
  • Integrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:
    • Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner Mode
    • Programmable Charge Pump Gain and Loop Filter Settings
    • Unique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.
  • Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:
    • 0.5 ps RMS (10 kHz to 20 MHz) Output Jitter Performance
    • Low Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHz
    • Output Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer Mode
    • LVPECL, LVDS, and LVCMOS
    • Independent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32
  • Flexible Inputs With Innovative Smart Multiplexer:
    • Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)
    • One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHz
    • Clock Generator Mode Using Crystal Input
    • Smart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe Operation
  • Typical Power Consumption 750 mW at 3.3 V
  • Integrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined State
  • Offered in QFN-32 Package
  • ESD Protection Exceeds 2000 V HBM
  • Industrial Temperature Range: –40°C to +85°C
  • APPLICATIONS
    • Data Converter and Data Aggregation Clocking
    • Wireless Infrastructure
    • Switches and Routers
    • Medical Electronics
    • Military and Aerospace
    • Industrial
    • Clock Generation and Jitter Cleaning


All other trademarks are the property of their respective owners

The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS(1).

It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 10.94 MHz to 1.175 GHz(2)). If Both outputs are configured in single-ended mode (such as LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an external AT-Cut crystal through an onboard oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference through the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

(1) 10-kHz to 20-MHz integration bandwidth.
(2) Frequency range depends on operational mode and output format selected.

The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS(1).

It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 10.94 MHz to 1.175 GHz(2)). If Both outputs are configured in single-ended mode (such as LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an external AT-Cut crystal through an onboard oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference through the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available.

(1) 10-kHz to 20-MHz integration bandwidth.
(2) Frequency range depends on operational mode and output format selected.

Download View video with transcript Video

Similar products you might be interested in

open-in-new Compare alternates
Same functionality with different pin-out to the compared device
CDCM6208 ACTIVE 2:8 ultra-low power, low jitter clock generator Higher performance compared to CDCE62002

Technical documentation

star =Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 2
Type Title Date
* Data sheet CDCE62002 Four Output Clock Generator/Jitter Cleaner With Integrated Dual VCOs datasheet (Rev. E) PDF | HTML 09 Oct 2016
User guide Two/Four Output Low Noise Clock Evaluation Board 19 Jun 2009

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

CDCE62002EVM — CDCE62002 Evaluation Module

CDCE62002EVM is the evaluation module for CDCE62002. The CDCE62002 is a high performance clock generator featuring low output jitter, a high degree of configurability via a SPI interface, and programmable start up modes determined by on-chip EEPROM. The CDCE62002 achieves jitter performance under (...)

User guide: PDF
Not available on TI.com
GUI for evaluation module (EVM)

SCAC112 CDCE62002EVM GUI

Supported products & hardware

Supported products & hardware

Products
Clock generators
CDCE62002 Four output clock generator/jitter cleaner with integrated dual VCOs
Hardware development
Evaluation board
CDCE62002EVM CDCE62002 Evaluation Module
Download options
Simulation model

CDCE62002 IBIS Model

SCAM063.ZIP (68 KB) - IBIS Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins CAD symbols, footprints & 3D models
VQFN (RHB) 32 Ultra Librarian

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos