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CDCLVD110

NOT RECOMMENDED FOR NEW DESIGNS

1-to-10 LVDS clock buffer up to 900-MHz with minimum skew for clock distribution

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Data sheet
CDCLVD110 is not recommended for new designs
This product continues to be available for existing customers. New designs should consider an alternate product.
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Drop-in replacement with upgraded functionality to the compared device
CDCLVD110A ACTIVE 1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution Offers better jitter performance

CDCLVD110

NOT RECOMMENDED FOR NEW DESIGNS
Data sheet Order now

Product details

Function Differential Core supply voltage (V) 2.5 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVDS
Function Differential Core supply voltage (V) 2.5 Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVDS
  • Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
  • Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
  • VCC range 2.5 V ±5%
  • Typical Signaling Rate Capability of Up to 1.1 GHz
  • Configurable Register (SI/CK) Individually Enables Disables Outputs,
    Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
  • Full Rail-to-Rail Common-Mode Input Range
  • Receiver Input Threshold ±100 mV
  • Available in 32-Pin LQFP Package
  • Fail-Safe I/O-Pins for VDD = 0 V (Power Down)
  • Low-Output Skew <30 ps (Typical) for Clock-Distribution Applications
  • Distributes One Differential Clock Input to 10 LVDS Differential Clock Outputs
  • VCC range 2.5 V ±5%
  • Typical Signaling Rate Capability of Up to 1.1 GHz
  • Configurable Register (SI/CK) Individually Enables Disables Outputs,
    Selectable CLK0, CLK0 or CLK1, CLK1 Inputs
  • Full Rail-to-Rail Common-Mode Input Range
  • Receiver Input Threshold ±100 mV
  • Available in 32-Pin LQFP Package
  • Fail-Safe I/O-Pins for VDD = 0 V (Power Down)

The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50- transmission lines.

When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.

The CDCLVD110 is characterized for operation from -40°C to 85°C.

Not Recommended for New Designs. Use CDCLVD110A as a Replacement.

The CDCLVD110 clock driver distributes one pair of differential LVDS clock inputs (either CLK0 or CLK1) to 10 pairs of differential clock outputs (Q0, Q9) with minimum skew for clock distribution. The CDCLVD110 is specifically designed for driving 50- transmission lines.

When the control enable is high (EN = 1), the 10 differential outputs are programmable in that each output can be individually enabled/disabled (3-stated) according to the first 10 bits loaded into the shift register. Once the shift register is loaded, the last bit selects either CLK0 or CLK1 as the clock input. However, when EN = 0, the outputs are not programmable and all outputs are enabled.

The CDCLVD110 is characterized for operation from -40°C to 85°C.

Not Recommended for New Designs. Use CDCLVD110A as a Replacement.
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* Data sheet Programmable Low-Voltage 1:10 LVDS Clock Driver datasheet (Rev. C) 14 Jan 2008

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