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66AK2H06

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Hochleistungs-Multicore-DSP+Arm – 2x Arm A15-Kerne, 4x C66x-DSP-Kerne

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66AK2H06

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Produktdetails

Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1200, 1400 Coprocessors C66x DSP CPU 32-bit Protocols Ethernet Ethernet MAC 4-Port 1Gb switch PCIe 2 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Device identity, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1200, 1400 Coprocessors C66x DSP CPU 32-bit Protocols Ethernet Ethernet MAC 4-Port 1Gb switch PCIe 2 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Device identity, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (AAW) 1517 1600 mm² 40 x 40
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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Technische Dokumentation

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Typ Titel Datum
* Data sheet 66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G) PDF | HTML 09 Okt 2017
* Errata 66AK2Hxx Multicore DSP+ARM KeyStone II SOC Errata (Revs 1.0, 1.1, 2.0, 3.0, 3.1) (Rev. F) 05 Jun 2018
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 30 Mär 2023
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 30 Mär 2023
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 07 Jul 2022
Application note Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B) PDF | HTML 07 Sep 2021
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 25 Jun 2021
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 19 Mai 2021
Application note Implementing an FTP Server on TI 66AK2H Device With RTOS PDF | HTML 17 Aug 2020
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 11 Jun 2019
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 04 Jun 2019
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 03 Jun 2019
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 03 Jun 2019
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 17 Mai 2019
Application note KeyStone II DDR3 interface bring-up 07 Mär 2019
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 19 Nov 2018
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 19 Nov 2018
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 16 Jan 2018
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 16 Jan 2018
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 30 Sep 2017
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 30 Sep 2017
Application note Power Consumption Summary for 66AK2Hx System-on-Chip (SoC) Device Family 28 Sep 2017
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 21 Aug 2017
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 14 Aug 2017
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 26 Jul 2017
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 21 Jun 2017
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 21 Jun 2017
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 27 Jul 2016
Application note Power Management of KS2 Device (Rev. C) 15 Jul 2016
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 30 Apr 2016
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 30 Apr 2016
Application note SERDES Link Commissioning on KeyStone I and II Devices 13 Apr 2016
White paper Multicore SoCs stay a step ahead of SoC FPGAs 23 Feb 2016
Application note TI DSP Benchmarking 13 Jan 2016
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 22 Dez 2015
Application note Keystone II DDR3 Debug Guide 16 Okt 2015
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 06 Mai 2015
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 09 Apr 2015
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 27 Mär 2015
White paper TI’s processors leading the way in embedded analytics 03 Mär 2015
Application note Keystone II DDR3 Initialization 26 Jan 2015
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 05 Nov 2014
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 05 Nov 2014
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 04 Sep 2014
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) 03 Sep 2014
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 25 Aug 2014
Application note Hardware Design Guide for KeyStone II Devices 24 Mär 2014
Product overview 66AK2Hx KeyStone Multicore DSP+ARM System-on-chips (Rev. A) 08 Nov 2013
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 30 Sep 2013
User guide Debug and Trace for KeyStone II Devices User's Guide 26 Jul 2013
User guide ARM Bootloader User Guide for KeyStone II Devices 21 Jul 2013
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 15 Jul 2013
User guide Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D) 03 Jul 2013
User guide C66x CorePac User's Guide (Rev. C) 28 Jun 2013
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 28 Jun 2013
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 28 Mai 2013
User guide Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B) 05 Feb 2013
Product overview Multicore DSPs for High-Performance Video Coding 22 Jan 2013
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 12 Nov 2012
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 09 Nov 2012
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 09 Nov 2012
User guide ARM CorePac User Guide for KeyStone II Devices 31 Okt 2012
Application note Multicore Programming Guide (Rev. B) 29 Aug 2012
User guide Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A) 11 Jul 2012
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 30 Mär 2012
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 27 Mär 2012
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 22 Mär 2012
Application note PCIe Use Cases for KeyStone Devices 13 Dez 2011
Application note Introduction to TMS320C6000 DSP Optimization 06 Okt 2011
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 02 Sep 2011
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 24 Mai 2011
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 19 Mai 2011
User guide C66x CPU and Instruction Set Reference Guide 09 Nov 2010
User guide C66x DSP Cache User's Guide 09 Nov 2010
Application note Clocking Design Guide for KeyStone Devices 09 Nov 2010
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 09 Nov 2010
Application note Optimizing Loops on the C66x DSP 09 Nov 2010
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 09 Nov 2010
User guide Network Coprocessor for KeyStone Devices User's Guide 02 Nov 2010

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Debug-Tastkopf

TMDSEMU200-U — XDS200-USB-Debug-Tastkopf

Die XDS200 ist eine Debug-Sonde (Emulator) zum Debuggen von Embedded-Bausteinen von TI. Die XDS200 bietet ein ausgewogenes Preis-Leistungsverhältnis im Vergleich zum preiswerten XDS110 und dem leistungsstarken XDS560v2 und unterstützt zahlreiche Standards (IEEE1149,1, IEEE1149,7, SWD) in einem (...)

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Debug-Tastkopf

TMDSEMU560V2STM-U — XDS560v2 System-Trace-USB-Debug-Tastkopf

Der XDS560v2 ist die leistungsstärkste Debug-Sonde aus der XDS560™ Familie von Debug-Sonden und unterstützt sowohl den traditionellen JTAG-Standard (IEEE1149.1) als auch cJTAG (IEEE1149.7).  Bitte beachten: Diese Lösung unterstützt kein Serial Wire Debug (SWD).

Alle XDS-Debug-Tastköpfe unterstützen (...)

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Debug-Tastkopf

TMDSEMU560V2STM-UE — XDS560v2 System-Trace-USB-und Ethernet-Debug-Tastkopf

The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors that (...)

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Software-Entwicklungskit (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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66AK2E05 — Hochleistungs-Multicore DSP+Arm – 4x Arm A15-Kerne, 1x C66x DSP-Kern, NetCP, 10 GbE 66AK2H06 — Hochleistungs-Multicore-DSP+Arm – 2x Arm A15-Kerne, 4x C66x-DSP-Kerne 66AK2H12 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x-DSP-Kerne 66AK2H14 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x DSP-Kerne, 10 GbE AM5K2E02 — Sitara-Prozessor: Dual-Arm Cortex-A15 AM5K2E04 — Sitara-Prozessor: Vierfach-Arm Cortex-A15
Digitale Signalprozessoren (DSPs)
66AK2L06 — System-on-Chip (SoC) mit Multicore-DSP + ARM KeyStone II
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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-K2HK — Linux Processor SDK for K2H

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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ARM-basierte Prozessoren
66AK2H06 — Hochleistungs-Multicore-DSP+Arm – 2x Arm A15-Kerne, 4x C66x-DSP-Kerne 66AK2H12 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x-DSP-Kerne 66AK2H14 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x DSP-Kerne, 10 GbE
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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-RT-K2HK — Linux-RT Processor SDK for K2H

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

Unterstützte Produkte und Hardware

Unterstützte Produkte und Hardware

Produkte
ARM-basierte Prozessoren
66AK2H06 — Hochleistungs-Multicore-DSP+Arm – 2x Arm A15-Kerne, 4x C66x-DSP-Kerne 66AK2H12 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x-DSP-Kerne 66AK2H14 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x DSP-Kerne, 10 GbE
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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-K2HK — RTOS Processor SDK for K2H

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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Produkte
ARM-basierte Prozessoren
66AK2H06 — Hochleistungs-Multicore-DSP+Arm – 2x Arm A15-Kerne, 4x C66x-DSP-Kerne 66AK2H12 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x-DSP-Kerne 66AK2H14 — Hochleistungs-Multicore-DSP+Arm – 4x Arm A15-Kerne, 8x C66x DSP-Kerne, 10 GbE
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Treiber oder Bibliothek

FFTLIB — FFT-Bibliothek für Fließkomma-Bausteine

The Texas Instruments FFT library is an optimized floating-point math function library for computing the discrete Fourier transform (DFT).
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Treiber oder Bibliothek

MATHLIB — DSP-Mathematikbibliothek für Fließkommabausteine

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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Treiber oder Bibliothek

SPRC264 — TMS320C5000/6000-Bildbibliothek (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Benutzerhandbuch: PDF
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Treiber oder Bibliothek

SPRC265 — TMS320C6000-DSP-Bibliothek (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
Benutzerhandbuch: PDF
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IDE, Konfiguration, Compiler oder Debugger

CCSTUDIO — Code Composer Studio integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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Software-Codec

C66XCODECS — CODECS – Video, Sprache – für C66x-basierte Geräte

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
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Simulationsmodell

66AK2H06 Power Consumption Model (Rev. A)

SPRM649A.ZIP (136 KB) - Power Model
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Simulationsmodell

66AK2H12 66AK2H06 AAW BSDL Model

SPRM609.ZIP (36 KB) - BSDL Model
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Simulationsmodell

66AK2H12 66AK2H06 AAW IBIS Model

SPRM618.ZIP (2189 KB) - IBIS Model
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Simulationsmodell

66AK2Hx FloTherm Model

SPRM603.ZIP (6 KB) - Power Model
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Simulationsmodell

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
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Schaltplan

66AK2H14 66AK2H12 66AK2H106 AAW OrCAD Symbols

SPRR189.ZIP (144 KB)
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Referenzdesigns

TIDEP0045 — Referenzdesign zur Implementierung eines Echtzeit-SAR-Algorithmus (Synthetic Aperture Radar) auf dem

This reference design shows a real-time synthetic aperture radar (SAR) running on a multicore TMS320C6678 digital signal processor (DSP). One of the main challenges of  SAR is to generate high-resolution images in real-time, since forming the image involves computationally-demanding signal (...)
Design guide: PDF
Schaltplan: PDF
Referenzdesigns

TIDEP0037 — Verwendung des TMS320C6678-Prozessors zur Implementierung einer energieeffizienten skalierbaren H.26

HEVC is an efficient, but processing intensive video standard, that is said to double the data compression ratio compared to H.264 / MPEG-4 at the same level of video quality. This design shows how a power efficient, soft H.265 / HEVC solution, that scales across resolutions, frame rates & (...)
Design guide: PDF
Schaltplan: PDF
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