SN74AUP1G80

ACTIVO

Biestable único de tipo D con activación de borde positivo de baja potencia

Detalles del producto

Number of channels 1 Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 260 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 1 Technology family AUP Supply voltage (min) (V) 0.8 Supply voltage (max) (V) 3.6 Input type Standard CMOS Output type Push-Pull Clock frequency (max) (MHz) 260 IOL (max) (mA) 4 IOH (max) (mA) -4 Supply current (max) (µA) 0.9 Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
DSBGA (YFP) 6 1.4000000000000001 mm² 1 x 1.4000000000000001 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DPW) 5 0.64 mm² 0.8 x 0.8 X2SON (DSF) 6 1 mm² 1 x 1
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoStar™ Package
  • Low Static-Power Consumption
    (ICC = 0.9 µA Maximum)
  • Low Dynamic-Power Consumption
    (Cpd = 4.3 pF Typical at 3.3 V)
  • Low Input Capacitance (Ci = 1.5 pF Typical)
  • Low Noise – Overshoot and Undershoot <10% of VCC
  • Ioff Supports Partial-Power-Down Mode Operation
  • Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input
    (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • tpd = 4.4 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family assures a low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see AUP – The Lowest-Power Family). This product also maintains excellent signal integrity (see Excellent Signal Integrity).

This is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.

Descargar Ver vídeo con transcripción Video

Productos similares que pueden interesarle

open-in-new Comparar alternativas
Reemplazo con funcionalidad mejorada del dispositivo comparado
SN74LVC1G74 ACTIVO Biestable único de tipo D con activación de borde positivo con opciones de eliminación y preajuste Larger voltage range (1.65V to 5.5V), higher drive average drive strength (24mA)
Pin por pin con la misma funcionalidad que el dispositivo comparado
SN74LVC1G80 ACTIVO Biestable único de tipo D con activación de borde positivo Larger voltage range (1.65V to 5.5V), higher drive average drive strength (24mA)

Documentación técnica

star =Principal documentación para este producto seleccionada por TI
No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.
Ver todo 8
Tipo Título Fecha
* Data sheet SN74AUP1G80 Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop datasheet (Rev. F) PDF | HTML 20 jul 2017
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML 15 dic 2022
Application brief Understanding Schmitt Triggers (Rev. A) PDF | HTML 22 may 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Application note Designing and Manufacturing with TI's X2SON Packages 23 ago 2017
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
Modelo de simulación

SN74AUP1G80 IBIS Model (Rev. B)

SCEM444B.ZIP (64 KB) - IBIS Model
Diseños de referencia

TIDA-01056 — Diseño de referencia DAQ de 1 MSPS de 20 bits que optimiza la eficiencia de la fuente de alimentació

This reference design for high performance data acquisition (DAQ) systems optimizes power stage in order to reduce power consumption and minimize the effect of EMI from switching regulator by using LMS3635-Q1 buck converter.  This reference designs yields 7.2% efficiency improvement at most (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01054 — Diseño de referencia de potencia multicarril para eliminar los efectos EMI en sistemas DAQ de alto r

The TIDA-01054 reference design helps eliminate the performance degrading effects of EMI on Data Acquisition (DAQ) systems greater than 16 bits with the help of the LM53635 buck converter. The buck converter enables the designer to place power solutions close to the signal path without the (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01055 — Diseño de referencia de optimización de búfer de referencia de tensión ADC para sistemas DAQ de alto

The TIDA-01055 reference design for high performance DAQ Systems optimizes the ADC reference buffer to improve SNR performance and reduce power consumption with the TI OPA837 high-speed op amp. This device is used in a composite buffer configuration and provides a 22% power improvement over (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01057 — Diseño de referencia que maximiza el rango dinámico de señal para entrada diferencial real de 10 Vpp

This reference design is designed for high performance data acquisition(DAQ) systems to improve the dynamic range of 20 bit differential input ADCs. Many DAQ systems require the measurement capability at a wide FSR (Full Scale Range) in order to obtain sufficient signal dynamic range. Many earlier (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01051 — Diseño de referencia que optimiza la utilización de FPGA y la producción de datos para equipos de pr

The TIDA-01051 reference design is used to demonstrate optimized channel density, integration, power consumption, clock distribution and signal chain performance of very high channel count data acquisition (DAQ) systems such as those used in automatic test equipment (ATE). Using serializers, such (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01050 — Diseño de referencia del sistema DAQ de interfaz analógica optimizado para convertidores de datos SA

The TIDA-01050 reference design aims to improve the integration, power consumption, performance, and clocking issues typically associated with automatic test equipment. This design is applicable to any ATE system but most applicable to systems requiring a large number of input channels.
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01052 — Diseño de referencia de controlador ADC que mejora la THD a escala completa mediante alimentación ne

The TIDA-01052 reference design aims to highlight system performance increases seen using a negative voltage rail on the analog front end driver amplifiers rather than ground. This concept is relative to all analog front ends, however this design is aimed specifically at automatic test equipment.
Design guide: PDF
Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
DSBGA (YFP) 6 Ultra Librarian
SOT-23 (DBV) 5 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DPW) 5 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.

Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI. ​​​​​​​​​​​​​​

Videos