TLC3574

ACTIVO

14 bits, salida en serie, baja potencia con reloj de conversión integrado y FIFO por 8, 4 canales

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document-pdfAcrobat 5-V Analog, 3-/5-V Digital, 14-/12-Bit, 200-KSPS, 4-/8-Channel Serial Analog-to- datasheet (Rev. C) (Inglés)

TLC3574

ACTIVO

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Detalles del producto

Resolution (Bits)

14

Sample rate (max) (ksps)

200

Number of input channels

4

Interface type

SPI

Architecture

SAR

Input type

Pseudo-Differential, Single-ended

Multichannel configuration

Multiplexed

Rating

Catalog

Reference mode

External

Input voltage range (max) (V)

10

Input voltage range (min) (V)

-10

Features

Oscillator

Operating temperature range (°C)

-40 to 85

Power consumption (typ) (mW)

29

Analog supply (min) (V)

4.75

Analog supply voltage (max) (V)

5.5

SNR (dB)

80

Digital supply (min) (V)

2.7

Digital supply (max) (V)

5.5

Resolution (Bits)

14

Sample rate (max) (ksps)

200

Number of input channels

4

Interface type

SPI

Architecture

SAR

Input type

Pseudo-Differential, Single-ended

Multichannel configuration

Multiplexed

Rating

Catalog

Reference mode

External

Input voltage range (max) (V)

10

Input voltage range (min) (V)

-10

Features

Oscillator

Operating temperature range (°C)

-40 to 85

Power consumption (typ) (mW)

29

Analog supply (min) (V)

4.75

Analog supply voltage (max) (V)

5.5

SNR (dB)

80

Digital supply (min) (V)

2.7

Digital supply (max) (V)

5.5

SOIC (DW)

20

131.84 mm² 12.8 x 10.3

TSSOP (PW)

20

41.6 mm² 6.5 x 6.4

14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578
Maximum Throughput 200-KSPS
Multiple Analog Inputs:
- 8 Single-Ended Channels for TLC3578/2578
- 4 Single-Ended Channels for TLC3574/2574
Analog Input Range: ±10 V
Pseudodifferential Analog Inputs
SPI/DSP-Compatible Serial Interfaces With SCLK up to 25-MHz
Built-In Conversion Clock and 8x FIFO
Single 5-V Analog Supply; 3-/5-V Digital Supply
Low-Power
- 5.8 mA in Normal Operation
- 20 µA in Power Down
Programmable Autochannel Sweep and Repeat
Hardware-Controlled, Programmable Sampling Period
Hardware Default Configuration
INL: TLC3574/78: ±1 LSB;
TLC2574/78: ±0.5 LSB
DNL: TLC3574/78: ±0.5 LSB;
TLC2574/78: ±0.5 LSB
SINAD: TLC3574/78: 79 dB;
TLC2574/78: 72 dB
THD: TLC3574/78: –82 dB;
TLC2574/78: –82 dB

Note: Recommended Voltage Reference: REF02 and REF102

14-Bit Resolution for TLC3574/78, 12-Bit for TLC2574/2578
Maximum Throughput 200-KSPS
Multiple Analog Inputs:
- 8 Single-Ended Channels for TLC3578/2578
- 4 Single-Ended Channels for TLC3574/2574
Analog Input Range: ±10 V
Pseudodifferential Analog Inputs
SPI/DSP-Compatible Serial Interfaces With SCLK up to 25-MHz
Built-In Conversion Clock and 8x FIFO
Single 5-V Analog Supply; 3-/5-V Digital Supply
Low-Power
- 5.8 mA in Normal Operation
- 20 µA in Power Down
Programmable Autochannel Sweep and Repeat
Hardware-Controlled, Programmable Sampling Period
Hardware Default Configuration
INL: TLC3574/78: ±1 LSB;
TLC2574/78: ±0.5 LSB
DNL: TLC3574/78: ±0.5 LSB;
TLC2574/78: ±0.5 LSB
SINAD: TLC3574/78: 79 dB;
TLC2574/78: 72 dB
THD: TLC3574/78: –82 dB;
TLC2574/78: –82 dB

Note: Recommended Voltage Reference: REF02 and REF102

The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter. CS\ can be tied to ground if only one converter is used. FS must be tied to DV_DD if it is not used (such as in an SPI interface). When SDI is tied to DV_DD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS\ or FS) are needed to interface with the host.

In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin, CSTART\, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are designed to operate with low-power consumption. The power saving feature is further enhanced with autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78 and TLC2574/78 are specified with bipolar input and a full scale range of ±10 V.

The TLC3574, TLC3578, TLC2574, and TLC2578 are a family of high-performance, low-power, CMOS analog-to-digital converters (ADC). TLC3574/78 is a 14-bit ADC; TLC2574/78 is a 12-bit ADC. All parts operate from single 5-V analog power supply and 3-V to 5-V digital supply. The serial interface consists of four digital input [chip select (CS\), frame sync (FS), serial input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS\ (works as SS\, slave select), SDI, SDO and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form DSP interface. The frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters connect to one serial port of a DSP, CS\ works as the chip select to allow the host DSP to access the individual converter. CS\ can be tied to ground if only one converter is used. FS must be tied to DV_DD if it is not used (such as in an SPI interface). When SDI is tied to DV_DD, the device is set in hardware default mode after power on and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS\ or FS) are needed to interface with the host.

In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold function is automatically started after the fourth SCLK (normal sampling) or can be controlled by a special pin, CSTART\, to extend the sampling period (extended sampling). The normal sampling period can also be programmed as short sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among high-performance signal processors. The TLC3574/78 and TLC2574/78 are designed to operate with low-power consumption. The power saving feature is further enhanced with autopower-down mode and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3574/78 and TLC2574/78 are specified with bipolar input and a full scale range of ±10 V.

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