PCM5102-Q1
オートモーティブ・カタログ、112dB ステレオ DAC、2VRMS 出力およびオーディオ PLL 内蔵
比較対象デバイスと類似の機能
PCM5102-Q1
- Qualified for Automotive Applications
- AEC-Q100 Qualified With the Following Results:
- Device Temperature Grade 2: –40°C to 105°C Ambient
Operating Temperature Range - Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C3B
- Device Temperature Grade 2: –40°C to 105°C Ambient
- Market-Leading Low Out-of-Band Noise
- Selectable Digital-Filter Latency and Performance
- No DC Blocking Capacitors Required
- Integrated Negative Charge Pump
- Internal Pop-Free Control For Sample-Rate Changes or Clock Halts
- Intelligent Muting System; Soft Up/Down Ramp
and Analog Mute For 120-dB Mute SNR With Popless Operation. - Integrated High-Performance Audio PLL With BCK Reference to
Generate SCK Internally - Small 20-pin TSSOP Package
Other Key Features
- Accepts 16-, 24-, and 32-Bit Audio Data
- PCM Data Formats: I2S, Left-Justified
- Automatic Power-Save Mode When LRCK And BCK Are Deactivated
- 3.3-V Failsafe LVCMOS Digital Inputs
- Hardware Configuration
- Single-Supply Operation:
- 3.3-V Analog, 3.3-V Digital
- Integrated Power-On Reset
The PCM510x-Q1 family is a series of monolithic CMOS integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510x-Q1 uses the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.
The PCM510x-Q1 provides 2.1-VRMS ground-centered outputs, allowing designers to eliminate not only dc blocking capacitors on the output, but also external muting circuits traditionally associated with single-supply line drivers.
The integrated line driver surpasses all other charge-pump-based line drivers by supporting loads down to 1 kΩ. By supporting loads down to 1 k&3937;, the PCM510x-Q1 can essentially drive up to 10 products in parallel (LCD TV, DVDR, AV receivers, and so on).
The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock). This allows a three-wire I2S connection, along with reduced system EMI.
Intelligent clock error and PowerSense undervoltage protection uses a two-level mute system for pop-free performance. On clock error or system power failure, the device digitally attenuates the data (or last known-good data), then mutes the analog circuit
Compared with existing DAC technology, the PCM510x-Q1 offers up to 20-dB lower out-of-band (OBN) noise, reducing EMI and aliasing in downstream amplifiers/ADCs. (from traditional 100-kHz OBN measurements all the way to 3 MHz)
The PCM510x-Q1 accepts industry-standard audio data formats with 16- to 32-bit data and supports sSample rates up to 384 kHz.
技術資料
種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
---|---|---|---|---|---|---|
* | データシート | 2Vrms DirectPath,112/106/100dB Audio Stereo DAC with 32-bit, 384kHz PCM IF データシート (Rev. C) | 2013年 4月 12日 |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点