SN74ABT16601
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
- Flow-Through Architecture Optimizes PCB Layout
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
Widebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.
These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, clocked, and clock-enabled modes.
Data flow in each direction is controlled by output-enable ( and
), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by
the clock-enable (
and
) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high. When LEAB
is low, the A data is latched if CLKAB is held at a high or low logic
level. If LEAB is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. Output enable
is active low. When
is low, the outputs are active.
When
is high, the
outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses , LEBA, CLKBA, and
.
To ensure the high-impedance state during power up or power down,
should be tied
to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the
driver.
The SN54ABT16601 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16601 is characterized for operation from -40°C to 85°C.
技術資料
設計および開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
---|---|---|
SSOP (DL) | 56 | Ultra Librarian |
TSSOP (DGG) | 56 | Ultra Librarian |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点