製品詳細

Configuration 1:1 SPST Number of channels 24 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 5 CON (typ) (pF) 13 ON-state leakage current (max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 1:1 SPST Number of channels 24 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 5 CON (typ) (pF) 13 ON-state leakage current (max) (µA) 20 Bandwidth (MHz) 100 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Signal path translation Input/output continuous current (max) (mA) 128 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
SSOP (DL) 56 190.647 mm² 18.42 x 10.35 TSSOP (DGG) 56 113.4 mm² 14 x 8.1 TVSOP (DGV) 56 72.32 mm² 11.3 x 6.4
  • Member of the Texas Instruments Widebus Family
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on
    All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level
      Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output
      Level Shift With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered Up
    or Powered Down
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low ON-State Resistance (ron) Characteristics
    (ron = 5 Ω Typ)
  • Low Input/Output Capacitance Minimizes
    Loading (Cio(OFF) = 5 pF Typ)
  • Data and Control Inputs Provide
    Undershoot Clamp Diodes
  • Low Power Consumption
    (ICC = 70 µA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL
    or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications: Level
    Translation, PCI Interface, Bus Isolation
  • Ideal for Low-Power Portable Equipment

  • Member of the Texas Instruments Widebus Family
  • Output Voltage Translation Tracks VCC
  • Supports Mixed-Mode Signal Operation on
    All Data I/O Ports
    • 5-V Input Down to 3.3-V Output Level
      Shift With 3.3-V VCC
    • 5-V/3.3-V Input Down to 2.5-V Output
      Level Shift With 2.5-V VCC
  • 5-V Tolerant I/Os With Device Powered Up
    or Powered Down
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low ON-State Resistance (ron) Characteristics
    (ron = 5 Ω Typ)
  • Low Input/Output Capacitance Minimizes
    Loading (Cio(OFF) = 5 pF Typ)
  • Data and Control Inputs Provide
    Undershoot Clamp Diodes
  • Low Power Consumption
    (ICC = 70 µA Max)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0- to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL
    or 5-V/3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Digital Applications: Level
    Translation, PCI Interface, Bus Isolation
  • Ideal for Low-Power Portable Equipment

The SN74CB3T16211 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16211 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels.

The I/O port of this device has a pullup current source that maintains the output voltage at VCC when the device is ON, and the input is greater than or equal to VCC – 1. Because of the pullup current source, the output voltage level may be less than VCC when the operating frequency is low and the I/O port is connected to a pulldown resistor. In order to maintain the output voltage at VCC, a pullup resistor must be connected to VCC instead of a pulldown resistor to ground.

The SN74CB3T16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3T16211 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (ron), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O ports by providing voltage translation that tracks VCC. The SN74CB3T16211 supports systems using 5-V TTL, 3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels.

The I/O port of this device has a pullup current source that maintains the output voltage at VCC when the device is ON, and the input is greater than or equal to VCC – 1. Because of the pullup current source, the output voltage level may be less than VCC when the operating frequency is low and the I/O port is connected to a pulldown resistor. In order to maintain the output voltage at VCC, a pullup resistor must be connected to VCC instead of a pulldown resistor to ground.

The SN74CB3T16211 is organized as two 12-bit bus switches with separate output-enable (1OE, 2OE) inputs. It can be used as two 12-bit bus switches or as one 24-bit bus switch. When OE is low, the associated 12-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 12-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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技術資料

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート SN74CB3T16211 データシート (Rev. C) 2012年 8月 17日
アプリケーション・ノート Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
アプリケーション・ノート Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
アプリケーション・ノート CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. C) PDF | HTML 2021年 11月 19日
アプリケーション概要 Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021年 1月 6日
セレクション・ガイド Logic Guide (Rev. AB) 2017年 6月 12日
アプリケーション・ノート How to Select Little Logic (Rev. A) 2016年 7月 26日
アプリケーション・ノート Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
セレクション・ガイド ロジック・ガイド (Rev. AA 翻訳版) 最新英語版 (Rev.AB) 2014年 11月 6日
ユーザー・ガイド LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
その他の技術資料 Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
アプリケーション・ノート Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
アプリケーション・ノート Selecting the Right Level Translation Solution (Rev. A) 2004年 6月 22日
ユーザー・ガイド Signal Switch Data Book (Rev. A) 2003年 11月 14日
アプリケーション・ノート Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

シミュレーション・モデル

HSPICE Model for SN74CB3T16211

SCDJ036.ZIP (118 KB) - HSpice Model
シミュレーション・モデル

SN74CB3T16211 IBIS Model

SCDM096.ZIP (28 KB) - IBIS Model
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
SSOP (DL) 56 Ultra Librarian
TSSOP (DGG) 56 Ultra Librarian
TVSOP (DGV) 56 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

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