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SN54ABT18245A

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Scan Test Devices With 18-Bit Bus Transceivers

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Data sheet

SN54ABT18245A

ACTIVE
Data sheet Order now

Product details

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -24 Input type TTL-Compatible CMOS Output type 3-State Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family ABT Rating Military Operating temperature range (°C) -55 to 125
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 18 IOL (max) (mA) 64 IOH (max) (mA) -24 Input type TTL-Compatible CMOS Output type 3-State Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family ABT Rating Military Operating temperature range (°C) -55 to 125
CFP (WD) 56 177.9372 mm² 18.42 x 9.66
  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Members of the Texas Instruments WidebusTM Family
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • SCOPETM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions, CLAMP and HIGHZ
    • Parallel-Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Device Identification
    • Even-Parity Opcodes
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages

SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Members of the Texas Instruments WidebusTM Family
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • SCOPETM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions, CLAMP and HIGHZ
    • Parallel-Signature Analysis at Inputs
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Device Identification
    • Even-Parity Opcodes
  • State-of-the-Art EPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages

SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPETM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE\) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE\ can be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18245A is characterized for operation from -40°C to 85°C.

The 'ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPETM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE\) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE\ can be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPETM bus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18245A is characterized for operation from -40°C to 85°C.

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Technical documentation

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Type Title Date
* Data sheet Scan Test Devices With 18-Bit Bus Transceivers datasheet (Rev. H) 19 Feb 1999
* SMD SN54ABT18245A SMD 5962-94601 21 Jun 2016
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 16 Feb 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 01 Mar 1997
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

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Simulation model

BSDL Model of SN74ABT18245A

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