The ´BCT620A bus transceiver is designed for asynchronous communication between data buses. The control function implementation allows for maximum flexibility in timing. The ´BCT620A provides inverted data at its outputs.
These devices allow data transmission from the A bus to the B bus
or from the B bus to the A bus depending upon the logic levels at the
output-enable (OEAB and 
)
inputs.
The output-enable inputs can be used to disable the device so that
the buses are effectively isolated. The dual-enable configuration
gives the transceivers the capability of storing data by
simultaneously enabling OEAB and . When both OEAB and are enabled and all other data sources to the two sets
of bus lines are at high impedance, both sets of bus lines (16 in
all) will remain at their last states. In this way, each output
reinforces its input in this configuration.
The SN54BCT620A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74BCT620A is characterized for operation from 0°C to 70°C.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | Octal Bus Transceivers With 3-State Outputs datasheet (Rev. B) | 01 Nov 1993 | |
| * | SMD | SN54BCT620A SMD 5962-90750 | 21 Jun 2016 | |
| Application note | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| Application note | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| Application note | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| Application note | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| Application note | Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) | 01 Aug 1997 | ||
| Application note | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| Application note | Input and Output Characteristics of Digital Integrated Circuits | 01 Oct 1996 | ||
| Application note | Live Insertion | 01 Oct 1996 |
For additional terms or required resources, click any title below to view the detail page where available.
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| CDIP (J) | 20 | Ultra Librarian |
| LCCC (FK) | 20 | Ultra Librarian |
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