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SN74LV132A

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4-ch, 4-input, 2-V to 5.5-V NAND gates with Schmitt-Trigger inputs

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Data sheet

SN74LV132A

ACTIVE
Data sheet Order now

Product details

Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10- 50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LV-A Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 4 Inputs per channel 4 IOL (max) (mA) 12 IOH (max) (mA) -12 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10- 50ns), Over-voltage tolerant inputs, Partial power down (Ioff) Data rate (max) (Mbps) 70 Rating Catalog Operating temperature range (°C) -40 to 125
SOIC (D) 14 51.9 mm² 8.65 x 6 SOP (NS) 14 79.56 mm² 10.2 x 7.8 SSOP (DB) 14 48.36 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23.04 mm² 3.6 x 6.4
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 9 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Latch-Up Performance Exceeds 250 mA per
    JESD 17
  • Ioff Supports Live Insertion, Partial Power-Down
    Mode, and Back Drive Protection
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Industrial PC: Rugged PC and Laptop
    • Access Control and Security: Camera
      Surveillance IP Network
    • Vending, Payment and Change Machines
    • Patient Monitoring STB / DVR / Streaming Media
      (Withdraw)
    • Other Motor Drives (Such as Switch Reluctance)

All other trademarks are the property of their respective owners
  • 2-V to 5.5-V VCC Operation
  • Max tpd of 9 ns at 5 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at
    VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2.3 V at
    VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on All
    Ports
  • Latch-Up Performance Exceeds 250 mA per
    JESD 17
  • Ioff Supports Live Insertion, Partial Power-Down
    Mode, and Back Drive Protection
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • APPLICATIONS
    • Industrial PC: Rugged PC and Laptop
    • Access Control and Security: Camera
      Surveillance IP Network
    • Vending, Payment and Change Machines
    • Patient Monitoring STB / DVR / Streaming Media
      (Withdraw)
    • Other Motor Drives (Such as Switch Reluctance)

All other trademarks are the property of their respective owners

The ’LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.

The ’LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

The ’LV132A devices are quadruple positive-NAND gates designed for 2-V to 5.5-V VCC operation.

The ’LV132A devices perform the Boolean function Y = A • B or Y = A + B in positive logic.

Each circuit functions as a NAND gate, but because of the Schmitt trigger, it has different input threshold levels for positive- and negative-going signals.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean jitter-free output signals.
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Technical documentation

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* Data sheet SNx4LV132A Quadruple Positive-NAND Gates With Schmitt-Trigger Inputs datasheet (Rev. J) PDF | HTML 20 Feb 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Logic product generic evaluation module for 14-pin to 24-pin D, DB, DGV, DW, DYY, NS and PW packages

The 14-24-LOGIC-EVM evaluation module (EVM) is designed to support any logic device that is in a 14-pin to 24-pin D, DW, DB, NS, PW, DYY or DGV package,

User guide: PDF | HTML
Not available on TI.com
Simulation model

HSPICE Model for SN74LV132A

SCEJ153.ZIP (51 KB) - HSpice Model
Download
Simulation model

SN74LV132A Behavioral SPICE Model

SCLM188.ZIP (7 KB) - PSpice Model
Download
Simulation model

SN74LV132A IBIS Model (Rev. A)

SCEM128A.ZIP (36 KB) - IBIS Model
Download
Package Pins CAD symbols, footprints & 3D models
SOIC (D) 14 Ultra Librarian
SOP (NS) 14 Ultra Librarian
SSOP (DB) 14 Ultra Librarian
TSSOP (PW) 14 Ultra Librarian
TVSOP (DGV) 14 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

Ordering & quality

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  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

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