Calculation tool
UCC5350
3kVrms, 5A/5A single-channel isolated gate driver with miller clamp or split out & 8V or 12V UVLO
Data sheet
UCC5350
- Feature options
- Split outputs (UCC53x0S)
- UVLO referenced to GND2 (UCC53x0E)
- Miller clamp option (UCC53x0M)
- 8-pin D (4mm creepage) and DWV (8.5mm creepage) package
- 60ns (typical) propagation delay
- 100kV/µs minimum CMTI
- Isolation barrier life > 40 Years
- 3V to 15V input supply voltage
- Up to 33V driver supply voltage
- 8V and 12V UVLO options
- Negative 5V handling capability on input pins
- Safety-related certifications:
- 7000VPK isolation DWV (planned) and 4242VPK isolation D per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
- 5000VRMS DWV and 3000VRMS D isolation rating for 1 minute per UL 1577
- CQC certification per GB4943.1-2011 D and DWV (planned)
- CMOS inputs
- Operating temperature: –40°C to +125°C
The UCC53x0 is a family of single-channel, isolated gate drivers designed to drive MOSFETs, IGBTs, SiC MOSFETs, and GaN FETs (UCC5350SBD). The UCC53x0S provides a split output that controls the rise and fall times individually. The UCC53x0M connects the gate of the transistor to an internal clamp to prevent false turn-on caused by Miller current. The UCC53x0E has its UVLO2 referenced to GND2 to get a true UVLO reading.
The UCC53x0 is available in a 4mm SOIC-8 (D) or 8.5mm SOIC-8 (DWV) package and can support isolation voltage up to 3kVRMS and 5kVRMS, respectively. With these various options the UCC53x0 family is a good fit for motor drives and industrial power supplies.
Compared to an optocoupler, the UCC53x0 family has lower part-to-part skew, lower propagation delay, higher operating temperature, and higher CMTI.
Technical documentation
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Evaluation board
UCC5320SCEVM-058 — UCC5320SC isolated gate driver evaluation module
UCC5320SCEVM is an Evaluation Module used to evaluate UCC53xx family of devices and it provides user with flexiblity of configuring driver to Split output, miller clamp or UVLO based on the device used . The EVM features enough test points & jumper options for one to evaluate the device (...)
User guide: PDF
Simulation model
UCC5350MCD Unencrypted PSpice Transient Model (Rev. A)
SLLM367A.ZIP (3 KB) - PSpice Model
Simulation tool
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs
TIDA-010257 — 10kW Vienna rectifier-based, three-phase power factor correction reference design
The Vienna rectifier power topology is used in high-power, three-phase power factor correction applications such as appliances, electric vehicle (EV) chargers, and telecom rectifiers. Control design of the rectifier can be complex. This reference design illustrates a method to control the power (...)
Design guide: PDF
Reference designs
PMP23126 — 3-kW phase-shifted full bridge with active clamp reference design with > 270-W/in3 power density
This reference design is a GaN-based 3-kW phase-shifted full bridge (PSFB) targeting maximum power density. The design has an active clamp to minimize voltage stress on the secondary synchronous rectifier MOSFETs enabling use of lower voltage-rating MOSFETs with better figure-of-merit (FoM). (...)
Test report: PDF
Reference designs
PMP23331 — 19-W, AC/DC multioutput 5-V and 12-V ZVS flyback reference design for server applications
This reference design converts a universal AC input to an isolated 12-V, 1.5-A output and an isolated 5-V, 0.2-A output. The design achieves a peak efficiency of 92.7%. This reference design features UCC28781-Q1 which is a zero-voltage switching (ZVS) flyback controller to minimize switching (...)
Test report: PDF
Reference designs
TIDA-01599 — TÜV SÜD-assessed safe torque off (STO) reference design for industrial drives (IEC 61800-5-2)
This reference design outlines a safe torque off (STO) subsystem for a three-phase inverter with CMOS input isolated IGBT gate drivers. The STO subsystem employs a dual-channel architecture (1oo2) with a hardware fault tolerance of 1 (HFT=1). It is implemented following a de-energize trip concept. (...)
Reference designs
PMP23224 — 220-W active-clamp flyback battery charger reference design
This reference design is a 220-W, active clamp flyback battery charger design with power factor correction (PFC) front end. This design takes a universal AC input of 90 V to 264 V and charges a battery with a VOUT range of 6-V to 22-V.
Test report: PDF
Reference designs
TIDA-01420 — Basic Isolated Three-Phase Compact Power Stage Reference Design for Industrial Drives
This three-phase, compact power stage reference design for industrial drives, which uses a UCC53xx gate driver to support basic capacitive isolation requirements, provides an increased lifespan and better propagation delay match over optocouplers to minimize inverter deadband distortions and (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| SOIC (D) | 8 | Ultra Librarian |
| SOIC (DWV) | 8 | Ultra Librarian |
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