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微控制器 (MCU) 與處理器
Arm 式處理器

66AK2H06

現行

高效能多核心 DSP+Arm - 2x Arm A15 核心、4x C66x DSP 核心

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66AK2H06

現行
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產品詳細資料

Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1200, 1400 Coprocessors C66x DSP CPU 32-bit Protocols Ethernet Ethernet MAC 4-Port 1Gb switch PCIe 2 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Device identity, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
Arm CPU 2 Arm Cortex-A15 Arm (max) (MHz) 1200, 1400 Coprocessors C66x DSP CPU 32-bit Protocols Ethernet Ethernet MAC 4-Port 1Gb switch PCIe 2 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Security Cryptography, Device identity, Secure boot Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (AAW) 1517 1600 mm² 40 x 40
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC
  • Eight TMS320C66x DSP Core Subsystems (C66x CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed- and Floating-Point DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2 GHz
    • Memory
      • 32-KB L1P Per CorePac
      • 32-KB L1D Per CorePac
      • 1024-KB Local L2 Per CorePac
  • ARM CorePac
    • Four ARM® Cortex®-A15 MPCore™ Processors at up to 1.4 GHz
    • 4MB of L2 Cache Memory Shared by Four ARM Cores
    • Full Implementation of ARMv7-A Architecture Instruction Set
    • 32-KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE) Master Port, Connected to MSMC for Low-Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 6MB of MSM SRAM Memory Shared by Eight DSP CorePacs and One ARM CorePac
    • Memory Protection Unit (MPU) for Both MSM SRAM and DDR3_EMIF
  • Multicore Navigator
    • 16k Multipurpose Hardware Queues With Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP, PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1-Gbps Wire Speed Throughput at 1.5 MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP, and WiMAX Air Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM, HMAC, CMAC, GMAC, AES, DES, 3DES, Kasumi, SNOW 3G, SHA-1, SHA-2 (256-Bit Hash), MD5
      • Up to 2.4 Gbps IPSec and 2.4 Gbps Air Ciphering
    • Ethernet Subsystem
      • Five-Port Switch (Four SGMII Ports)
  • Peripherals
    • Four Lanes of SRIO 2.1
      • Supports up to 5 GBaud
      • Supports Direct I/O, Message Passing
    • Two Lanes PCIe Gen2
      • Supports up to 5 GBaud
    • Two HyperLinks
      • Supports Connections to Other KeyStone™ Architecture Devices Providing Resource Scalability
      • Supports up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem (66AK2H14 Only)
      • Two XFI Ports
      • IEEE 1588 Support
    • Five Enhanced Direct Memory Access (EDMA) Modules
    • Two 72-Bit DDR3/DDR3L Interfaces With Speeds up to 1600 MHz
    • EMIF16 Interface
    • USB 3.0
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • Semaphore Module
    • 64-Bit Timers
      • Twenty 64-Bit Timers for 66AK2H14 and 66AK2H12
      • Fourteen 64-Bit Timers for 66AK2H06
    • Five On-Chip PLLs
  • Commercial Case Temperature:
    • 0ºC to 85ºC
  • Extended Case Temperature:
    • –40ºC to 100ºC

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

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類型 標題 日期
* Data sheet 66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G) PDF | HTML 2017年 10月 9日
* Errata 66AK2Hxx Multicore DSP+ARM KeyStone II SOC Errata (Revs 1.0, 1.1, 2.0, 3.0, 3.1) (Rev. F) 2018年 6月 5日
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 2023年 3月 30日
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 2023年 3月 30日
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022年 7月 7日
Application note Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B) PDF | HTML 2021年 9月 7日
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 2021年 6月 25日
Application note How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A) PDF | HTML 2021年 5月 19日
Application note Implementing an FTP Server on TI 66AK2H Device With RTOS PDF | HTML 2020年 8月 17日
Application note Using DSPLIB FFT Implementation for Real Input and Without Data Scaling PDF | HTML 2019年 6月 11日
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 2019年 6月 4日
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019年 6月 3日
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019年 6月 3日
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019年 5月 17日
Application note KeyStone II DDR3 interface bring-up 2019年 3月 7日
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018年 11月 19日
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018年 11月 19日
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018年 1月 16日
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018年 1月 16日
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017年 9月 30日
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017年 9月 30日
Application note Power Consumption Summary for 66AK2Hx System-on-Chip (SoC) Device Family 2017年 9月 28日
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 2017年 8月 21日
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017年 8月 14日
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017年 7月 26日
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017年 6月 21日
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017年 6月 21日
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 2016年 7月 27日
Application note Power Management of KS2 Device (Rev. C) 2016年 7月 15日
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016年 4月 30日
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016年 4月 30日
Application note SERDES Link Commissioning on KeyStone I and II Devices 2016年 4月 13日
White paper Multicore SoCs stay a step ahead of SoC FPGAs 2016年 2月 23日
Application note TI DSP Benchmarking 2016年 1月 13日
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 2015年 12月 22日
Application note Keystone II DDR3 Debug Guide 2015年 10月 16日
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015年 5月 6日
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015年 4月 9日
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 2015年 3月 27日
White paper TI’s processors leading the way in embedded analytics 2015年 3月 3日
Application note Keystone II DDR3 Initialization 2015年 1月 26日
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014年 11月 5日
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014年 11月 5日
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014年 9月 4日
User guide Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C) 2014年 9月 3日
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 2014年 8月 25日
Application note Hardware Design Guide for KeyStone II Devices 2014年 3月 24日
Product overview 66AK2Hx KeyStone Multicore DSP+ARM System-on-chips (Rev. A) 2013年 11月 8日
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 2013年 9月 30日
User guide Debug and Trace for KeyStone II Devices User's Guide 2013年 7月 26日
User guide ARM Bootloader User Guide for KeyStone II Devices 2013年 7月 21日
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013年 7月 15日
User guide Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D) 2013年 7月 3日
User guide C66x CorePac User's Guide (Rev. C) 2013年 6月 28日
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013年 6月 28日
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 2013年 5月 28日
User guide Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B) 2013年 2月 5日
Product overview Multicore DSPs for High-Performance Video Coding 2013年 1月 22日
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 2012年 11月 12日
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 2012年 11月 9日
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 2012年 11月 9日
User guide ARM CorePac User Guide for KeyStone II Devices 2012年 10月 31日
Application note Multicore Programming Guide (Rev. B) 2012年 8月 29日
User guide Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A) 2012年 7月 11日
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012年 3月 30日
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 27日
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 22日
Application note PCIe Use Cases for KeyStone Devices 2011年 12月 13日
Application note Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011年 9月 2日
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011年 5月 24日
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011年 5月 19日
User guide C66x CPU and Instruction Set Reference Guide 2010年 11月 9日
User guide C66x DSP Cache User's Guide 2010年 11月 9日
Application note Clocking Design Guide for KeyStone Devices 2010年 11月 9日
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010年 11月 9日
Application note Optimizing Loops on the C66x DSP 2010年 11月 9日
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010年 11月 9日
User guide Network Coprocessor for KeyStone Devices User's Guide 2010年 11月 2日

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XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比，XDS200 是兼具低成本與優異效能的完美平衡，可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

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所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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66AK2E05 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、1x C66x DSP 核心、NetCP、10GbE 66AK2H06 — 高效能多核心 DSP+Arm - 2x Arm A15 核心、4x C66x DSP 核心 66AK2H12 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心 66AK2H14 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心、10GbE AM5K2E02 — Sitara 處理器雙 Arm Cortex-A15 AM5K2E04 — Sitara 處理器：四 Arm Cortex-A15
數位訊號處理器 (DSP)
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-K2HK — Linux Processor SDK for K2H

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Arm 式處理器
66AK2H06 — 高效能多核心 DSP+Arm - 2x Arm A15 核心、4x C66x DSP 核心 66AK2H12 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心 66AK2H14 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心、10GbE
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-K2HK — Linux-RT Processor SDK for K2H

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Arm 式處理器
66AK2H06 — 高效能多核心 DSP+Arm - 2x Arm A15 核心、4x C66x DSP 核心 66AK2H12 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心 66AK2H14 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心、10GbE
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PROCESSOR-SDK-RTOS-K2HK — RTOS Processor SDK for K2H

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66AK2H06 — 高效能多核心 DSP+Arm - 2x Arm A15 核心、4x C66x DSP 核心 66AK2H12 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心 66AK2H14 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心、10GbE
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FFTLIB — 適用於浮點裝置的 FFT 函式庫

The Texas Instruments FFT library is an optimized floating-point math function library for computing the discrete Fourier transform (DFT).
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MATHLIB — 用於浮點裝置的 DSP 數學函式庫

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
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SPRC265 — TMS320C6000 DSP 庫 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
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CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

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C66XCODECS — 轉碼器 - 視訊、語音 - 適用於 C66x 架構產品

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
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模擬型號

66AK2H06 Power Consumption Model (Rev. A)

SPRM649A.ZIP (136 KB) - Power Model
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模擬型號

66AK2H12 66AK2H06 AAW BSDL Model

SPRM609.ZIP (36 KB) - BSDL Model
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模擬型號

66AK2H12 66AK2H06 AAW IBIS Model

SPRM618.ZIP (2189 KB) - IBIS Model
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模擬型號

66AK2Hx FloTherm Model

SPRM603.ZIP (6 KB) - Power Model
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模擬型號

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
lock = 需要匯出核准 (1 分鐘)
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配置圖

66AK2H14 66AK2H12 66AK2H106 AAW OrCAD Symbols

SPRR189.ZIP (144 KB)
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參考設計

TIDEP0045 — 透過 TI C6678 DSP 實作即時合成孔徑雷達 (SAR) 演算法的參考設計

This reference design shows a real-time synthetic aperture radar (SAR) running on a multicore TMS320C6678 digital signal processor (DSP). One of the main challenges of  SAR is to generate high-resolution images in real-time, since forming the image involves computationally-demanding signal (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0037 — 使用 TMS320C6678 處理器實作具電源效率且可擴充的 H.265/HEVC 解決方案參考設計

HEVC is an efficient, but processing intensive video standard, that is said to double the data compression ratio compared to H.264 / MPEG-4 at the same level of video quality. This design shows how a power efficient, soft H.265 / HEVC solution, that scales across resolutions, frame rates & (...)
Design guide: PDF
電路圖: PDF
封裝 針腳 CAD 符號、佔位空間與 3D 模型
FCBGA (AAW) 1517 Ultra Librarian
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