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微控制器 (MCU) 與處理器
數位訊號處理器 (DSP)

66AK2L06

現行

多核心 DSP+ARM KeyStone II 晶片系統 (SoC)

立即訂購
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66AK2L06

現行
產品規格表 立即訂購

產品詳細資料

DSP type 4 C66x DSP (max) (MHz) 1200 CPU 32-/64-bit Operating system Integrity, Linux, SYS/BIOS, VxWorks Security Cryptographic acceleration, Device identity, Secure boot Ethernet MAC 4-port 1Gb Switch PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) 0 to 0
DSP type 4 C66x DSP (max) (MHz) 1200 CPU 32-/64-bit Operating system Integrity, Linux, SYS/BIOS, VxWorks Security Cryptographic acceleration, Device identity, Secure boot Ethernet MAC 4-port 1Gb Switch PCIe 2 PCIe Gen2 Rating Catalog Operating temperature range (°C) 0 to 0
FCBGA (CMS) 900 625 mm² 25 x 25
  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D PerCorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Msps at FFT Size 1024
      • Support Max FFT Size 8192
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security AcceleratorEngine Enables Support for
      • IPSec, SRTP, and SSL/TLS Security
      • ECB, CBC, CTR, F8,CCM, GCM, HMAC,
        CMAC, GMAC, AES, DES, 3DES, SHA-1,
        SHA-2 (256-bit Hash), MD5
      • Up to 6.4 Gbps IPSec
    • Ethernet Subsystem
    • Peripherals
      • DigitalFront End (DFE) Subsystem
        • Support up to Four Lane JESD204A/B (7.37
          Gbps Line Rate Max.) Interface to Multiple
          Data Converters
        • Integration of Digital Down/Up-Conversion
          (DDC/DUC) Module
      • IQNet Subsystem
        • Transporting data streams to an integrated
          Digital Front End (DFE)
      • Two One-Lane PCIe Gen2 Interfaces
        • Supports Up to 5 GBaud
      • Three Enhanced Direct Memory Access (EDMA)
        Controllers
      • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
      • EMIF16 Interface
      • USB 3.0 Interface
      • USIM Interface
      • Four UART Interfaces
      • Three I2C Interfaces
      • 64 GPIO Pins
      • Three SPI Interfaces
      • Semaphore Module
      • Fourteen 64-Bit Timers
    • Commercial Case Temperature:
      • 0°C to 100°C
    • Extended Case Temperature:
      • –40°C to 100°C
  • Four TMS320C66x DSP Core Subsystems (C66x
    CorePacs), Each With
    • 1.0 GHz or 1.2 GHz C66x Fixed/Floating-Point
      DSP Core
      • 38.4 GMacs/Core for Fixed Point @ 1.2 GHz
      • 19.2 GFlops/Core for Floating Point @ 1.2
        GHz
    • Memory
      • 32K Byte L1P Per CorePac
      • 32K Byte L1D PerCorePac
      • 1024K Byte Local L2 Per CorePac
  • ARM CorePac
    • Two ARM® Cortex®-A15 MPCore™ Processors
      at Up to 1.2 GHz
    • 1MB L2 Cache Memory Shared by Two ARM
      Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC for Low
      Latency Access to Shared MSMC SRAM
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory Shared by Four DSP
      CorePacs and One ARM CorePac
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • On-chip Standalone RAM (OSR) - 1MB On-Chip
    SRAM for Additional Shared Memory
  • Hardware Coprocessors
    • Two Fast Fourier Transform Coprocessors
      • Support Up to 1200 Msps at FFT Size 1024
      • Support Max FFT Size 8192
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security AcceleratorEngine Enables Support for
      • IPSec, SRTP, and SSL/TLS Security
      • ECB, CBC, CTR, F8,CCM, GCM, HMAC,
        CMAC, GMAC, AES, DES, 3DES, SHA-1,
        SHA-2 (256-bit Hash), MD5
      • Up to 6.4 Gbps IPSec
    • Ethernet Subsystem
    • Peripherals
      • DigitalFront End (DFE) Subsystem
        • Support up to Four Lane JESD204A/B (7.37
          Gbps Line Rate Max.) Interface to Multiple
          Data Converters
        • Integration of Digital Down/Up-Conversion
          (DDC/DUC) Module
      • IQNet Subsystem
        • Transporting data streams to an integrated
          Digital Front End (DFE)
      • Two One-Lane PCIe Gen2 Interfaces
        • Supports Up to 5 GBaud
      • Three Enhanced Direct Memory Access (EDMA)
        Controllers
      • 72-Bit DDR3 Interface, Speeds Up to 1600 MHz
      • EMIF16 Interface
      • USB 3.0 Interface
      • USIM Interface
      • Four UART Interfaces
      • Three I2C Interfaces
      • 64 GPIO Pins
      • Three SPI Interfaces
      • Semaphore Module
      • Fourteen 64-Bit Timers
    • Commercial Case Temperature:
      • 0°C to 100°C
    • Extended Case Temperature:
      • –40°C to 100°C

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.

The 66AK2L06 KeyStone SoC is a member of the C66x family based on TI's new KeyStone II Multicore SoC Architecture and is a low-power solution with integrated JESD204B lanes that meets the more stringent power, size, and cost requirements of applications requiring connectivity with ADC and DAC based applications. The device’s ARM and DSP cores deliver exceptional processing power on platforms requiring high signal and control processing.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (ARM CorePac, C66x CorePacs, IP network, Digital Front End, and FFT processing) and uses a queue-based communication system that allows the SoC resources to operate efficiently and seamlessly. This unique SoC architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to dedicated coprocessors and high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The addition of the ARM CorePac in the 66AK2L06 device enables the ability for complex control code processing on-chip. Operations such as housekeeping and management processing can be performed with the Cortex-A15 processor.

TI’s new C66x core launches a new era of DSP technology by combining fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is an industry-leading 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x CorePac incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2L06 contains many coprocessors to offload the bulk of the processing demands of higher layers of application. This keeps the cores free for algorithms and other differentiating functions. The SoC contains multiple copies of key coprocessors such as the FFTC. The architectural elements of the SoC (Multicore Navigator) ensure that data is processed without any CPU intervention or overhead, allowing the system to make optimal use of its resources.

TI’s scalable multicore SoC architecture solutions provide developers with a range of software-compatible and hardware-compatible devices to minimize development time and maximize reuse.

The 66AK2L06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows and Linux debugger interface for visibility into source code execution.
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Support through a third party

This product does not have ongoing direct design support from TI. For support while working through your design, you may contact the following third party: Azcom Technology.

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類型 標題 日期
* Data sheet 66AK2L06 Multicore DSP+ARM KeyStone II System-on-Chip (SoC) datasheet 2015年 4月 21日
* Errata 66AK2Lxx Multicore DSP+ARM KeyStone II SOC (Silicon Revision 1.0) 2015年 4月 20日
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022年 7月 7日
Application note Keystone Error Detection and Correction EDC ECC (Rev. A) 2021年 6月 25日
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 2019年 6月 4日
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 2017年 8月 21日
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017年 8月 14日
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017年 7月 26日
Design guide Wideband Receiver With 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design 2016年 9月 23日
Application note Keystone EDMA FAQ 2016年 9月 1日
Third party document Download XEVMK2LX schematics, bill of materials and design guide 2016年 8月 3日
Third party document XEVMK2LX Quick Setup Guide 2016年 8月 3日
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 2016年 7月 27日
Application note Power Management of KS2 Device (Rev. C) 2016年 7月 15日
Application note 66AK2L06 JESD Attach to ADC12J4000/DAC38J84 Getting Started Guide (Rev. B) 2016年 6月 20日
Technical article How to complete your RF sampling solution PDF | HTML 2016年 5月 18日
Application note SERDES Link Commissioning on KeyStone I and II Devices 2016年 4月 13日
Technical article Accelerating the Fast Fourier Transform (FFT/iFFT) by 10x and more PDF | HTML 2016年 3月 2日
White paper Multicore SoCs stay a step ahead of SoC FPGAs 2016年 2月 23日
Application note TI DSP Benchmarking 2016年 1月 13日
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 2015年 12月 22日
White paper Optimizing Modern Radar Systems using Low- Latency, High-Performance FFT Coproce 2015年 12月 17日
Technical article Are 66AK2L06 SoCs an answer to miniaturization of test and measurement equipment? PDF | HTML 2015年 12月 2日
White paper Optimizing your test and measurement solution by leveraging the most integrated 2015年 11月 3日
Design guide 66AK2L06 JESD Attach to ADC12J4000 / DAC38J84 Design Guide (Rev. A) 2015年 10月 22日
Application note Keystone II DDR3 Debug Guide 2015年 10月 16日
Application note System solution for avionics & defense 2015年 9月 23日
Application note TPS544Bxx/TPS544Cxx Powering TCI6630K2L in Smart Reflex Class 0 TC Mode 2015年 9月 18日
Technical article Summertime showdown: DSPs vs FPGAs PDF | HTML 2015年 7月 9日
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015年 5月 6日
Technical article Wireless infrastructure - Now simpler and more accessible! PDF | HTML 2015年 5月 5日
User guide Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 2015年 4月 28日
Product overview 66AK2L06 SoC Product Bulletin 2015年 4月 15日
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015年 4月 9日
White paper Optimizing synthetic aperture radar design with TI's integrated 66AK2L06 SoC 2015年 4月 9日
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 2015年 3月 27日
User guide Digital Front End (DFE) for Keystone II Devices User's Guide (Rev. A) 2015年 3月 23日
White paper Ready to make the jump to JESD204B? White Paper (Rev. B) 2015年 3月 19日
User guide Fast Fourier Transform Coprocessor (FFTC) for KeyStone II Devices User's Guide (Rev. A) 2015年 2月 11日
Application note Keystone II DDR3 Initialization 2015年 1月 26日
User guide IQN2 for KeyStone II Devices User's Guide (Rev. A) 2014年 10月 1日
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014年 9月 4日
User guide Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 2014年 8月 19日
User guide Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 2014年 8月 19日
User guide Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 2014年 8月 13日
Application note Hardware Design Guide for KeyStone II Devices 2014年 3月 24日
User guide Debug and Trace for KeyStone II Devices User's Guide 2013年 7月 26日
User guide DSP Bootloader for KeyStone Architecture User's Guide (Rev. C) 2013年 7月 15日
User guide C66x CorePac User's Guide (Rev. C) 2013年 6月 28日
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013年 6月 28日
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 2012年 11月 12日
User guide ARM CorePac User Guide for KeyStone II Devices 2012年 10月 31日
Application note Multicore Programming Guide (Rev. B) 2012年 8月 29日
User guide Semaphore2 Hardware Module for KeyStone Devices User's Guide (Rev. A) 2012年 4月 24日
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012年 3月 30日
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 27日
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 22日
Application note PCIe Use Cases for KeyStone Devices 2011年 12月 13日
Application note Introduction to TMS320C6000 DSP Optimization 2011年 10月 6日
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011年 9月 2日
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011年 5月 24日
White paper Software and Hardware Design Challenges Due to Dynamic Raw NAND Market 2011年 5月 19日
User guide C66x CPU and Instruction Set Reference Guide 2010年 11月 9日
User guide C66x DSP Cache User's Guide 2010年 11月 9日
Application note Clocking Design Guide for KeyStone Devices 2010年 11月 9日
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010年 11月 9日
Application note Optimizing Loops on the C66x DSP 2010年 11月 9日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比，XDS200 是兼具低成本與優異效能的完美平衡，可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

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TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

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偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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軟體開發套件 (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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Arm 式處理器
66AK2E05 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、1x C66x DSP 核心、NetCP、10GbE 66AK2H06 — 高效能多核心 DSP+Arm - 2x Arm A15 核心、4x C66x DSP 核心 66AK2H12 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心 66AK2H14 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心、10GbE AM5K2E02 — Sitara 處理器雙 Arm Cortex-A15 AM5K2E04 — Sitara 處理器：四 Arm Cortex-A15
數位訊號處理器 (DSP)
66AK2L06 — 多核心 DSP+ARM KeyStone II 晶片系統 (SoC)
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-K2L — Linux Processor SDK for K2L

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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數位訊號處理器 (DSP)
66AK2L06 — 多核心 DSP+ARM KeyStone II 晶片系統 (SoC)
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-K2L — Linux-RT Processor SDK for K2L

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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數位訊號處理器 (DSP)
66AK2L06 — 多核心 DSP+ARM KeyStone II 晶片系統 (SoC)
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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-K2L — RTOS Processor SDK for K2L

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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數位訊號處理器 (DSP)
66AK2L06 — 多核心 DSP+ARM KeyStone II 晶片系統 (SoC)
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軟體開發套件 (SDK)

RFSDK — 射頻軟體開發套件 (RFSDK)

Texas Instruments Radio Frequency Software Development Kit (RFSDK) is a collection of highly optimized APIs and highly abstracted commands to control, configure and manage the JESD204B interface, digital front end (DFE), analog front end (AFE) and high speed data converters (ADC/DAC). The RFSDK (...)
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驅動程式或資料庫

MATHLIB — 用於浮點裝置的 DSP 數學函式庫

The Texas Instruments math library is an optimized floating-point math function library for C programmers using TI floating point devices. These routines are typically used in computationally intensive real-time applications where optimal execution speed is critical. By using these routines instead (...)
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驅動程式或資料庫

SPRC264 — TMS320C5000/6000 映像庫 (IMGLIB)

C5000/6000 Image Processing Library (IMGLIB) is an optimized image/video processing function library for C programmers. It includes C-callable general-purpose image/video processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
使用指南: PDF
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驅動程式或資料庫

SPRC265 — TMS320C6000 DSP 庫 (DSPLIB)

TMS320C6000 Digital Signal Processor Library (DSPLIB) is a platform-optimized DSP function library for C programmers. It includes C-callable, general-purpose signal-processing routines that are typically used in computationally intensive real-time applications. With these routines, higher (...)
使用指南: PDF
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It comprises a suite of tools used to develop and debug embedded applications.  Code Composer Studio is available for download across Windows®, Linux® and macOS® desktops. It can also (...)

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軟體轉碼器

C66XCODECS — 轉碼器 - 視訊、語音 - 適用於 C66x 架構產品

TI codecs are free, come with production licensing and are available for download now. All are production-tested for easy integration into video and voice applications. In many cases, the C64x+ codecs are provided and validated for C66x platforms. Datasheets and Release Notes are on the download (...)
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模擬型號

66AK2L06 Power Consumption Model

SPRM656.ZIP (169 KB) - Power Model
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模擬型號

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
lock = 需要匯出核准 (1 分鐘)
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模擬型號

TCI6632K2L TCI6631K2L and TCI6630K2L AAW IBIS Model

SPRM589.ZIP (3192 KB) - IBIS Model
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參考設計

TIDEP0081 — 使用 66AK2L06 JESD204B 連接 ADC32RF80 的寬頻接收器參考設計

For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0060 — 使用 DSP+ARM SoC 的最佳化雷達系統參考設計

For modern radar system developers currently using an FPGA or ASIC to connect to high speed data converters, who need faster time to market with increased performance and significant reduction in cost, power, and size, this reference design includes the first widely available processor integrating (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0034 — 連接至寬頻 ADC 和 DAC 且具有 JESD204B 的 66AK2L06 DSP+ARM 處理器

For developers currently using an FPGA or ASIC to connect to high speed data converters who need faster time to market with increased performance and significant reduction in cost, power, and size this reference design includes the first widely available processor integrating a JESD204B interface (...)
Design guide: PDF
電路圖: PDF
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