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微控制器 (MCU) 與處理器
Arm 式處理器

AM5K2E04

現行

Sitara 處理器：四 Arm Cortex-A15

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產品規格表
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AM5K2E04

現行
產品規格表 立即訂購

產品詳細資料

Arm CPU 4 Arm Cortex-A15 Arm (max) (MHz) 1250, 1400 Coprocessors Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
Arm CPU 4 Arm Cortex-A15 Arm (max) (MHz) 1250, 1400 Coprocessors Network co-processor CPU 32-bit Protocols Ethernet Ethernet MAC 8-Port 1Gb switch PCIe 4 PCIe Gen 2 Hardware accelerators Packet Accelerator, Security Accelerator Features Networking Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 100
FCBGA (ABD) 1089 729 mm² 27 x 27
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C
  • ARM® Cortex®-A15 MPCore™ CorePac
    • Up to Four ARM Cortex-A15 Processor Cores at
      up to 1.4-GHz
    • 4MB L2 Cache Memory Shared by all Cortex-
      A15 Processor Cores
    • Full Implementation of ARMv7-A Architecture
      Instruction Set
    • 32KB L1 Instruction and Data Caches per Core
    • AMBA 4.0 AXI Coherency Extension (ACE)
      Master Port, Connected to MSMC (Multicore
      Shared Memory Controller) for Low Latency
      Access to SRAM and DDR3
  • Multicore Shared Memory Controller (MSMC)
    • 2 MB SRAM Memory for ARM CorePac
    • Memory Protection Unit for Both SRAM and
      DDR3_EMIF
  • Multicore Navigator
    • 8k Multi-Purpose Hardware Queues with Queue
      Manager
    • One Packet-Based DMA Engine for Zero-
      Overhead Transfers
  • Network Coprocessor
    • Packet Accelerator Enables Support for
      • Transport Plane IPsec, GTP-U, SCTP,
        PDCP
      • L2 User Plane PDCP (RoHC, Air Ciphering)
      • 1 Gbps Wire Speed Throughput at 1.5
        MPackets Per Second
    • Security Accelerator Engine Enables Support for
      • IPSec, SRTP, 3GPP and WiMAX Air
        Interface, and SSL/TLS Security
      • ECB, CBC, CTR, F8, A5/3, CCM, GCM,
        HMAC, CMAC, GMAC, AES, DES, 3DES,
        Kasumi, SNOW 3G, SHA-1, SHA-2 (256-bit
        Hash), MD5
      • Up to 6.4 Gbps IPSec and 3 Gbps Air
        Ciphering
    • Ethernet Subsystem
      • Eight SGMII Ports with Wire Rate Switching
      • IEEE1588 v2 (with Annex D/E/F) Support
      • 8 Gbps Total Ingress/Egress Ethernet BW
        from Core
      • Audio/Video Bridging (802.1Qav/D6.0)
      • QOS Capability
      • DSCP Priority Mapping
  • Peripherals
    • Two PCIe Gen2 Controllers with Support for
      • Two Lanes per Controller
      • Supports Up to 5 GBaud
    • One HyperLink
      • Supports Connections to Other KeyStone Architecture
        Devices Providing Resource
        Scalability
      • Supports Up to 50 GBaud
    • 10-Gigabit Ethernet (10-GbE) Switch Subsystem
      • Two SGMII/XFI Ports with Wire Rate
        Switching and MACSEC Support
      • IEEE1588 v2 (with Annex D/E/F) Support
    • One 72-Bit DDR3/DDR3L Interface with Speeds Up
      to 1600 MTPS in DDR3 Mode
    • EMIF16 Interface
    • Two USB 2.0/3.0 Controllers
    • USIM Interface
    • Two UART Interfaces
    • Three I2C Interfaces
    • 32 GPIO Pins
    • Three SPI Interfaces
    • One TSIP
      • Support 1024 DS0s
      • Support 2 Lanes at 32.768/16.3848.192
        Mbps Per Lane
  • System Resources
    • Three On-Chip PLLs
    • SmartReflex Automatic Voltage Scaling
    • Semaphore Module
    • Twelve 64-Bit Timers
    • Five Enhanced Direct Memory Access (EDMA)
      Modules
  • Commercial Case Temperature:
    • 0°C to 85°C
  • Extended Case Temperature:
    • –40°C to 100°C

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.

The AM5K2E0x is a high performance device based on TI’s KeyStone II Multicore SoC Architecture, incorporating the most performance-optimized Cortex-A15 processor dual-core or quad-core CorePac that can run at a core speed of up to 1.4 GHz. TI’s AM5K2E0x device enables a high performance, power-efficient and easy to use platform for developers of a broad range of applications such as enterprise grade networking end equipment, data center networking, avionics and defense, medical imaging, test and automation.

TI’s KeyStone II Architecture provides a programmable platform integrating various subsystems (for example, ARM CorePac (Cortex-A15 Processor Quad Core CorePac), network processing, and uses a queue-based communication system that allows the device resources to operate efficiently and seamlessly. This unique device architecture also includes a TeraNet switch that enables the wide mix of system elements, from programmable cores to high-speed IO, to each operate at maximum efficiency with no blocking or stalling.

The AM5K2E0x KeyStone II device integrates a large amount of on-chip memory. The Cortex-A15 processor cores each have 32KB of L1Data and 32KB of L1 Instruction cache. The up to four Cortex A15 cores in the ARM CorePac share a 4MB L2 Cache. The device also integrates 2MB of Multicore Shared Memory (MSMC) that can be used as a shared L3 SRAM. All L2 and MSMC memories incorporate error detection and error correction. For fast access to external memory, this device includes a 64-bit DDR-3 (72-bit with ECC support) external memory interface (EMIF) running at 1600 MTPS.

The device enables developers to use a variety of development and debugging tools that include GNU GCC, GDB, Open source Linux, Eclipse based debugging environment enabling kernel and user space debugging using a variety of Eclipse plug-ins including TI's industry leading IDE Code Composer Studio.
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類型 標題 日期
* Data sheet AM5K2E04/02 Multicore ARM KeyStone II System-on-Chip (SoC) datasheet (Rev. D) 2015年 3月 11日
* Errata AM5K2E04/02 KeyStone SoC Silicon Errata (Silicon Rev 1.0) (Rev. B) 2015年 8月 20日
User guide ARM Assembly Language Tools v20.2.0.LTS User's Guide (Rev. Z) PDF | HTML 2023年 3月 30日
User guide ARM Optimizing C/C++ Compiler v20.2.0.LTS User's Guide (Rev. W) PDF | HTML 2023年 3月 30日
Application note DDR3 Design Requirements for KeyStone Devices (Rev. D) PDF | HTML 2022年 7月 7日
Application note Using Arm ROM Bootloader on Keystone II Devices PDF | HTML 2019年 6月 4日
User guide ARM Assembly Language Tools v19.6.0.STS User's Guide (Rev. X) 2019年 6月 3日
User guide ARM Optimizing C/C++ Compiler v19.6.0.STS User's Guide (Rev. U) 2019年 6月 3日
Application note Keystone Multicore Device Family Schematic Checklist PDF | HTML 2019年 5月 17日
Application note KeyStone II DDR3 interface bring-up 2019年 3月 7日
User guide ARM Assembly Language Tools v18.12.0.LTS User's Guide (Rev. W) 2018年 11月 19日
User guide ARM Optimizing C/C++ Compiler v18.12.0.LTS User's Guide (Rev. T) 2018年 11月 19日
User guide How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018年 9月 24日
User guide ARM Assembly Language Tools v18.1.0.LTS User's Guide (Rev. U) 2018年 1月 16日
User guide ARM Optimizing C/C++ Compiler v18.1.0.LTS User's Guide (Rev. R) 2018年 1月 16日
User guide ARM Assembly Language Tools v17.9.0.STS User's Guide (Rev. T) 2017年 9月 30日
User guide ARM Optimizing C/C++ Compiler v17.9.0.STS User's Guide (Rev. Q) 2017年 9月 30日
User guide KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A) 2017年 8月 21日
Application note Thermal Design Guide for DSP and Arm Application Processors (Rev. B) 2017年 8月 14日
User guide Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I) 2017年 7月 26日
User guide ARM Assembly Language Tools v17.6.0.STS User's Guide (Rev. S) 2017年 6月 21日
User guide ARM Optimizing C/C++ Compiler v17.6.0.STS User's Guide (Rev. P) 2017年 6月 21日
Application note Power Consumption Summary for K2E System-on-Chip (SoC) Device Family 2017年 6月 14日
Application note Clocking Spreadsheet for K2E Device Family 2017年 1月 26日
User guide Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A) 2016年 7月 27日
Application note Power Management of KS2 Device (Rev. C) 2016年 7月 15日
User guide ARM Assembly Language Tools v16.9.0.LTS User's Guide (Rev. P) 2016年 4月 30日
User guide ARM Optimizing C/C++ Compiler v16.9.0.LTS User's Guide (Rev. M) 2016年 4月 30日
Application note Throughput Performance Guide for KeyStone II Devices (Rev. B) 2015年 12月 22日
Application note Keystone II DDR3 Debug Guide 2015年 10月 16日
User guide Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B) 2015年 5月 6日
User guide Gigabit Ethernet (GbE) Switch SS for K2E & K2L Devices User's Guide (Rev. A) 2015年 4月 28日
User guide Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H) PDF | HTML 2015年 4月 9日
User guide DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C) 2015年 3月 27日
White paper Save power and costs with TI's K2E on-chip networking features 2015年 3月 25日
Application note Keystone II DDR3 Initialization 2015年 1月 26日
User guide ARM Assembly Language Tools v5.2 User's Guide (Rev. M) 2014年 11月 5日
User guide ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J) 2014年 11月 5日
User guide Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C) 2014年 9月 4日
White paper KeyStone™-II-based processors: 10G Ethernet as an optical interface 2014年 8月 25日
User guide Packet Accelerator 2 (PA2) for K2E and K2L Devices User's Guide 2014年 8月 19日
User guide Security Accelerator 2 (SA2) for K2E and K2L Devices User's Guide 2014年 8月 19日
White paper Differentiating AM5K2E02 and AM5K2E04 SoCs from Alternate ARM® Cortex®-A15 Devic 2014年 8月 14日
User guide Network Coprocessor (NETCP) for K2E and K2L Devices User's Guide 2014年 8月 13日
Application note Hardware Design Guide for KeyStone II Devices 2014年 3月 24日
User guide PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D) 2013年 9月 30日
User guide Debug and Trace for KeyStone II Devices User's Guide 2013年 7月 26日
User guide ARM Bootloader User Guide for KeyStone II Devices 2013年 7月 21日
User guide Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A) 2013年 6月 28日
User guide HyperLink for KeyStone Devices User's Guide (Rev. C) 2013年 5月 28日
User guide 10 Gigabit Ethernet Switch Subsystem User Guide for KeyStone II Devices 2013年 2月 8日
User guide Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices 2012年 11月 12日
Product overview Industrial Imaging: Applications of the K2H and K2E platforms 2012年 11月 9日
Product overview Video Infrastructure - Applications of the K2E, K2H platforms 2012年 11月 9日
User guide ARM CorePac User Guide for KeyStone II Devices 2012年 10月 31日
Application note Multicore Programming Guide (Rev. B) 2012年 8月 29日
User guide Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A) 2012年 3月 30日
User guide Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 27日
User guide 64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A) 2012年 3月 22日
Application note PCIe Use Cases for KeyStone Devices 2011年 12月 13日
User guide Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide 2011年 9月 2日
User guide External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A) 2011年 5月 24日
User guide C66x DSP Cache User's Guide 2010年 11月 9日
Application note Clocking Design Guide for KeyStone Devices 2010年 11月 9日
User guide General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide 2010年 11月 9日
Application note Optimizing Loops on the C66x DSP 2010年 11月 9日
User guide Telecom Serial Interface Port (TSIP) for KeyStone Devices User's Guide 2010年 11月 9日
User guide Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG 2010年 11月 9日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

偵錯探測器

TMDSEMU200-U — XDS200 USB 偵錯探測器

XDS200 是為 TI 嵌入式裝置偵錯的偵錯探測器 (模擬器)。與低成本 XDS110 和高效能 XDS560v2 相比，XDS200 是兼具低成本與優異效能的完美平衡，可在單一 pod 中支援各種標準 (IEEE1149.1、IEEE1149.7、SWD)。所有 XDS 偵錯探測器均支援具嵌入式追踪緩衝區 (ETB) 的 Arm® 與 DSP 處理器中的核心和系統追蹤功能。透過針腳進行核心追蹤則需要 XDS560v2 PRO TRACE。

XDS200 透過 TI 20 針腳連接器 (配備適用 TI 14 針腳、Arm Cortex® 10 針腳和 Arm 20 針腳的多重轉接器) (...)

TI.com 無法提供
偵錯探測器

TMDSEMU560V2STM-U — XDS560v2 System Trace USB 偵錯探測器

XDS560v2 是 XDS560™ 偵錯探測器系列的最高性能表現，支援傳統 JTAG 標準 (IEEE1149.1) 和 cJTAG (IEEE1149.7)。請注意，序列線偵錯 (SWD) 不受支援。

所有 XDS 偵錯探測器均支援所有具有嵌入式追踪緩衝區 (ETB) 的 ARM 和 DSP 處理器中的核心和系統追蹤功能。對於針腳追蹤則需要 XDS560v2 PRO TRACE。

XDS560v2 透過 MIPI HSPT 60 針腳接頭 (具有用於 TI 14 針腳、TI 20 針腳和 ARM 20 針腳的多轉接器) 連接到目標電路板，並透過 USB2.0 高速 (480Mbps) (...)

TI.com 無法提供
偵錯探測器

TMDSEMU560V2STM-UE — XDS560v2 System Trace USB 與乙太網路偵錯探測器

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7). Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

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開發套件

EVMK2EX — K2E 開發基板

The EVMK2EX is a full-featured development tool for 66AK2Exx and AM5K2Exx KeyStone II based SoCs. Get started developing general purpose embedded computing systems for industrial, mission critical, and networking applications today with this double-wide AMC form-factor evaluation board featuring a (...)

使用指南: PDF
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軟體開發套件 (SDK)

BIOSLINUXMCSDK-K2 — MCSDK supporting SYS/BIOS RTOS and Linux OS for KeyStone II ARM A15 + DSP C66x

NOTE: K2x, C665x and C667x devices are now actively maintained on the Processor-SDK release stream. See links above.

Our Multicore Software Development Kits (MCSDK) provide highly-optimized bundles of foundational, platform-specific drivers to enable development on selected TI ARM and DSP devices. (...)

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產品
Arm 式處理器
66AK2E05 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、1x C66x DSP 核心、NetCP、10GbE 66AK2H06 — 高效能多核心 DSP+Arm - 2x Arm A15 核心、4x C66x DSP 核心 66AK2H12 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心 66AK2H14 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、8x C66x DSP 核心、10GbE AM5K2E02 — Sitara 處理器雙 Arm Cortex-A15 AM5K2E04 — Sitara 處理器：四 Arm Cortex-A15
數位訊號處理器 (DSP)
66AK2L06 — 多核心 DSP+ARM KeyStone II 晶片系統 (SoC)
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-K2E — Linux Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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產品
Arm 式處理器
66AK2E05 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、1x C66x DSP 核心、NetCP、10GbE AM5K2E02 — Sitara 處理器雙 Arm Cortex-A15 AM5K2E04 — Sitara 處理器：四 Arm Cortex-A15
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軟體開發套件 (SDK)

PROCESSOR-SDK-LINUX-RT-K2E — Linux-RT Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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產品
Arm 式處理器
66AK2E05 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、1x C66x DSP 核心、NetCP、10GbE AM5K2E02 — Sitara 處理器雙 Arm Cortex-A15 AM5K2E04 — Sitara 處理器：四 Arm Cortex-A15
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軟體開發套件 (SDK)

PROCESSOR-SDK-RTOS-K2E — RTOS Processor SDK for K2E

 

Processor SDK (Software Development Kit) is a unified software platform for TI embedded processors providing easy setup and fast out-of-the-box access to benchmarks and demos.  All releases of Processor SDK are consistent across TI’s broad portfolio, allowing developers to seamlessly (...)

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產品
Arm 式處理器
66AK2E05 — 高效能多核心 DSP+Arm - 4x Arm A15 核心、1x C66x DSP 核心、NetCP、10GbE AM5K2E02 — Sitara 處理器雙 Arm Cortex-A15 AM5K2E04 — Sitara 處理器：四 Arm Cortex-A15
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IDE、配置、編譯器或偵錯程式

CCSTUDIO — Code Composer Studio™ integrated development environment (IDE)

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

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模擬型號

AM5K2E04 AM5K2E02 ABD BSDL Model

SPRM623.ZIP (28 KB) - BSDL Model
下載
模擬型號

AM5K2E04 AM5K2E02 ABD IBIS Model

SPRM621.ZIP (2180 KB) - IBIS Model
下載
模擬型號

AM5K2E04 AM5K2E02 ABD Thermal Model

SPRM622.ZIP (5 KB) - Thermal Model
下載
模擬型號

AM5K2E04 and AM5K2E02 Power Consumption Model (Rev. A)

SPRM653A.ZIP (142 KB) - Power Model
下載
模擬型號

KeyStone II IBIS AMI Models

SPRM743.ZIP (265889 KB) - IBIS-AMI Model
lock = 需要匯出核准 (1 分鐘)
lock 下載
計算工具

CLOCKTREETOOL — 適用於 Sitara、車用、視覺分析和數位訊號處理器的時脈樹工具

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
使用指南: PDF
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配置圖

66AK2E05 66AK2E02 AM5K2E04 AM5K2E02 ABD OrCAD Symbols

SPRR197.ZIP (99 KB)
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參考設計

TIDEP0042 — 使用 TPS544C25 和 PMBus 為 K2E 產生 AVS SmartReflex 核心電壓的參考設計

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage using software and the PMBus interface of the TPS544C25. The circuit can be implemented on the XEVMK2EX.
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0041 — 可產生 AVS SmartReflex 核心電壓、適用於 K2E 的 PMBus 參考設計

The K2E requires the use of AVS SmartReflex control for the CVDD core voltage. This design provides method of generating the proper voltage without the need for any software. The circuit is currently implemented on the XEVMK2EX.
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0031 — 使用具有 PMBus 的 UCD9090 為 K2E 進行電源排序

The K2E devices require power supplies to be sequenced in a proper order. This design demonstrates power sequencing for the 66AK2Ex and AM5K2Ex families of KeyStone II ARM+DSP and ARM-only multicore processors by use of the UCD9090. The UCD9090 is a 10-rail PMBus/I2C addressable power-supply (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDEP0026 — K2E 時鐘產生參考設計

A single clock source should not be used to drive multiple clock inputs for a high-performance processor device, such as multicore ARM Cortex-A15 based 66AK2Ex and AM5K2Ex processors, since excessive loading, reflections, and noise will negatively impact performance. These can be avoided through (...)
Design guide: PDF
電路圖: PDF
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