ADC32RF44
- 14-Bit, Dual-Channel, 2.6-GSPS ADC
- Noise Floor: –154.2 dBFS/Hz
- RF Input Supports Up to 4.0 GHz
- Aperture Jitter: 90 fS
- Channel Isolation: 95 dB at fIN = 1.8 GHz
- Spectral Performance (fIN = 900 MHz, –2 dBFS):
- SNR: 61.2 dBFS
- SFDR: 65-dBc HD2, HD3
- SFDR: 79-dBc Worst Spur
- Spectral Performance (fIN = 1.85 GHz, –2 dBFS):
- SNR: 58.3 dBFS
- SFDR: 69-dBc HD2, HD3
- SFDR: 74-dBc Worst Spur
- On-Chip Digital Down-Converters:
- Up to 4 DDCs (Dual-Band Mode)
- Up to 3 Independent NCOs per DDC
- On-Chip Input Clamp for Overvoltage Protection
- Programmable On-Chip Power Detectors with Alarm Pins for AGC Support
- On-Chip Dither
- On-Chip Input Termination
- Input Full-Scale: 1.35 VPP
- Support for Multi-Chip Synchronization
- JESD204B Interface:
- Subclass 1-Based Deterministic Latency
- 4 Lanes Per Channel at 12.5 Gbps
- Power Dissipation: 2.95 W/Ch at 2.6 GSPS
- 72-Pin VQFN Package (10 mm × 10 mm)
The ADC32RF44 device is a 14-bit, 2.6-GSPS, dual-channel, analog-to-digital converter (ADC) that supports RF sampling with input frequencies up to 4 GHz and beyond. Designed for high signal-to-noise ratio (SNR), the ADC32RF44 delivers a noise spectral density of –154.2 dBFS/Hz as well as dynamic range and channel isolation over a large input frequency range. The buffered analog input with on-chip termination provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy.
Each ADC channel can be connected to a dual-band, digital down-converter (DDC) with up to three independent, 16-bit numerically-controlled oscillators (NCOs) per DDC for phase-coherent frequency hopping. Additionally, the ADC is equipped with front-end peak and RMS power detectors and alarm functions to support external automatic gain control (AGC) algorithms.
The ADC32RF44 supports the JESD204B serial interface with subclass 1-based deterministic latency using data rates up to 12.5 Gbps with up to four lanes per ADC. The device is offered in a 72-pin VQFN package (10 mm × 10 mm) and supports the industrial temperature range (–40°C to +85°C).
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | ADC32RF44 Dual-Channel, 14-Bit, 2.6-GSPS, Analog-to-Digital Converter datasheet (Rev. A) | PDF | HTML | 2017年 3月 23日 |
EVM User's guide | ADC32RFxxEVM User's Guide (Rev. E) | 2020年 1月 31日 | ||
Application note | Spurs Analysis in the RF Sampling ADC | 2018年 2月 9日 | ||
Application note | Configuration Files for ADC32RF45, ADC32RF83, and ADC32RF80 (Rev. B) | 2017年 9月 5日 |
設計與開發
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SBAC187 — KCU105 + ADC32RF44 Design Firmware
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SBAC148 — ADC32RFxxEVM SPI GUI Installer
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FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
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VQFNP (RMP) | 72 | Ultra Librarian |
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