韌體
產品規格表
ADC12DJ3200
- ADC core:
- 12-bit resolution
- Up to 6.4 GSPS in single-channel mode
- Up to 3.2 GSPS in dual-channel mode
- Performance specifications:
- Noise floor (no signal, VFS = 1.0 VPP-DIFF):
- Dual-channel mode: –151.8 dBFS/Hz
- Single-channel mode: –154.6 dBFS/Hz
- HD2, HD3: –65 dBc up to 3 GHz
- Noise floor (no signal, VFS = 1.0 VPP-DIFF):
- Buffered analog inputs with VCMI of 0 V:
- Analog input bandwidth (–3 dB): 8.0 GHz
- Usable input frequency range: >10 GHz
- Full-scale input voltage (VFS, default): 0.8 VPP
- Analog input common-mode (VICM): 0 V
- Noiseless aperture delay (TAD) adjustment:
- Precise sampling control: 19-fs step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204B serial data interface:
- Supports subclass 0 and 1
- Maximum lane rate: 12.8 Gbps
- Up to 16 lanes allows reduced lane rate
- Digital down-converters in dual-channel mode:
- Real output: DDC bypass or 2x decimation
- Complex output: 4x, 8x, or 16x decimation
- Four independent 32-Bit NCOs per DDC
- Power consumption: 3 W
- Power supplies: 1.1 V, 1.9 V
The ADC12DJ3200 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ3200 can sample up to 3200 MSPS and up to 6400 MSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ3200 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features, including noiseless aperture delay (TAD) adjustment and SYSREF windowing, simplify system design for phased array radar and MIMO communications. Optional digital down converters (DDCs) in dual-channel mode allow for reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex decimation modes only).
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開發板
ADC12DJ3200EVM — ADC12DJ3200 12 位元雙路 3.2 GSPS 或單路 6.4 GSPS 射頻取樣 ADC 評估模組
ADC12DJ3200 評估模組 (EVM) 可用於評估裝置 ADC12DJ3200。ADC12DJ3200 是是一款具有緩衝類比輸入的低功耗、12 位元、雙 3.2-GSPS/單 6.4-GSPS、射頻取樣類比轉數位轉換器 (ADC)，是具可編程 NCO 和降取設定 (包括未降取的 12 位元和 8 位元 ADC 輸出) 的整合式數位降壓轉換器，並且具有 JESD204B 介面。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。EVM 隨附 LMX2582 時鐘合成器和 LMK04828 JESD204B 時鐘產生器，可配置為提供適用於完整 JESD204B 子類別 1 (...)
使用指南: PDF
開發板
ABACO-3P-FMC134 — Abaco Systems ® 直接射頻轉換 4 通道 3.2-GSPS 或 2 通道 6.4-GSPS ADC FPGA 夾層介面卡
The Abaco FMC134 provides four 12-bit 3.2-GSPS or two 12-bit 6.4-GSPS analog-to-digital converters (ADCs). The module highlights the Texas Instruments ADC12DJ3200 two-channel, 12-bit, 3.2-GSPS ADC (two) in a daughtercard with an FPGA mezzanine card (FMC) connector using the JEDEC JESD204B (...)
開發板
ANNAP-3P-WWDM60 — Annapolis Microsystems 4 通道 ADC、2 通道 DAC FPGA 夾層介面卡，最高可達 10GSPS
This high performance WILD FMC+ DM60 ADC & DAC has two input bandwidth options, internal sample clock options and internal 10MHz reference clock options. The WWDM60 has a choice of speed grades that utilize the ADC12DJ2700, ADC12DJ3200 and ADC12DJ5200RF up to 10GSPS. It allows for ADC and DAC (...)
開發板
PENTEK-3P-71141-XMC — Pentek 型號 71141 1 通道 6.4 GHz 或 2 通道 3.2 GHz ADC、2 通道 6.4 GHz DAC Kintex UltraScale - XMC
Accelerate your project by considering a complete off-the-shelf board that utilizes the ADC12DJ3200. The Pentek Jade® Model 71141 is an ideal radar and software radio interface solution that includes the Texas Instrument's ADC12DJ3200 ADC. The solution from Pentek provides a one-channel 6.4GSPS (...)
韌體
SLVC698 — Xilinx KCU105 + ADC12DJ3200 JMODE0/JMODE2 Design Firmware
支援產品和硬體
產品
高速 ADC (≥10 MSPS)
硬體開發
開發板
韌體
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
支援產品和硬體
產品
高速 DAC (>10 MSPS)
高速 ADC (≥10 MSPS)
RF 收發器
RF 接收器
RF 發射器
開發模組 (EVM) 的 GUI
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.20
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
支援產品和硬體
產品
高速 DAC (>10 MSPS)
高速 ADC (≥10 MSPS)
超音波 AFE
RF 收發器
RF 接收器
RF 發射器
硬體開發
開發板
軟體
支援軟體
開發模組 (EVM) 的 GUI
SLAC745 — ADC12DJxx00 GUI
支援產品和硬體
產品
高速 ADC (≥10 MSPS)
硬體開發
開發板
模擬型號
ADC12DJ3200 and ADC12DJ3200QML-SP IBIS and IBIS-AMI Model
SLVMDV3.ZIP (47828 KB) - IBIS-AMI Model
計算工具
FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
支援產品和硬體
產品
高速 ADC (≥10 MSPS)
RF 收發器
RF 接收器
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
TIDA-01021 — 適用於 DSO、雷達和 5G 無線測試儀的多通道 JESD204B 15 GHz 時鐘參考設計
High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 (...)
參考設計
TIDA-01022 — 適用於 DSO、雷達和 5G 無線測試系統的靈活 3.2-GSPS 多通道 AFE 參考設計
This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
參考設計
TIDA-01023 — 適用於雷達和 5G 無線測試器的高通道計數 JESD204B 時鐘產生參考設計
High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
參考設計
TIDA-01024 — 適用於雷達和 5G 無線測試器的高通道計數 JESD204B 菊輪鍊時鐘參考設計
High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
參考設計
TIDA-01027 — 在 12.8 GSPS 資料採集系統中發揮最大效能的低雜訊電源供應參考設計
This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
參考設計
TIDA-01028 — 適用於高速示波器和寬頻帶數位器的 12.8-GSPS 類比前端參考設計
This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
參考設計
TIDA-010122 — 適用於多通道射頻系統的參考設計同步數據轉換器 DDC 和 NCO 功能
此參考設計可解決與新興 5G 適配應用相關，例如大規模多輸入多輸出 (mMIMO)、相位陣列雷達與通訊酬載等應用相關的同步設計挑戰。一般 RF 前端包含天線、低雜訊放大器 (LNA)、混波器、類比網域中的本地振盪器 (LO) 及類比轉數位轉換器、數值控制振盪器 (NCO) 和數位降轉換器 (DDC)。為了達到整體系統同步化，這些數位區塊必須與系統時鐘同步。本參考設計採用 ADC12DJ3200 資料轉換器，透過同步處理晶片內建 NCO 與 SYNC ~ 並使用無雜訊孔徑延遲調整 (tAD 調整) 功能，在多個接收器之間達到小於 5-ps 的頻道間偏斜的效果，以進一步降低偏斜。此設計也具備搭載 (...)
參考設計
TIDA-01442 — 適用於 L、S、C 和 X 波段的直接射頻取樣雷達接收器參考設計
此參考設計利用 ADC12DJ3200 評估模組 (EVM)，展示用於以 HF、VHF、UHF、L、S、C 和 X 波段的一部分操作雷達的直接射頻取樣接收器。類比轉數位轉換器 (ADC) 的廣泛類比輸入頻寬與高取樣率 (6.4 GSPS)，採用單或雙 ADC 提供多頻段範圍。ADC 的直接射頻取樣功能，可透過省去數個向下轉換階段減少零組件數量，進而降低整體系統複雜性。
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
| FCCSP (ZEG) | 144 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。