ADS42JB69
- Dual-Channel ADCs
- 14- and 16-Bit Resolution
- Maximum Clock Rate: 250 MSPS
- JESD204B Serial Interface
- Subclass 0, 1, 2 Compliant
- Up to 3.125 Gbps
- Two and Four Lanes Support
- Analog Input Buffer with High-Impedance Input
- Flexible Input Clock Buffer:
Divide-by-1, -2, and -4 - Differential Full-Scale Input: 2 VPP and 2.5 VPP
(Register Programmable) - Package: 9-mm × 9-mm VQFN-64
- Power Dissipation: 850 mW/Ch
- Aperture Jitter: 85 fS rms
- Internal Dither
- Channel Isolation: 100 dB
- Performance:
- fIN = 170 MHz at 2 VPP, –1 dBFS
- SNR: 73.3 dBFS
- SFDR: 93 dBc for HD2, HD3
- SFDR: 100 dBc for Non HD2, HD3
- fIN = 170 MHz at 2.5 VPP, –1 dBFS
- SNR: 74.7 dBFS
- SFDR: 89 dBc for HD2, HD3 and
95 dBc for Non HD2, HD3
- fIN = 170 MHz at 2 VPP, –1 dBFS
The ADS42JB69 and ADS42JB49 are high-linearity, dual-channel, 16- and 14-bit, 250-MSPS, analog-to-digital converters (ADCs). These devices support the JESD204B serial interface with data rates up to
3.125 Gbps. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy making it easy to drive analog inputs up to very high input frequencies. A sampling clock divider allows more flexibility for system clock architecture design. The devices employ internal dither algorithms to provide excellent spurious-free dynamic range (SFDR) over a large input frequency range.
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設計與開發
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ADS42JB69EVM — ADS42JB69 雙通道、16 位元、250 MSPS 類比轉數位轉換器評估模組
The ADS42JB69EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS42JB69 and LMK04828 clock jitter cleaner. The ADS42JB69 is a low power, 16-bit, 250-MSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)
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The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VQFN (RGC) | 64 | Ultra Librarian |
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- MTBF/FIT 估算值
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- 進行中持續性的可靠性監測
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