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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS54J69

現行

雙通道、16 位元、500-MSPS 類比轉數位轉換器 (ADC)

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ADC3669 現行 具有 LVDS 介面和高達 32768x 降取的 16 位元、雙通道、500MSPS ADC Lower power, higher SNR, smaller package size, LVDS interface

ADS54J69

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.2 ENOB (Bits) 12 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 500 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1.9 Power consumption (typ) (mW) 2700 Architecture Pipeline SNR (dB) 74.2 ENOB (Bits) 12 SFDR (dB) 95 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 16-Bit Resolution, Dual-Channel, 500-MSPS ADC
  • Idle Channel Noise Floor: –159 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 73 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 93 dBc
    • SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone)
  • Spectral Performance (fIN = 310 MHz at –1 dBFS):
    • SNR: 71.7 dBFS
    • NSD: –155.7 dBFS/Hz
    • SFDR: 81 dBc
    • SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Decimate-by-2 Filter
  • JESD204B Interface with Subclass 1 Support:
    • 1 Lane per ADC at 10.0 Gbps
    • 2 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/ch at 500 MSPS
  • 72-Pin VQFNP Package (10 mm × 10 mm)
  • 16-Bit Resolution, Dual-Channel, 500-MSPS ADC
  • Idle Channel Noise Floor: –159 dBFS/Hz
  • Spectral Performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 73 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 93 dBc
    • SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone)
  • Spectral Performance (fIN = 310 MHz at –1 dBFS):
    • SNR: 71.7 dBFS
    • NSD: –155.7 dBFS/Hz
    • SFDR: 81 dBc
    • SFDR: 94 dBc (Except HD2, HD3, and Interleaving Tone)
  • Channel Isolation: 100 dBc at fIN = 170 MHz
  • Input Full-Scale: 1.9 VPP
  • Input Bandwidth (3 dB): 1.2 GHz
  • On-Chip Dither
  • Integrated Decimate-by-2 Filter
  • JESD204B Interface with Subclass 1 Support:
    • 1 Lane per ADC at 10.0 Gbps
    • 2 Lanes per ADC at 5.0 Gbps
    • Support for Multi-Chip Synchronization
  • Power Dissipation: 1.35 W/ch at 500 MSPS
  • 72-Pin VQFNP Package (10 mm × 10 mm)

The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.

The ADS54J69 is a low-power, wide-bandwidth, 16-bit, 500-MSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting one or two lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel is directly connected to a wideband digital down-converter (DDC) block. The ADS54J69 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.
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* Data sheet ADS54J69 Dual-Channel, 16-Bit, 500-MSPS, Analog-to-Digital Converter datasheet (Rev. C) PDF | HTML 2017年 1月 20日

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開發板

ADS54J69EVM — ADS54J69 雙通道、16 位元、500 MSPS 類比轉數位轉換器評估模組

ADS54J69EVM 是一種評估模組 (EVM)，可用於評估德州儀器 (TI) 的 ADS54J69 和 LMK04828 時鐘抖動清除器。ADS54J69 是一款低功耗、16 位元、500-MSPS 類比轉數位轉換器 (ADC)，擁有具備 JESD204B 介面的緩衝類比輸入和輸出。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。LMK04828 為完整的 JESD204B 子類 1 計時解決方案，提供超低抖動和相位雜訊 ADC 取樣時鐘，以及系統參考時鐘和裝置取樣時鐘。

ADS54J69 和 LMK04828 是透過易於使用的軟體 GUI (...)

使用指南: PDF
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韌體

TI204C-IP — Request for JESD204 rapid design IP

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)

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開發模組 (EVM) 的 GUI

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

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開發模組 (EVM) 的 GUI

SLAC594 — ADS54Jxx EVM GUI

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模擬型號

ADS54J69 IBIS Model

SBAM257.ZIP (43 KB) - IBIS Model
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模擬型號

ADS54J69_IBIS_AMI_MODEL

SBAM258.ZIP (1953 KB) - IBIS-AMI Model
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計算工具

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI 是有助於評估類比電路功能的設計和模擬環境。這款全功能設計和模擬套件使用 Cadence® 的類比分析引擎。PSpice for TI 包括業界最大的模型庫之一，涵蓋我們的類比和電源產品組合，以及特定類比行為模型，且使用無需支付費用。

PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前，建立完整的終端設備設計和解決方案原型，進而縮短上市時間並降低開發成本。 

在 PSpice for TI 設計與模擬工具中，您可以搜尋 TI (...)
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VQFNP (RMP) 72 Ultra Librarian
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