韌體
產品規格表
ADC12DJ5200RF
- ADC core:
- 12-bit resolution
- Up to 10.4GSPS in single-channel mode
- Up to 5.2GSPS in dual-channel mode
- Performance specifications:
- Noise floor (–20dBFS, VFS = 1VPP-DIFF):
- Dual-channel mode: –151.8dBFS/Hz
- Single-channel mode: –154.4dBFS/Hz
- ENOB (dual channel, FIN = 2.4GHz): 8.6 Bits
- Noise floor (–20dBFS, VFS = 1VPP-DIFF):
- Buffered analog inputs with VCMI of 0V:
- Analog input bandwidth (–3dB): 8GHz
- Usable input frequency range: > 10GHz
- Full-scale input voltage (VFS, default): 0.8VPP
- Noiseless aperture delay (tAD) adjustment:
- Precise sampling control: 19fs Step
- Simplifies synchronization and interleaving
- Temperature and voltage invariant delays
- Easy-to-use synchronization features:
- Automatic SYSREF timing calibration
- Timestamp for sample marking
- JESD204C serial data interface:
- Maximum lane rate: 17.16Gbps
- Support for 64b/66b and 8b/10b encoding
- 8b/10b modes are JESD204B compatible
- Optional digital down-converters (DDC):
- 4x, 8x, 16x and 32x complex decimation
- Four independent 32-Bit NCOs per DDC
- Peak RF Input Power (Diff): +26.5dBm (+ 27.5dBFS, 560x fullscale power)
- Programmable FIR filter for equalization
- Power consumption: 4W
- Power supplies: 1.1V, 1.9V
The ADC12DJ5200RF device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10GHz. ADC12DJ5200RF can be configured as a dual-channel, 5.2GSPS ADC or single-channel, 10.4GSPS ADC. Support of a useable input frequency range of up to 10GHz enables direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.
The ADC12DJ5200RF uses a high-speed JESD204C output interface with up to 16 serialized lanes supporting up to 17.16Gbps line rate. Deterministic latency and multi-device synchronization is supported through JESD204C subclass-1. The JESD204C interface can be configured to trade-off line rate and number of lanes. Both 8b/10b and 64b/66b data encoding schemes are supported. 64b/66b encoding supports forward error correction (FEC) for improved bit error rates. The interface is backwards compatible with JESD204B receivers.
Innovative synchronization features, including noiseless aperture delay adjustment and SYSREF windowing, simplify system design for multi-channel applications. Optional digital down converters (DDCs) are available to provide digital conversion to baseband and to reduce the interface rate. A programmable FIR filter allows on-chip equalization.
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開發板
ADC12DJ5200RFEVM — ADC12DJ5200RF 射頻取樣 12 位元雙路 5.2GSPS 或單路 10.4GSPS ADC 評估模組
ADC12DJ5200RF 評估模組 (EVM) 可用於評估裝置 ADC12DJ5200RF。ADC12DJ5200RF 是一款低功耗、12 位元、雙路 5.2GSPS/單路 10.4GSPS、射頻取樣類比轉數位轉換器 (ADC)，具有緩衝類比輸入、整合式數位降壓轉換器，附帶可編程 NCO 和降取設定 (包括未降取的 12 位元和 8 位元 ADC 輸出)，並且具有 JESD204B/C 介面。此 EVM 具有變壓器耦合類比輸入，可適應廣泛的訊號來源和頻率。
EVM 隨附 LMX2582 時鐘合成器和 LMK04828 JESD204B/C 時鐘產生器，可配置為提供適用於完整 (...)
開發板
TRF1208-ADC12DJ5200RFEVM — 適用於具有 ADC12DJ5200RF 的高速射頻取樣全差動放大器的 TRF1208 評估模組
TRF1208-ADC12DJ5200RFEVM 用於評估 ADC12DJ5200RF 和 ADC12DJ4000RF 類比轉數位轉換器 (ADC)。ADC12DJ5200RF 是雙通道 12 位元 ADC，可在雙通道模式下以高達 5.2 GSPS，或在單通道模式下以 10.4 GSPS 的取樣速率運作。ADC12DJ4000RF 是雙通道 12 位元 ADC，可在雙通道模式下以高達 4 GSPS，或在單通道模式下以 8 GSPS 的取樣速率運作。
開發板
TSW14J59EVM — TSW14J59 評估模組
TSW14J59 評估模組 (EVM) 是新一代資料擷取卡，可用來評估全新 TI JESD204C_B 系列高速類比轉數位轉換器 (ADC)、高速數位轉類比轉換器 (DAC) 和類比前端 (AFE) 的性能。
安裝 Kintex Ultrascale+® FPGA 並使用 JESD204B/C IP 解決方案後，TSW14J59 可動態配置為支援所有通道速度，範圍從 1Gbps 至 32Gbps，從 1 至 16 通道。
搭配隨附的 High-Speed Data Converter Pro (HSDC Pro) 資料擷取分析及軟體程式，是一套完整系統，可擷取並評估使用 JESD204B 及/或 (...)
開發板
ANNAP-3P-WWDM60 — Annapolis Microsystems 4 通道 ADC、2 通道 DAC FPGA 夾層介面卡，最高可達 10GSPS
This high performance WILD FMC+ DM60 ADC & DAC has two input bandwidth options, internal sample clock options and internal 10MHz reference clock options. The WWDM60 has a choice of speed grades that utilize the ADC12DJ2700, ADC12DJ3200 and ADC12DJ5200RF up to 10GSPS. It allows for ADC and DAC (...)
韌體
TI204C-IP — Request for JESD204 rapid design IP
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
支援產品和硬體
產品
高速 DAC (>10 MSPS)
高速 ADC (≥10 MSPS)
RF 收發器
RF 發射器
開發模組 (EVM) 的 GUI
DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.20
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
支援產品和硬體
產品
高速 DAC (>10 MSPS)
高速 ADC (≥10 MSPS)
超音波 AFE
RF 收發器
RF 接收器
RF 發射器
硬體開發
開發板
軟體
支援軟體
計算工具
FREQ-DDC-FILTER-CALC — RF-Sampling Frequency Planner, Analog Filter, and DDC Excel Calculator
This Excel calculator provides system designers a way to simplify the design and debugging of direct RF-sampling receivers. It offers three functions: frequency planning, analog filtering, and decimation filter spur location.
In the concept phase, a frequency-planning tool enables fine tuning of (...)
支援產品和硬體
產品
高速 ADC (≥10 MSPS)
RF 收發器
RF 接收器
設計工具
SLVRBH0 — ADC12DJ5200RF-EVM Assembly Package
支援產品和硬體
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
TIDA-01027 — 在 12.8 GSPS 資料採集系統中發揮最大效能的低雜訊電源供應參考設計
This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
參考設計
TIDA-01028 — 適用於高速示波器和寬頻帶數位器的 12.8-GSPS 類比前端參考設計
This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
參考設計
TIDA-010128 — 適用於 12 位元數位器的可擴充 20.8 GSPS 參考設計
This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
| FCCSP (ZEG) | 144 | Ultra Librarian |
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建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。