The terminal-compatible DAC37J84/DAC38J84 family is a low power, 16-bit, quad-channel, 1.6/2.5 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | Quad-Channel, 16-Bit, 1.6/2.5 GSPS, Digital-to-Analog Converters datasheet (Rev. B) | 2014年 3月 24日 | |
| Application note | DAC3xJ8x Device Initialization and SYSREF Configuration | 2017年 9月 27日 | ||
| EVM User's guide | DAC3XJ8XEVM User's Guide (Rev. B) | 2016年 4月 28日 | ||
| EVM User's guide | TSW3XJ8XEVM User's Guide (Rev. B) | 2016年 3月 9日 | ||
| Application note | System solution for avionics & defense | 2015年 9月 23日 | ||
| White paper | Ready to make the jump to JESD204B? White Paper (Rev. B) | 2015年 3月 19日 | ||
| EVM User's guide | Altera JESD204B IP Core and TI DAC37J84 Hardware Checkout Report (Rev. A) | 2014年 9月 15日 | ||
| Design guide | Analog Interfacing Networks for DAC348x and Modulators (TIDA-00077) (Rev. A) | 2013年 8月 14日 | ||
| Application note | High Speed, Digital-to-Analog Converters Basics (Rev. A) | 2012年 10月 23日 |
如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。
The DAC3XJ8XEVM is an evaluation module (EVM) designed to evaluate the DAC3XJ8X family of high-speed, JESD204B interface DACs (DAC37J82, DAC37J84, DAC38J82, DAC38J84). The EVM includes an onboard clocking solution (LMK04828), transformer coupled outputs, full power solution, and easy-to-use (...)
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。
The design resource accessed as www.ti.com/lit/zip/slwc107 or www.ti.com/lit/xx/slwc107w/slwc107w.zip has been migrated to a new user experience at www.ti.com/tool/download/SLWC107. Please update any bookmarks accordingly.