開發模組 (EVM) 的 GUI
產品規格表
DAC39J84
- Resolution: 16-Bit
- Maximum Sample Rate: 2.8GSPS
- Maximum Input Data Rate: 1.25GSPS
- JESD204B Interface
- 8 JESD204B Serial Input Lanes
- 12.5 Gbps Maximum Bit Rate per Lane
- Subclass 1 Multi-DAC Synchronization
- On-Chip Very Low Jitter PLL
- Selectable 1x –16x Interpolation
- Independent Complex Mixers with 48-bit NCO/
or ±n×Fs/8 - Wideband Digital Quadrature Modulator Correction
- Sinx/x Correction Filters
- Fractional Sample Group Delay Correction
- Multi-Band Mode: Digital Summation of Independent
Complex Signals - 3/4-Wire Serial Control Bus (SPI)
- Integrated Temperature Sensor
- JTAG Boundary Scan
- Pin-Compatible with Quad-Channel DAC37J84/
DAC38J84 Family - Power Dissipation: 1.8W at 2.8GSPS
- Package: 10 mm × 10 mm, 144-Ball Flip-Chip BGA
The DAC39J84 is a low power, 16-bit, quad-channel, 2.8 GSPS digital to analog converter (DAC) with JESD204B interface.
Digital data is input to the device through 1, 2, 4 or 8 configurable serial JESD204B lanes running up to 12.5 Gbps with on-chip termination and programmable equalization. The interface allows JESD204B Subclass 1 SYSREF based deterministic latency and full synchronization of multiple devices.
The device includes features that simplify the design of complex transmit architectures. Fully bypassable 2x to 16x digital interpolation filters with over 90 dB of stop-band attenuation simplify the data interface and reconstruction filters. An on-chip 48-bit Numerically Controlled Oscillator (NCO) and independent complex mixers allow flexible and accurate carrier placement.
A high-performance low jitter PLL simplifies clocking of the device without significant impact on the dynamic range. The digital Quadrature Modulator Correction (QMC) and Group Delay Correction (QDC) enable complete IQ compensation for gain, offset, phase, and group delay between channels in direct up-conversion applications. A programmable Power Amplifier (PA) protection mechanism is available to provide PA protection in cases when the abnormal power behavior of the input data is detected.
技術文件
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檢視所有 4 | 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | DAC39J84 Quad-Channel, 16-Bit, 2.8 GSPS, Digital-to-Analog Converter with 12.5 Gbps JESD204B Interface datasheet (Rev. A) | PDF | HTML | 2015年 1月 26日 |
| Application note | DAC3xJ8x Device Initialization and SYSREF Configuration | 2017年 9月 27日 | ||
| EVM User's guide | DAC3XJ8XEVM User's Guide (Rev. B) | 2016年 4月 28日 | ||
| Application note | System solution for avionics & defense | 2015年 9月 23日 |
設計與開發
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開發板
DAC39J84EVM — DAC39J84 四通道、16 位元、2.8 GSPS、1x-16x 內插數位轉類比轉換器 EVM
DAC39J84EVM 是評估模組 (EVM)，其設計旨在評估 DAC39J84 高速 JESD204B 介面 DAC。EVM 包括板載計時解決方案 (LMK04828)、變壓器耦合輸出、完整電源解決方案，以及易於使用的軟體 GUI 和 USB 介面。
DAC39J84EVM 旨在與德州儀器的 JESD204B 模式產生器卡 TSW14J56EVM 無縫合作，其透過高速數據轉換器 Pro (HSDCPro) 軟體工具進行高速數據轉換器評估。DAC3XJ8XEVM 也設計來與包含 FMC 連接器的一流 FPGA 廠商的許多開發套件搭配使用。
使用指南: PDF
開發板
ABACO-3P-FMC120 — Abaco Systems ® 4 通道 16 位元 ADC/DAC 輸入 /輸出 FPGA 夾層介面卡
The Abaco FMC120 provides four 16-bit analog-to-digital converters (ADCs) and four 16-bit digital-to-analog converters (DACs). The module highlights two products from Texas Instruments: the ADS54J60 two-channel, 16-bit, 1-GSPS ADC (two) and the DAC39J84 four-channel, 16-bit, 2.8-GSPS DAC (one) in a (...)
韌體
TI-JESD204-IP — JESD204 快速設計 IP，適用連接到 TI 高速資料轉換器的 FPGA
The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
TIDA-00996 — 同步多發送器參考設計：多個 DAC 實現時間對準的方法
To further increase the range, data rate, and reliability of modern mobile communications systems, system designers continue to place more emphasis on multiple-antenna transmitter systems to achieve combinations of spatial diversity and spatial multiplexing. Such implementations can further (...)
參考設計
TIDA-00335 — 高頻寬、高頻發射器參考設計
This design illustrates the circuit modifications required to support high bandwidth and high frequency applications using current source DACs like the DAC38J84 with the TRF3704 modulator. The TRF3704 is a 6 GHz modulator capable of supporting wide BB bandwidths. The (...)
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| FCCSP (AAV) | 144 | Ultra Librarian |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。