ADS5295
- Maximum Sample Rate: 100 MSPS
- Designed for Low Power:
- 80 mW per channel at 100 MSPS
- SNR: 70.6 dBFS
- SFDR: 85 dBc at 10 MHz, 100 MSPS
- Serial LVDS ADC Data Outputs:
- One- or Two-Wire Serialized LVDS Outputs per Channel
- One-Wire Interface:
Up to 80 MSPS Sample Rate - Two-Wire Interface:
Up to 100 MSPS Sample Rate
- Digital Processing Block:
- Programmable FIR Decimation Filter and Oversampling to Minimize Harmonic Interference
- Programmable IIR High-Pass Filter to Minimize DC Offset
- Programmable Digital Gain: 0 dB to 12 dB
- Low-Frequency Noise Suppression Mode
- Programmable Mapping Between ADC Input Channels and LVDS Output Pins
- Channel Averaging Mode
- Variety of LVDS Test Patterns to Verify
Data Capture by FPGA or Receiver - Package: 12-mm × 12-mm QFP-80
The ADS5295 is a low-power, 12-bit, 100-MSPS, 8-channel analog-to-digital converter (ADC). Low power consumption and integration of multiple channels in a compact package make the device attractive for very high channel count data acquisition systems.
Serial low-voltage differential signaling (LVDS) outputs reduce the number of interface lines and enable high system integration. The ADC digital data can be output over one or two wires of LVDS pins per channel. At high sample rates, the two-wire interface helps keep the serial data rate low, allowing low-cost field-programmable gate array (FPGA)-based receivers to be used.
The device integrates an internal reference trimmed to accurately match across devices. Best performance is expected to be achieved through the internal reference mode. However, the device can be driven with external references as well.
Several digital functions that are commonly used in systems are included in the device. These functions include a low-frequency suppression mode, digital filtering options, and programmable mapping.
For low input frequency applications, the low-frequency noise suppression mode enables noise suppression at low frequencies and improves signal-to-noise ratio (SNR) in the 1-MHz band near dc by approximately 3 dB. Digital filtering options include low-pass, high-pass, and band-pass digital filters, as well as dc offset removal filters. The device also provides programmable mapping of the LVDS output pins and analog input channels. For applications where the 12-bit ADC SNR is not required, the ADS5295 can be configured as an 8-channel, 10-bit ADC with 10x LVDS serialization to reduce the output data rate.
The device is available in a 12-mm × 12-mm QFP-80 package. The ADS5295 is specified over the –40°C to +85°C operating temperature range.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 12-Bit, 100-MSPS, 8-Channel Analog-to-Digital Converter datasheet | 2012年 12月 10日 | |
Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015年 5月 22日 | ||
Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013年 7月 19日 | ||
Application note | Understanding Serial LVDS Capture in High-Speed ADCs | 2013年 7月 10日 | ||
User guide | ADS5295, 8-Channel ADC Evaluation Module | 2012年 4月 30日 |
設計與開發
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ADS5295EVM — ADS5295 評估模組
ADS5295 評估模組 (EVM) 展示了低功率、12 位元、100MSPS、八通道類比數位轉換器 (ADC) ADS5295 的性能。低功率及整合多通道至小巧封裝的特色,讓 ADS5295 對極高通路計數的資料擷取系統深具吸引力。序列低電壓差動訊號 (LVDS) 輸出可減少介面線路並提供高系統整合度。ADC 數位資料可在各通道 LVDS 接腳的一或兩條線路上輸出。在高取樣率時,雙線路介面有助於保持低序列資料速率,因此可以使用 FPGA 架構接收器。該裝置整合內部參考修整,可在眾多裝置中精準比對。透過內部參考模式,可達到最佳性能。該裝置也可透過外部參考驅動。
ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
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封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
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HTQFP (PFP) | 80 | Ultra Librarian |
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