ADS61B23
- Maximum Sample Rate: 80 MSPS
- 12-bit Resolution with No Missing Codes
- Buffered Analog Inputs with
- Very Low Input Capacitance (< 2 pF)
- High DC Resistance (5 k)
- 82 dBc SFDR and 70 dBFS SNR
(-1 BFS or 1.8 Vpp input) - 85 dBc SFDR (-6 dBFS or 1 Vpp input)
- 3.5 dB Coarse Gain and up to 6 dB Programmable Fine Gain for SNR and SFDR Trade-Off
- Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
- Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs and Clock Amplitude Down to 400 mVPP
- Clock Duty Cycle Stabilizer
- Internal Reference with Support for External Reference
- External Decoupling Eliminated for References
- Programmable Output Clock Position and Drive Strength to Ease Data Capture
- 3.3 V Analog and 1.8 V to 3.3 V Digital Supply
- 32-pin QFN Package (5 mm × 5 mm)
- Pin Compatible 12-Bit Family (ADS612X)
- Temperature range -40°C to 85°C
- APPLICATIONS
- Wireless Communications Infrastructure
- Software Defined Radio
- Power Amplifier Linearization
- 802.16d/e
- Test and Measurement Instrumentation
- High Definition Video
- Medical Imaging
- Radar Systems
ADS61B23 is a 12-bit A/D converter (ADC) with a maximum sampling frequency of 80 MSPS. It combines high performance and low power consumption in a compact 32-QFN package. The analog inputs use buffers to isolate the switching transients of the internal sample & hold from the external driving circuit. The buffered inputs present very low input capacitance (< 2pF) & wide bandwidth. This makes it easy to drive them at high input frequencies, compared to an ADC without the input buffers.
ADS61B23 has coarse and fine gain options that are used to improve SFDR performance at lower full-scale analog input ranges.
The digital data outputs are parallel CMOS or DDR LVDS (Double Data Rate). Several features exist to ease data capturecontrols for output clock position and output buffer drive strength, plus LVDS current and internal termination programmability.
The output interface type, gain, and other functions are programmed using a 3-wire serial interface. Alternatively, some of these functions are configured using dedicated parallel pins so the device starts in the desired state after power-up.
ADS61B23 includes internal references, while eliminating the traditional reference pins and associated external decoupling. External reference mode is also supported.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | 12Bits 80MSPS ADC with Buffered Analog Inputs datasheet | 2008年 2月 7日 | |
Application note | Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) | 2015年 5月 22日 | ||
Application note | Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) | 2013年 7月 19日 | ||
Application note | Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) | 2010年 9月 10日 | ||
Application note | Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio | 2009年 4月 28日 | ||
Application note | CDCE62005 as Clock Solution for High-Speed ADCs | 2008年 9月 4日 | ||
Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 2008年 6月 8日 | ||
Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 2008年 6月 2日 | ||
Application note | QFN Layout Guidelines | 2006年 7月 28日 |
設計與開發
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ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
支援產品和硬體
產品
精密度運算放大器 (Vos<1mV)
一般用途運算放大器
音訊運算放大器
轉阻放大器
高速運算放大器 (GBW ≥ 50 MHz)
功率運算放大器
視訊放大器
線路驅動器
轉導放大器與雷射驅動器
全差分放大器
精確 ADC
生物感測 AFE
高速 ADC (≥10 MSPS)
觸控式螢幕控制器
差分放大器
儀器放大器
音訊線路接收器
類比電流感測放大器
數位電源監測器
配備整合式分流電阻器的類比電流感測放大器
具整合式分流電阻器的數位電源監測器
晶粒與晶圓服務
RF 接收器
RF 發射器
SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)
支援產品和硬體
產品
高速 ADC (≥10 MSPS)
RF 接收器
硬體開發
開發板
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VQFN (RHB) | 32 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。