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數據轉換器
類比轉數位轉換器 (ADC)
高速 ADC (≥10 MSPS)

ADS61JB46

現行

14 位元 160-MSPS 類比轉數位轉換器 (ADC)

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產品規格表

ADS61JB46

現行
產品規格表 立即訂購

產品詳細資料

Sample rate (max) (Msps) 160 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204A Analog input BW (MHz) 480 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 583 Architecture Pipeline SNR (dB) 75 ENOB (bit) 11.7 SFDR (dB) 77 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 160 Resolution (Bits) 14 Number of input channels 1 Interface type JESD204A Analog input BW (MHz) 480 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 583 Architecture Pipeline SNR (dB) 75 ENOB (bit) 11.7 SFDR (dB) 77 Operating temperature range (°C) -40 to 85 Input buffer Yes
VQFN (RHA) 40 36 mm² 6 x 6
  • Output Interface:
    • Single-Lane and Dual-Lane Interfaces
    • Maximum Data Rate: 3.125 Gbps
    • Meets JEDEC JESD204A Specification
    • CML Outputs with Current Programmable from 2 mA to 32 mA
  • Power Dissipation:
    • 583 mW at 160 MSPS in Dual-Lane Mode
    • Power Scales Down with Clock Rate
  • Input Interface: Buffered Analog Inputs
  • SNR at 185-MHz IF: –72.7 dBFS
  • Analog Input Dynamic Range: 2 VPP
  • Reference Support:
    External and Internal (Trimmed)
  • Supply:
    • Analog and Digital: 1.8 V
    • Input Buffer: 3.3 V
  • Programmable Digital Gain: 0 dB to 6 dB
  • Output: Straight Offset Binary or
    Twos Complement
  • Package: 6-mm × 6-mm QFN-40
  • Output Interface:
    • Single-Lane and Dual-Lane Interfaces
    • Maximum Data Rate: 3.125 Gbps
    • Meets JEDEC JESD204A Specification
    • CML Outputs with Current Programmable from 2 mA to 32 mA
  • Power Dissipation:
    • 583 mW at 160 MSPS in Dual-Lane Mode
    • Power Scales Down with Clock Rate
  • Input Interface: Buffered Analog Inputs
  • SNR at 185-MHz IF: –72.7 dBFS
  • Analog Input Dynamic Range: 2 VPP
  • Reference Support:
    External and Internal (Trimmed)
  • Supply:
    • Analog and Digital: 1.8 V
    • Input Buffer: 3.3 V
  • Programmable Digital Gain: 0 dB to 6 dB
  • Output: Straight Offset Binary or
    Twos Complement
  • Package: 6-mm × 6-mm QFN-40

The ADS61JB46 is a high-performance, low-power, single-channel, analog-to-digital converter with an integrated JESD204A output interface. Available in a 6-mm × 6-mm QFN package, with both single-lane and dual-lane output modes, the device offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per the IEEE standard 802.3-2002 part 3, clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample-and-hold switches and higher and more consistent input impedance.

The device is specified over the industrial temperature range (–40°C to +85°C).

The ADS61JB46 is a high-performance, low-power, single-channel, analog-to-digital converter with an integrated JESD204A output interface. Available in a 6-mm × 6-mm QFN package, with both single-lane and dual-lane output modes, the device offers an unprecedented level of compactness. The output interface is compatible to the JESD204A standard, with an additional mode (as per the IEEE standard 802.3-2002 part 3, clause 36.2.4.12) to interface seamlessly to the TI TLK family of SERDES transceivers. Equally impressive is the inclusion of an on-chip analog input buffer, providing isolation between the sample-and-hold switches and higher and more consistent input impedance.

The device is specified over the industrial temperature range (–40°C to +85°C).

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類型 標題 日期
* Data sheet 14-Bit, Input-Buffered, 160-MSPS, Analog-to-Digital Converter with JESD204A Outp datasheet (Rev. B) 2013年 10月 4日
EVM User's guide ADS61JBxx EVM User's Guide (Rev. A) 2013年 9月 30日

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韌體

TI-JESD204-IP — JESD204 快速設計 IP，適用連接到 TI 高速資料轉換器的 FPGA

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
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模擬型號

ADS61JBXX IBIS Model

SLOM341.ZIP (110 KB) - IBIS Model
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模擬工具

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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VQFN (RHA) 40 Ultra Librarian
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