ADS8319
- 500-kHz Sample Rate
- 16-Bit Resolution
- Zero Latency at Full Speed
- Unipolar, Single-Ended Input Range: 0 V to VREF
- SPI-Compatible Serial Interface With Daisy-Chain Option
- Excellent Performance:
- 93.6-dB SNR (Typical) at 10-kHz Input
- –106-dB THD (Typical) at 10-kHz Input
- ±1.5-LSB (Maximum) INL
- ±1-LSB (Maximum) DNL
- Low Power Dissipation: 18 mW (Typical) at 500 kSPS
- Power Scales Linearly with Speed: 3.6 mW / 100 kSPS
- Power Dissipation During Power-Down State: 0.25 µW (Typical)
- 10-Pin VSSOP and VSON Packages
The ADS8319 device is a 16-bit, 500-kSPS, analog-to-digital converter (ADC) that operates with a 2.25-V to 5.5-V external reference. The device includes a capacitor-based, successive-approximation register (SAR) ADC with inherent sample and hold.
The device includes a 50-MHz, SPI-compatible serial interface. The interface is designed to support daisy-chaining or cascading of multiple devices. Furthermore, a Busy Indicator makes synchronizing with the digital host easy.
The device unipolar, single-ended input range supports an input swing of 0 V to +VREF.
Device operation is optimized for very-low power operation and the power consumption directly scales with speed. This feature makes the device attractive for lower-speed applications. The device is available in 10-pin VSSOP and VSON packages.
技術文件
設計與開發
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ANALOG-ENGINEER-CALC — PC software analog engineer's calculator
The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)
支援產品和硬體
產品
精密度運算放大器 (Vos<1mV)
一般用途運算放大器
音訊運算放大器
轉阻放大器
高速運算放大器 (GBW ≥ 50 MHz)
功率運算放大器
視訊放大器
線路驅動器
轉導放大器與雷射驅動器
全差分放大器
精確 ADC
生物感測 AFE
高速 ADC (≥10 MSPS)
觸控式螢幕控制器
差分放大器
儀器放大器
音訊線路接收器
類比電流感測放大器
數位電源監測器
配備整合式分流電阻器的類比電流感測放大器
具整合式分流電阻器的數位電源監測器
晶粒與晶圓服務
RF 接收器
RF 發射器
JITTER-SNR-CALC — Jitter and SNR calculator
JITTER-SNR-CALC can be used for calculating theoretical Signal to Noise (SNR) performance of ADCs based on input frequency and clock jitter.
支援產品和硬體
產品
高速 ADC (≥10 MSPS)
精確 ADC
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
支援產品和硬體
產品
系列電壓參考
精確 ADC
生物感測 AFE
整合式精密 ADC 與 DAC
高速 ADC (≥10 MSPS)
精密 DAC (≤10 MSPS)
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
VSON (DRC) | 10 | Ultra Librarian |
VSSOP (DGS) | 10 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。