DAC539E4W
- Quad comparator inputs
- 10-bit independent comparator thresholds
- 1 LSB DNL
- Gains of 1 ×, 1.5 ×, 2 ×, 3 ×, and 4 ×
- Quad general-purpose output (GPO)
- Look-up table (LUT) based comparator-to-GPO mapping
- Automatically detected SPI and I 2C interface
- 1.62-V V IH with V DD = 5.5 V
- MODE pin to select between programming and standalone modes
- User-programmable nonvolatile memory (NVM)
- Reference: internal, external, VDD
- Wide operating range
- Power supply: 1.8 V to 5.5 V
- Temperature range: –40˚C to +125˚C
- Tiny package:
- 16-pin DSBGA: 1.72 mm × 1.72 mm, nominal
The DAC539E4W is 10-bit smart digital-to-analog converters (DACs) with quad programmable comparator inputs and quad general-purpose outputs. A look-up table maps the comparator inputs to the GPOs. The DAC539E4W also supports a programmable delay to allow the input transitions to settle. These devices provide NVM for storing the configurations. This smart DAC functions without the need for a processor ( processor-less operation) using LUT and NVM.
This device has an automatically detected SPI and I 2C interface and an internal reference. The feature set combined with the tiny package and low power make the smart DAC an excellent choice for applications in fault management.
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設計與開發
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ANALOG-ENGINEER-CALC — 類比工程師計算機
除了作為獨立工具使用外,此計算機還與類比工程師口袋參考中描述的概念相得益彰。
ADC-DAC-TO-VREF-SELECT-DESIGN-TOOL — The ADC-TO-VREF-SELECT tool enables the pairing of TI ADCs, DACs, and series voltage references.
支援產品和硬體
產品
系列電壓參考
精確 ADC
生物感測 AFE
整合式精密 ADC 與 DAC
高速 ADC (≥10 MSPS)
精密 DAC (≤10 MSPS)
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PSpice for TI 設計和模擬環境可讓您使用其內建函式庫來模擬複雜的混合訊號設計。在進行佈局和製造之前,建立完整的終端設備設計和解決方案原型,進而縮短上市時間並降低開發成本。
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TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
DSBGA (YBH) | 16 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點