This reference design addresses synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array radar and communication payload. The typical RF front end contains antenna, low-noise amplifier (LNA), mixer, local oscillator (LO) in analog domain and analog-to-digital converter, numerical-controlled oscillator (NCO) and digital down converter (DDC) in digital domain. To achieve overall system synchronization, these digital blocks need to be synchronized with a system clock. This reference design uses ADC12DJ3200 data converter to achieve less than 5-ps channel-to-channel skew across multiple receiver with deterministic latency by synchronizing on-chip NCO with SYNC~ and uses noiseless aperture delay adjustment (tAD Adjust) feature to further reduce skew. This design also provides a very low-phase noise clocking based on LMX2594 wideband PLL and LMK04828 synthesizer and jitter cleaner.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
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Reference design overview and verified performance test data
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Complete listing of design components, reference designators, and manufacturers/part numbers
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Design file that contains information on physical board layer of design PCB
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Reference Design Synchronizing Data Converter DDC and NCO Features for Multi-cha | Jun. 13, 2019 | |
| Application note | JESD204B Multi-Device Synchronization Using LMK0461x | Aug. 16, 2017 | ||
| Analog Design Journal | JESD204B multi-device synchronization: Breaking down the requirements | Apr. 28, 2015 | ||
| Application note | Defining Skew, Propagation-Delay, Phase Offset (Phase Error) | Nov. 28, 2001 |
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