Software
GUI for evaluation module (EVM)
TIDA-01021
Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers
TIDA-01021
Overview
High speed multi-channel applications require precise clocking solutions capable of managing channel-to-channel skew in order to achieve optimal system SNR, SFDR, and ENOB. This reference design is capable of supporting two high speed channels on separate boards by utilizing TI’s LMX2594 wideband PLL with integrated VCOs to generate a 10 MHz to 15 GHz clock and SYSREF for JESD204B interfaces. The 10 KHz offset phase noise is < -104 dBc/Hz for a 15 GHz clock frequency. By using TI’s ADC12DJ3200 high speed converter EVMs, a board-to-board clock skew of <10ps is achieved and a SNR of 49.6 dB with a 5.25 GHz input signal. All key design theories are described, guiding users through the part selection process and design optimization. Finally, schematic, board layout, hardware testing, and results are also presented.
Features
- Up to 15GHz sample clock generation
- Multi-channel JESD204B compliant clock solution
- Low phase noise clocking for RF sampling ADC/DAC
- Configurable phase synchronization to achieve low skew in multi-channel system
- Supports TI’s high-speed converter and capture cards (ADC12DJ3200EVM, TSW14J56 / TSW14J57)
Communications equipment
Industrial
- Air Circuit Breaker (ACB)
- Aircraft cockpit display
- Complete radar system
- Defense radio
- Digital multimeter (DMM) - benchtop
- Digitizer (>= 50MSPS)
- Electronic warfare
- Global positioning system receiver
- Interconnect/distribution box
- Laser distance meter
- Laser guidance
- Oscilloscope (DSO) - benchtop
- Oscilloscope (DSO) - modular
- Radar guidance
- Spectrum analyzer
- Vector signal transceiver (VST)
- Wireless communications test
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDUD80A.PDF (2105 K)
Reference design overview and verified performance test data
TIDRR75A.PDF (1786 K)
Detailed schematic diagram for design layout and components
TIDRR76A.PDF (696 K)
Detailed schematic diagram for design layout and components
TIDRR77A.PDF (193 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRR78A.PDF (44 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDRR79A.PDF (1084 K)
Detailed overview of design layout for component placement
TIDRR80A.PDF (644 K)
Detailed overview of design layout for component placement
TIDRR83A.ZIP (8944 K)
Files used for 3D models or 2D drawings of IC components
TIDRR84A.ZIP (7976 K)
Files used for 3D models or 2D drawings of IC components
TIDCDH9A.ZIP (6571 K)
Design file that contains information on physical board layer of design PCB
TIDCDI0A.ZIP (2080 K)
Design file that contains information on physical board layer of design PCB
TIDRR81A.PDF (7470 K)
PCB layer plot file used for generating PCB design layout
TIDRR82A.PDF (4389 K)
PCB layer plot file used for generating PCB design layout
Products
Includes TI products in the design and potential alternatives.
Analog switches & muxes
SN74CBTLV3257 — 3.3-V, 2:1 (SPDT), 4-channel analog switch with partial-power-down mode
Data sheet: PDF | HTMLHigh-speed ADCs (≥10 MSPS)
ADC08DJ3200 — 8-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC)
Data sheet: PDF | HTMLHigh-speed ADCs (≥10 MSPS)
ADC12DJ2700 — 12-bit, dual 2.7-GSPS or single 5.4-GSPS, RF-sampling analog-to-digital converter (ADC)
Data sheet: PDF | HTMLHigh-speed ADCs (≥10 MSPS)
ADC12DJ3200 — 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)
Data sheet: PDF | HTMLLVDS, M-LVDS & PECL ICs
DS90LV028AQ-Q1 — Automotive LVDS dual differential line receiver
Data sheet: PDF | HTMLMOSFETs
CSD15571Q2 — 20-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm
Data sheet: PDFNoninverting buffers & drivers
SN74LVC1G125 — Single 1.65-V to 5.5-V buffer with 3-state outputs
Data sheet: PDF | HTMLStart development
Technical documentation
= Top documentation selected by TI
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | Design guide | Multichannel JESD204B 15-GHz Clocking Reference Design (Rev. A) | Jun. 14, 2017 | |
| Technical article | Step-by-step considerations for designing wide-bandwidth multichannel systems | PDF | HTML | Jun. 04, 2019 | |
| Technical article | Preparing for 5G applications: sync your multichannel JESD204B data acquisition sy | PDF | HTML | Aug. 28, 2017 |
Related design resources
Hardware development
EVALUATION BOARD
Reference designs
REFERENCE DESIGN
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