TIDA-01022

Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems

TIDA-01022

Design files

Overview

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew and deterministic latency. This reference design demonstrates multi-channel AFE and clock solution using high speed data converters with JESD204B, high speed amplifiers, high performance clocks and low noise power solutions to achieve optimum system performance

Features
  • 3.2 Gsps, 1.5 GHz multi- channel high speed analog front for high performance receiver
  • < 5 ps clock skew between channels
  • Multi-channel JESD204B complaint clock solution
  • Scalable platform for pin compatible ADC12DJxx00 family
  • Supports TI’s high-speed converter and capture cards (TSW14J56 / TSW14J57)
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

PDF | HTML
TIDUDA6A.PDF (3004 K)

Reference design overview and verified performance test data

TIDRUT6.PDF (5000 K)

Detailed schematic diagram for design layout and components

TIDRUT7.PDF (132 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDRUT8.PDF (3076 K)

Detailed overview of design layout for component placement

TIDRUU0.ZIP (69995 K)

Files used for 3D models or 2D drawings of IC components

TIDCEB2.ZIP (7572 K)

Design file that contains information on physical board layer of design PCB

TIDRUT9.ZIP (14285 K)

PCB layer plot file used for generating PCB design layout

Products

Includes TI products in the design and potential alternatives.

AND gates

SN74LVC1G081-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate

Data sheet: PDF
Analog switches & muxes

SN74LVC2G535-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package)

Data sheet: PDF | HTML
Clock buffers

LMK003043.1-GHz differential clock buffer/level translator with 4 configurable outputs

Data sheet: PDF | HTML
Clock jitter cleaners

LMK04828Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.

Data sheet: PDF | HTML
Comparators

LMC6762Dual Micro-Power Rail-to-Rail Input CMOS Comparator with Push-Pull Output

Data sheet: PDF
Digital temperature sensors

LM95233±2°C Dual Remote and Local Temperature Sensor with TruTherm Technology and SMBus Interface

Data sheet: PDF
Direction-controlled voltage translators

SN74AVC4T774Four-bit dual-supply bus transceiver with configurable voltage-level shifting and tri-state outputs

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC08DJ32008-Bit, Dual 3.2-GSPS or Single 6.4-GSPS, RF-Sampling Analog-to-Digital Converter (ADC)

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC12DJ270012-bit, dual 2.7-GSPS or single 5.4-GSPS, RF-sampling analog-to-digital converter (ADC)

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADC12DJ320012-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling analog-to-digital converter (ADC)

Data sheet: PDF | HTML
High-speed op amps (GBW ≥ 50 MHz)

BUF802Wide-bandwidth, 2.3-nV/√Hz, high-input impedance JFET buffer

Data sheet: PDF | HTML
I2C general-purpose I/Os (GPIOs)

TCA9534A8-bit 1.65- to 5.5-V I2C/SMBus I/O expander with interrupt, & config registers

Data sheet: PDF | HTML
LVDS, M-LVDS & PECL ICs

DS90LT012AQ-Q1Automotive LVDS differential line receiver

Data sheet: PDF
LVDS, M-LVDS & PECL ICs

DS90LV028AQ-Q1Automotive LVDS dual differential line receiver

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TLV702300-mA, high-PSRR, low-IQ, low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A331-A, high-PSRR, negative, adjustable low-dropout voltage regulator with enable

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A83002-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi

Data sheet: PDF | HTML
Linear & low-dropout (LDO) regulators

TPS7A843-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good with high-accuracy

Data sheet: PDF | HTML
MOSFETs

CSD15571Q220-V, N channel NexFET™ power MOSFET, single SON 2 mm x 2 mm, 19.2 mOhm

Data sheet: PDF
Noninverting buffers & drivers

SN74LVC1G125Single 1.65-V to 5.5-V buffer with 3-state outputs

Data sheet: PDF | HTML
Oscillators

LMK61E2156.250-MHz, ±50 ppm, ultra-low jitter, integrated EEPROM, fully programmable oscillator

Data sheet: PDF | HTML
Power modules (integrated inductor)

TPS8213017-V input 3-A step-down converter module with integrated inductor

Data sheet: PDF | HTML
RF FDAs

LMH54018-GHz Ultra wideband fully differential amplifier

Data sheet: PDF | HTML
RF PLLs & synthesizers

LMX259415-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support

Data sheet: PDF | HTML
RF VGAs

LMH64014.5 GHz ultra wideband digital variable gain amplifier

Data sheet: PDF | HTML
eFuses & hot swap controllers

TPS259264.5-V to 13.8-V, 30mΩ, 2-5A eFuse

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* Design guide Flexible 3.2-GSPS Multichannel AFE Reference Design for DSOs, RADAR, and 5G (Rev. A) PDF | HTML Jan. 21, 2022
Technical article Step-by-step considerations for designing wide-bandwidth multichannel systems PDF | HTML Jun. 04, 2019

Related design resources

Hardware development

EVALUATION BOARD
ADC12DJ3200EVM ADC12DJ3200 12-bit, dual 3.2-GSPS or single 6.4-GSPS, RF-sampling ADC evaluation module TSW14J57EVM Data capture/pattern generator: data converter EVM with 16 JESD204B lanes from 1.6-15Gbps

Reference designs

REFERENCE DESIGN
TIDA-01021 Multi-channel JESD204B 15-GHz clocking reference design for DSO, radar and 5G wireless testers TIDA-01023 High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers TIDA-01024 High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

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