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CDCEL949

現行

具 1.8-V LVCMOS 輸出的可編程 4-PLL VCXO 時脈合成器

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產品規格表

CDCEL949

現行
產品規格表 立即訂購

產品詳細資料

Function Clock synthesizer Number of outputs 9 Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type XTAL Output type LVCMOS Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
Function Clock synthesizer Number of outputs 9 Output frequency (max) (MHz) 230 Core supply voltage (V) 1.8 Output supply voltage (V) 1.8 Input type XTAL Output type LVCMOS Operating temperature range (°C) -40 to 85 Features Integrated EEPROM, Multiplier or divider, Spread-spectrum clocking (SSC) Rating Catalog
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4
  • Member of programmable clock generator family
    • CDCEx913: 1 PLLs, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-System programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)
  • Member of programmable clock generator family
    • CDCEx913: 1 PLLs, 3 outputs
    • CDCEx925: 2 PLLs, 5 outputs
    • CDCEx937: 3 PLLs, 7 outputs
    • CDCEx949: 4 PLLs, 9 outputs
  • In-System programmability and EEPROM
    • Serial programmable volatile register
    • Nonvolatile EEPROM to store customer settings
  • Flexible input clocking concept
    • External crystal: 8MHz to 32MHz
    • On-chip VCXO pull-range: ±150ppm
    • Single-ended LVCMOS up to 160MHz
  • Free selectable output frequency up to 230MHz
  • Low-noise PLL core
    • PLL loop filter components integrated
    • Low period jitter: 60ps (typical)
  • Separate output supply pins
    • CDCE949: 3.3V and 2.5V
    • CDCEL949: 1.8V
  • Flexible clock driver
    • Three user-definable control inputs [S0/S1/S2] (for example: SSC selection, frequency switching, output enable or power down)
    • Generates highly accurate clocks for video, audio, USB, IEEE1394, RFID, Bluetooth, WLAN, Ethernet™, and GPS
    • Generates common clock frequencies used with TI-DaVinci™, OMAP™, DSPs
    • Programmable SSC modulation
    • Enables 0ppm clock generation
  • 1.8V device core supply
  • Wide temperature range: –40°C to 85°C
  • Packaged in TSSOP
  • Development and programming kit for easy PLL design and programming (TI Pro-Clock™)

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. These devices generate up to nine output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.

The CDCEx949 operates in a 1.8V environment within a temperature range of –40°C to 85°C.

The CDCE949 and CDCEL949 are modular PLL-based low cost, high-performance, programmable clock synthesizers, multipliers and dividers. These devices generate up to nine output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230MHz, using up to four independent configurable PLLs.

The CDCEx949 has separate output supply pins (VDDOUT): 1.8V for the CDCEL949 and 2.5V to 3.3V for the CDCE949.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0pF to 20pF. Additionally, an on-chip VCXO is selectable, allowing synchronization of the output frequency to an external control signal, that is, a PWM signal.

The deep M/N divider ratio allows the generation of 0ppm audio or video, networking (WLAN, BlueTooth™, Ethernet, GPS) or Interface (USB, IEEE1394, Memory Stick) clocks from a reference input frequency, such as 27MHz.

All PLLs support SSC (Spread-Spectrum Clocking). SSC can be Center-Spread or Down-Spread clocking. This is a common technique to reduce electro-magnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop-filter components are automatically adjusted to achieve high stability, and to optimize the jitter-transfer characteristics of each PLL.

The device supports non-volatile EEPROM programming for easy customization of the device to the application. The CDCEx949 is preset to a factory-default configuration. The device can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA and SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1 and S2, can be used to control various aspects of operation including frequency selection, changing the SSC parameters to lower EMI, PLL bypass, power down, and choosing between low level or 3-state for the output-disable function.

The CDCEx949 operates in a 1.8V environment within a temperature range of –40°C to 85°C.
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類型 標題 日期
* Data sheet CDCE(L)949: Flexible Low Power LVCMOS Clock Generator With SSC Support for EMI Reduction datasheet (Rev. G) PDF | HTML 2024年 1月 16日
Application note VCXO Application Guideline for CDCE(L)9xx Family (Rev. A) 2012年 4月 23日
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual (Rev. A) 2010年 11月 22日
User guide CDCE(L)9xx Performance Evaluation Module (Rev. A) 2010年 7月 7日
Application note Troubleshooting I2C Bus Protocol 2009年 10月 19日
Application note Usage of I2C for CDCE(L)949, CDCE(L)937, CDCE(L)925, CDCE(L)913 2009年 9月 23日
User guide CDCE(L)9XX & CDCEx06 Programming Evaluation Module Manual 2008年 12月 9日
Application note Generating Low Phase-Noise Clocks for Audio Data Converters from Low Frequency 2008年 3月 31日
Application note Practical consideration on choosing a crystal for CDCE(L)9xx family 2008年 3月 24日

設計與開發

如需其他條款或必要資源，請按一下下方的任何標題以檢視詳細頁面 (如有)。

開發板

CDCEL949PERF-EVM — CDCEL949 性能評估模組

The CDCEL949PERF-EVM will help to verify the functionality and performance of CDCEL949 with the options of crystal and 1.8 V LVCMOS inputs. The outputs can be connected to the Oscilloscope directly with SMA cables. The below information/items are included: The EVM use's guide : SCAU022; the (...)

使用指南: PDF
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開發板

CDCEL9XXPROGEVM — CDCE(L)949 系列 EEPROM 程式設計基板

The clock generator CDCE(L)949 family has integrated EEPROM that allows the default frequency settings to be saved upon start up. CDCEL9XXPROGEVM is a programming board that allows a fast programming of prototyping samples or small production quantities. It applies to all 8 devices in the family: (...)

使用指南: PDF
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驅動程式或資料庫

SCAC131 — Drivers for the CDCEL9xx programmer EVM

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支援產品和硬體

產品
時鐘產生器
CDCE913 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 1-PLL VCXO 時脈合成器 CDCE925 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 2-PLL VCXO 時脈合成器 CDCE937 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 3-PLL VCXO 時脈合成器 CDCE949 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 4-PLL VCXO 時脈合成器 CDCEL913 — 具 1.8-V LVCMOS 輸出的可編程 1-PLL VCXO 時脈合成器 CDCEL925 — 具 1.8-V LVCMOS 輸出的可編程 2-PLL VCXO 時脈合成器 CDCEL937 — 具 1.8-V LVCMOS 輸出的可編程 3-PLL VCXO 時脈合成器 CDCEL949 — 具 1.8-V LVCMOS 輸出的可編程 4-PLL VCXO 時脈合成器
硬體開發
開發板
CDCE906-706PROGEVM — CDCE906 和 CDCE706 可編程 EVM CDCE925PERF-EVM — CDCE925 性能評估模組 CDCE949PERF-EVM — CDCE949 性能評估模組 CDCEL913PERF-EVM — CDCEL913 性能評估模組 CDCEL925PERF-EVM — CDCEL925 性能評估模組 CDCEL949PERF-EVM — CDCEL949 性能評估模組
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支援軟體

CLOCKPRO — ClockPro Software

TI's ClockPro software allows users to program/configure the following devices in a friendly GUI interface:

  • CDCE949
  • CDCE937
  • CDCE925
  • CDCE913
  • CDCE906
  • CDCE706
  • CDCEL949
  • CDCEL937
  • CDCEL925
  • CDCEL913

It is intended to be used with the evaluation modules of the above devices.

支援產品和硬體

支援產品和硬體

產品
時鐘產生器
CDCE706 — 300-MHz、LVCMOS、可編程的 3-PLL 時脈合成器/倍頻器/分頻器 CDCE906 — 167-MHz、LVCMOS、可編程的 3-PLL 時脈合成器/倍頻器/分頻器 CDCE913 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 1-PLL VCXO 時脈合成器 CDCE925 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 2-PLL VCXO 時脈合成器 CDCE937 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 3-PLL VCXO 時脈合成器 CDCE949 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 4-PLL VCXO 時脈合成器 CDCEL913 — 具 1.8-V LVCMOS 輸出的可編程 1-PLL VCXO 時脈合成器 CDCEL925 — 具 1.8-V LVCMOS 輸出的可編程 2-PLL VCXO 時脈合成器 CDCEL937 — 具 1.8-V LVCMOS 輸出的可編程 3-PLL VCXO 時脈合成器 CDCEL949 — 具 1.8-V LVCMOS 輸出的可編程 4-PLL VCXO 時脈合成器
硬體開發
開發板
CDCE906-706PROGEVM — CDCE906 和 CDCE706 可編程 EVM CDCE913PERF-EVM — CDCE913 性能評估模組 CDCE925PERF-EVM — CDCE925 性能評估模組 CDCE949PERF-EVM — CDCE949 性能評估模組 CDCEL913PERF-EVM — CDCEL913 性能評估模組 CDCEL925PERF-EVM — CDCEL925 性能評估模組 CDCEL949PERF-EVM — CDCEL949 性能評估模組 CDCEL9XXPROGEVM — CDCE(L)949 系列 EEPROM 程式設計基板
軟體
軟體程式設計工具
CLOCKPRO — ClockPro™ 程式設計軟體
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支援軟體

SCAC073 — TI-Pro-Clock Programming Software

支援產品和硬體

支援產品和硬體

產品
時鐘產生器
CDC706 — 200-MHz、LVCMOS、客製編程的 3-PLL 時脈合成器、倍頻器和分頻器 CDC906 — 167-MHz、LVCMOS、客製編程的 3-PLL 時脈合成器、倍頻器和分頻器 CDCE706 — 300-MHz、LVCMOS、可編程的 3-PLL 時脈合成器/倍頻器/分頻器 CDCE906 — 167-MHz、LVCMOS、可編程的 3-PLL 時脈合成器/倍頻器/分頻器 CDCE913 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 1-PLL VCXO 時脈合成器 CDCE925 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 2-PLL VCXO 時脈合成器 CDCE937 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 3-PLL VCXO 時脈合成器 CDCE949 — 具 2.5-V 或 3.3-V LVCMOS 輸出的可編程 4-PLL VCXO 時脈合成器 CDCEL913 — 具 1.8-V LVCMOS 輸出的可編程 1-PLL VCXO 時脈合成器 CDCEL925 — 具 1.8-V LVCMOS 輸出的可編程 2-PLL VCXO 時脈合成器 CDCEL937 — 具 1.8-V LVCMOS 輸出的可編程 3-PLL VCXO 時脈合成器 CDCEL949 — 具 1.8-V LVCMOS 輸出的可編程 4-PLL VCXO 時脈合成器
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設計工具

CLOCK-TREE-ARCHITECT — 時鐘樹架構程式設計軟體

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
要求
封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 24 Ultra Librarian
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